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2019-03-20drm/amd/powerplay: Zero initialize num_of_levels in vega20_set_single_dpm_tableNathan Chancellor1-1/+1
When building with -Wsometimes-uninitialized, Clang warns: drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:456:2: warning: variable 'num_of_levels' is used uninitialized whenever '?:' condition is false [-Wsometimes-uninitialized] smu_read_smc_arg(smu, &num_of_levels); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:608:3: note: expanded from macro 'smu_read_smc_arg' ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0) ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:457:7: note: uninitialized use occurs here if (!num_of_levels) { ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:456:2: note: remove the '?:' if its condition is always true smu_read_smc_arg(smu, &num_of_levels); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:608:3: note: expanded from macro 'smu_read_smc_arg' ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0) ^ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:446:27: note: initialize the variable 'num_of_levels' to silence this warning uint32_t i, num_of_levels, clk; ^ = 0 1 warning generated. The if statement it mentions as potentially problematic is currently always true because the read_smc_arg callback is assigned at the bottom of this file but Clang can't tell that. If the callback were ever to disappear, num_of_levels would never be initialized. Just zero initialize it to ensure that the intent behind this code remains the same. Link: https://github.com/ClangBuiltLinux/linux/issues/425 Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/ttm: remove set but not used variable 'rdev'YueHaibing1-4/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_move_vram_ram': drivers/gpu/drm/radeon/radeon_ttm.c:254:24: warning: variable 'rdev' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_move_ram_vram': drivers/gpu/drm/radeon/radeon_ttm.c:301:24: warning: variable 'rdev' set but not used [-Wunused-but-set-variable] It's not used since a987fcaa805f ("ttm: Make parts of a struct ttm_bo_device global.") Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Only put primary planes into the mode_info->planes listNicholas Kazlauskas1-10/+9
We want DRM planes to be initialized in the following order: - primary planes - overlay planes - cursor planes to support existing userspace expectations for plane z-ordering. This means that we also need to register CRTCs after all planes have been initialized since overlay planes can be placed on any CRTC. So the only reason why we have the mode_info->planes list is to remember the primary planes for use later when we need to register the CRTC. Overlay planes have no purpose being in this list. DRM will cleanup any planes that we've registered for us, so the only planes that need to be explicitly cleaned up are the ones that have failed to register. By dropping the explicit free on every plane in the mode_info->planes list this patch also fixes a double-free in the case where we fail to initialize only some of the planes. Cc: Leo Li <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Add debugfs dpcd interfaceDavid Francis3-1/+112
[Why] We need arbitrary read/write over DP AUX DPCD for debugging [How] Three debugfs entries Set the target address by writing to "aux_dpcd_address" (The first four bytes written are used) Set the transaction size in bytes by writing to "aux_dpcd_size" (The first four bytes written are used) Start a transaction by reading/writing "aux_dpcd_data" Do note: there is no concerrency protection at all Accessing these entries in quick succession can lead to strange behaviour Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Generic SDP message access in amdgpuLeo (Hanghong) Ma1-1/+49
[Why] We need to add DP SDP message test debugfs to make sdp message test more convenient and efficient. [How] Add sdp_message debugfs entry in amdgpu. Signed-off-by: Leo (Hanghong) Ma <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Expose generic SDP message access interfaceLeo (Hanghong) Ma5-1/+97
[Why] We need to add DP SDP message test debugfs to make sdp message test more convenient and efficient. [How] Add a DM accessible SDP interface for custom data. Signed-off-by: Leo (Hanghong) Ma <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: fix odm pipe managementDmytro Laktyushkin2-7/+53
There are issues removing surfaces/streams when odm is active. This is a step to fix that Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: add missing opp programming for odmDmytro Laktyushkin3-8/+6
A number of places opp programming was missing for odm second pipe. This change fixes the oversight. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: fix odm combine pipe resetDmytro Laktyushkin1-4/+2
We fail to reset the second odm combine pipe. This change fixes odm pointer management. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: fix releasing planes when exiting odmDmytro Laktyushkin1-2/+4
Releasing planes should not release the 2nd odm pipe right away, this change leaves us with 2 pipes with null planes and same stream when planes are released during odm. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: 3.2.23Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Fix VTEM InfoPacket programmingReza Amini1-33/+111
Refactor setting bit fields. Correcting the offset of MD0. Initializing the InfoPacket header fields. Defining the field offsets and masks. Signed-off-by: Reza Amini <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Link train only when link is DP and backend is enabledSamson Tam1-1/+12
[Why] In certain cases we do link training when we don't have a backend. [How] In dc_link_set_preferred_link_settings(), store preferred link settings first and then verify that the link is DP and the link stream's backend is enabled. If either is false, then we will not do any link retraining. Signed-off-by: Samson Tam <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: add global master update lock interfacesWenjing Liu2-0/+6
Add these interfacese for future use setup_global_lock() lock_global() pipe_control_lock_global() Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Use dc_is_hdmi_signal() instead of ENUMEric Bernstein2-3/+2
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: cache additional dpcd caps for HDR capability checkHarmanprit Tatla3-5/+50
[Why] Currently we are missing a few checks to see if HDR10 is allowed. In particular we never check for the extended colorimetry bit (whether its present or set to 1). Further we don't read in the dpcd block in DC that would provide these bits. [How] - Added in DC code to read in the block containing the extended colorimetry bit. Signed-off-by: Harmanprit Tatla <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Update ABM crtc state on non-modesetDavid Francis1-0/+3
[Why] Somewhere in the atomic check reshuffle ABM got lost. ABM is a crtc property (copied from a connector property). It can change without a modeset, just like underscan. [How] In the skip_modeset branch of atomic check crtc updates, copy over the abm property. Signed-off-by: David Francis <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Programming correct VRR_EN bit in VTEM structureHugo Hu1-2/+2
[Why] In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0. VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3. [How] Programming correct VRR_EN bit in EMP-MD0-bit0. Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Reza Amini <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: 3.2.22Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: extend EDID support to 1kbJun Lei1-1/+1
[why] There exist displays with EDIDs > 512 bytes, existing code will cause us to ignore all extension blocks. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Fix DP audio regressionWesley Chalmers1-3/+2
Audio was unmuted for HDMI only, need to do so for DP as well. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Chris Park <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Add a hysteresis to BTR frame multiplierAric Cyr1-2/+22
[Why] Flickering is observed on some displays when the number of inserted BTR frames changes frequently. [How] Add in a margin of drift to prevent the inserted number of frames from jumping around too frequently. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: fix DP 422 VID_M half the rate issue.Charlene Liu5-9/+31
[Description] when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N. for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Fix setting DP_VID_N_MULEric Bernstein3-4/+11
[Why] Need to set VID_N_MUL for 4:2:0 cases [How] Move setting to enc1_stream_encoder_dp_unblank and ensure it is also set for non-4:2:0 cases. Signed-off-by: Eric Bernstein <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Move dm_read_reg_func to dc_helper.Yongqiang Sun2-17/+22
Move out of header to dc_helper.c, in preparation for future implementations. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Use drm helper for resetting plane stateNicholas Kazlauskas1-7/+2
[Why] To help prevent plane state not being set to the correct default value if any new properties are added in the future. [How] Use the drm helper - which seems to be the common solution among other DRM drivers. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: change generic_reg_wait to void.Yongqiang Sun3-6/+5
we were only checking the return value in one place, thus changing generic_reg_wait from int to void and reading the register instead of getting it from generic_reg_wait, when we need the return value. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Reset alpha state for planes to the correct valuesNicholas Kazlauskas1-0/+2
[Why] The plane_reset callback is subclassed but hasn't been updated since the drm helper got updated to include resetting alpha related state (state->alpha and state->pixel_blend_mode). The overlay planes exposed by amdgpu_dm were therefore being rendered as invisible by default ever since supported was exposed for alpha blending properties on overlays. This caused regressions in igt@kms_plane_multiple@atomic-tiling-none and igt@kms_plane@plane-position-covered-pipe tests. [How] Reset the plane state values to their correct values as defined in the drm helper. This fixes the IGT test regression. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: use more entries for the first paging queueChristian König1-0/+2
To aid recoverable page faults. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: free up the first paging queue v2Christian König1-8/+14
We need the first paging queue to handle page faults. v2: handle any number of SDMA instances gracefully Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: re-enable retry faultsChristian König2-2/+2
Now that we have re-reoute faults to the other IH ring we can enable retries again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdkfd/sriov:Put the pre and post reset in exclusive mode v2Wentao Lou1-0/+3
add amdgpu_amdkfd_pre_reset and amdgpu_amdkfd_post_reset inside amdgpu_device_reset_sriov. Signed-off-by: Wentao Lou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Respect DRM framebuffer info for video surfacesNicholas Kazlauskas1-11/+10
[Why] Incorrect hardcoded assumptions are made regarding luma and chroma alignment. The actual values set for the DRM framebuffer should be used when programming the address. [How] Respect the given pitch for both luma and chroma planes - it's not like we can force the alignment to anything else at this point anyway. Use the FB offset for the chroma planes directly. DRM already provides this to us so there's no need to calculate it manually. While we don't actually use the chroma surface size parameters on Raven, these should have technically been fb->width / 2 and fb->height / 2 since the chroma plane is half size of the luma plane for NV12. Leave a TODO indicating that those should be set based on the actual surface format instead since this is only correct for YUV420 formats. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: Wait for newly allocated PTs to be idleFelix Kuehling1-7/+13
When page table are updated by the CPU, synchronize with the allocation and initialization of newly allocated page tables. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: more descriptive message if HMM not enabledPhilip Yang1-0/+2
If using old kernel config file, CONFIG_ZONE_DEVICE is not selected, so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver error message "Failed to register MMU notifier" is not clear. Inform user with more descriptive message on how to fix the missing kernel config option. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808 Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-21drm/exynos/mixer: fix MIXER shadow registry synchronisation codeAndrzej Hajda1-44/+66
MIXER on Exynos5 SoCs uses different synchronisation method than Exynos4 to update internal state (shadow registers). Apparently the driver implements it incorrectly. The rule should be as follows: - do not request updating registers until previous request was finished, ie. MXR_CFG_LAYER_UPDATE_COUNT must be 0. - before setting registers synchronisation on VSYNC should be turned off, ie. MXR_STATUS_SYNC_ENABLE should be reset, - after finishing MXR_STATUS_SYNC_ENABLE should be set again. The patch hopefully implements it correctly. Below sample kernel log from page fault caused by the bug: [ 25.670038] exynos-sysmmu 14650000.sysmmu: 14450000.mixer: PAGE FAULT occurred at 0x2247b800 [ 25.677888] ------------[ cut here ]------------ [ 25.682164] kernel BUG at ../drivers/iommu/exynos-iommu.c:450! [ 25.687971] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM [ 25.693778] Modules linked in: [ 25.696816] CPU: 5 PID: 1553 Comm: fb-release_test Not tainted 5.0.0-rc7-01157-g5f86b1566bdd #136 [ 25.705646] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 25.711710] PC is at exynos_sysmmu_irq+0x1c0/0x264 [ 25.716470] LR is at lock_is_held_type+0x44/0x64 v2: added missing MXR_CFG_LAYER_UPDATE bit setting in mixer_enable_sync Reported-by: Marian Mihailescu <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2019-03-20scsi: ibmvscsi: Fix empty event pool access during host removalTyrel Datwyler1-6/+16
The event pool used for queueing commands is destroyed fairly early in the ibmvscsi_remove() code path. Since, this happens prior to the call so scsi_remove_host() it is possible for further calls to queuecommand to be processed which manifest as a panic due to a NULL pointer dereference as seen here: PANIC: "Unable to handle kernel paging request for data at address 0x00000000" Context process backtrace: DSISR: 0000000042000000 ????Syscall Result: 0000000000000000 4 [c000000002cb3820] memcpy_power7 at c000000000064204 [Link Register] [c000000002cb3820] ibmvscsi_send_srp_event at d000000003ed14a4 5 [c000000002cb3920] ibmvscsi_send_srp_event at d000000003ed14a4 [ibmvscsi] ?(unreliable) 6 [c000000002cb39c0] ibmvscsi_queuecommand at d000000003ed2388 [ibmvscsi] 7 [c000000002cb3a70] scsi_dispatch_cmd at d00000000395c2d8 [scsi_mod] 8 [c000000002cb3af0] scsi_request_fn at d00000000395ef88 [scsi_mod] 9 [c000000002cb3be0] __blk_run_queue at c000000000429860 10 [c000000002cb3c10] blk_delay_work at c00000000042a0ec 11 [c000000002cb3c40] process_one_work at c0000000000dac30 12 [c000000002cb3cd0] worker_thread at c0000000000db110 13 [c000000002cb3d80] kthread at c0000000000e3378 14 [c000000002cb3e30] ret_from_kernel_thread at c00000000000982c The kernel buffer log is overfilled with this log: [11261.952732] ibmvscsi: found no event struct in pool! This patch reorders the operations during host teardown. Start by calling the SRP transport and Scsi_Host remove functions to flush any outstanding work and set the host offline. LLDD teardown follows including destruction of the event pool, freeing the Command Response Queue (CRQ), and unmapping any persistent buffers. The event pool destruction is protected by the scsi_host lock, and the pool is purged prior of any requests for which we never received a response. Finally, move the removal of the scsi host from our global list to the end so that the host is easily locatable for debugging purposes during teardown. Cc: <[email protected]> # v2.6.12+ Signed-off-by: Tyrel Datwyler <[email protected]> Signed-off-by: Martin K. Petersen <[email protected]>
2019-03-20scsi: ibmvscsi: Protect ibmvscsi_head from concurrent modificaitonTyrel Datwyler1-0/+5
For each ibmvscsi host created during a probe or destroyed during a remove we either add or remove that host to/from the global ibmvscsi_head list. This runs the risk of concurrent modification. This patch adds a simple spinlock around the list modification calls to prevent concurrent updates as is done similarly in the ibmvfc driver and ipr driver. Fixes: 32d6e4b6e4ea ("scsi: ibmvscsi: add vscsi hosts to global list_head") Cc: <[email protected]> # v4.10+ Signed-off-by: Tyrel Datwyler <[email protected]> Signed-off-by: Martin K. Petersen <[email protected]>
2019-03-20drm/i915: make raw access function work on uncoreDaniele Ceraolo Spurio3-54/+57
This allows us to ditch i915 in some more places. v2: use local var in check_vgpu (Paulo) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: move regs pointer inside the uncore structureDaniele Ceraolo Spurio7-68/+75
This will allow futher simplifications in the uncore handling. v2: move register access setup under uncore (Chris) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: reduce the dev_priv->uncore dance in uncore.cDaniele Ceraolo Spurio1-36/+43
Use a local variable where it makes sense. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: make find_fw_domain work on intel_uncoreDaniele Ceraolo Spurio1-10/+10
Remove unneeded usage of dev_priv from 1 extra function. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: make more uncore function work on intel_uncoreDaniele Ceraolo Spurio6-156/+159
Move the init, fini, prune, suspend, resume function to work on intel_uncore instead of dev_priv. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: use intel_uncore for all forcewake get/putDaniele Ceraolo Spurio17-115/+107
Now that the internal code all works on intel_uncore, flip the external-facing interface. v2: fix GVT. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20drm/i915: use intel_uncore in fw get/put internal pathsDaniele Ceraolo Spurio6-108/+121
Get/put functions used outside of uncore.c are updated in the next patch for a nicer split. v2: use dev_priv where we still have it (Paulo) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20blkcg: Fix kernel-doc warningsBart Van Assche1-4/+5
Avoid that the following warnings are reported when building with W=1: block/blk-cgroup.c:1755: warning: Function parameter or member 'q' not described in 'blkcg_schedule_throttle' block/blk-cgroup.c:1755: warning: Function parameter or member 'use_memdelay' not described in 'blkcg_schedule_throttle' block/blk-cgroup.c:1779: warning: Function parameter or member 'blkg' not described in 'blkcg_add_delay' block/blk-cgroup.c:1779: warning: Function parameter or member 'now' not described in 'blkcg_add_delay' block/blk-cgroup.c:1779: warning: Function parameter or member 'delta' not described in 'blkcg_add_delay' Signed-off-by: Bart Van Assche <[email protected]> Signed-off-by: Jens Axboe <[email protected]>
2019-03-20drm/i915: always use masks on FW regsDaniele Ceraolo Spurio2-32/+16
Upper bits are reserved on gen6, so no issue if we write them. Note that we're already doing this in the non-MT case of IVB, which uses the same register. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-20blk-iolatency: #include "blk.h"Bart Van Assche1-0/+1
This patch avoids that the following warning is reported when building with W=1: block/blk-iolatency.c:734:5: warning: no previous prototype for 'blk_iolatency_init' [-Wmissing-prototypes] Cc: Josef Bacik <[email protected]> Fixes: d70675121546 ("block: introduce blk-iolatency io controller") # v4.19 Signed-off-by: Bart Van Assche <[email protected]> Signed-off-by: Jens Axboe <[email protected]>
2019-03-20block: Unexport blk_mq_add_to_requeue_list()Bart Van Assche3-3/+2
This function is not used outside the block layer core. Hence unexport it. Cc: Christoph Hellwig <[email protected]> Cc: Ming Lei <[email protected]> Signed-off-by: Bart Van Assche <[email protected]> Signed-off-by: Jens Axboe <[email protected]>
2019-03-20block: add BLK_MQ_POLL_CLASSIC for hybrid poll and return EINVAL for ↵Yufen Yu3-7/+12
unexpected value For q->poll_nsec == -1, means doing classic poll, not hybrid poll. We introduce a new flag BLK_MQ_POLL_CLASSIC to replace -1, which may make code much easier to read. Additionally, since val is an int obtained with kstrtoint(), val can be a negative value other than -1, so return -EINVAL for that case. Thanks to Damien Le Moal for some good suggestion. Reviewed-by: Damien Le Moal <[email protected]> Signed-off-by: Yufen Yu <[email protected]> Signed-off-by: Jens Axboe <[email protected]>
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