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Use the r8a7790 timer init function on Lager
to make sure the architected timer is started
regardless of boot loader setting.
Signed-off-by: Magnus Damm <[email protected]>
Tested-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Implement a SoC-specific timer init function for
r8a7790 that makes sure the architected timer
is started regardless of boot loader setting.
Signed-off-by: Magnus Damm <[email protected]>
Tested-by: Kuninori Morimoto <[email protected]
Signed-off-by: Simon Horman <[email protected]>
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Add the GPIO I/O memory range to the r8a7790 PFC device.
This extra I/O memory range is needed when using the PFC
tables to drive both pin functions (using PINCTRL or
function GPIO for old code) and actual GPIO. The goal is
however to use a separate GPIO driver in the long run
and when that happens this extra I/O memory range can
be removed.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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MMCIF and SDHI1 share the same slot on mackerel. One of them is selected
by a jumper, which cannot be queried from software. Currently in software
one of the two interfaces is selected, depending whether or not the MMCIF
driver is enabled. This is not optimal, since the kernel has to be rebuilt
to switch from one interface to another. Still, so far there isn't a
better option. At least make this selection consistent.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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To unify with SDHI1 also use named IRQs for SDHI0. This also clarifies
which specific IRQs are used.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Both SDHI and MMCIF drivers can use the standard slot-gpio card-detection
functions. Switch mackerel to using them instead of platform callbacks.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Both SDHI and MMCIF drivers ignore their OCR platform values, when
available voltages can be retrieved from regulators.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The SDHI driver doesn't care about platform resource order, explicit
resource numbering is redundant.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Lager base board support making use of 2 GiB of memory,
the r8a7790 SoC with the SCIF0 serial port and CA15 with
ARM architected timer.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add LAN9220 support to the APE6EVM board using C and DT.
At this point the PFC driver lacks DT bindings so to
configure the PFC we use PINCTRL in C board code.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Start using the r8a73a4 PFC on the APE6EVM board
and configure the SCIFA0 console signals in the
PFC via PINCTRL.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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V3 of APE6EVM base board support making use of
1 GiB of memory, the SCIFA0 serial port and
ARM architected timer.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add a DT node for the SMSC 9221 ethernet chip, found on kzm9g, to its
reference implementation.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add basic Bock-W board support
More devices will be added on top of this patch after
PICNTRL and clock framework are in better shape.
Signed-off-by: Kuninori Morimoto <[email protected]>
Acked-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Second round of Renesas ARM and SH based SoC pinmux updates for v3.10
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
This merge is made to supply run-time dependencies for the following
patches that will bea added on top:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
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Remove unused pull-up/down data from the r8a73a4 PFC code.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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All r8a73a4 platforms use the pinctrl API to control pin functions.
Function GPIOs are no longer needed.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Remove IRQ pin function GPIOs that have been deprecated by the pinctrl
API.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Remove SCIF function GPIOs that have been deprecated by the pinctrl API.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The r8a73a4 board support will use the pinctrl API to control the
external IRQ pins so remove the unused function GPIOS.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and
SCIFB0->SCIFB3.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add initial PFC support for the r8a73a4 SoC.
At this point only GPIO interface is supported, move to newer interfaces
planned as incremental changes.
Original authors are Morimoto-san with help from Yoshii-san, thanks to
them for the heavy lifting. Adjusted by Magnus to work together with
updated code in drivers/pinctrl.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Takashi Yoshii <[email protected]>
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Move GPIOs handling from the PFC device to separate GPIO devices.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.
This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.
If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The board has 3 LEDs connected to GPIOs. Add a led-gpio device to
support them.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).
Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.
In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.
At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.
Signed-off-by: Magnus Damm <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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struct resource is defined in linux/ioport.h. Include it.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Conflicts:
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
This merge is to provide r8a73a4 SoC files, which are added in the
soc branch and depended on by r8a73a4 pfc-changes which are to
be added to the pinmux branch.
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The r8a7790 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: Takashi Yoshii <[email protected]>
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The r8a73a4 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: Takashi Yoshii <[email protected]>
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add a platform device for the r8a7790 PFC.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add IRQC interrupt controller support to r8a7790 by
hooking up a single IRQC instances to handle 4 external
IRQ signals. The IRQC controller is tied to SPIs of
the GIC. On r8a7790 the external IRQ pins routing is
handled by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add SCIF serial port support to the r8a7790 SoC by
adding platform devices for SCIFA0 -> SCIFA2 as well
as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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