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2014-01-23drm/nouveau/pwr: implement a simple i2c stackBen Skeggs11-279/+2066
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/pwr: have rd/wr32 routines clobber data instead of addrBen Skeggs5-65/+67
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb: turn off some bits in 10f584 at initBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: merge a fix from ddr3 for one of the timing settingsBen Skeggs1-2/+5
Titan. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: yet another random 10f200 bitBen Skeggs3-0/+10
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvc0-/fb: hook up skeleton interrupt handlerBen Skeggs2-0/+18
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: more 10f200 stuffBen Skeggs1-3/+5
Seen on Titan. NFI what the condition to switch this on is yet, and, hardcoding it to on currently causes master to report unknown intr with a mask of 0x08002000. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/clk: report ddr memory frequencyBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/fb/gddr5: make sure we update mr7 when we're supposed toBen Skeggs1-4/+13
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: 10f698/69cBen Skeggs1-1/+5
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb: it's now safe to obey the memory voltage setting properlyBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb: multi-stage reclock is required for certain transitionsBen Skeggs2-16/+70
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/clk: allow fb to signal it needs to do a multi-stage reclockBen Skeggs1-3/+6
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: parse bios data into struct rather than using directlyBen Skeggs10-218/+412
Still essentially a struct of magic values with magic names and unknown purposes. But, we will shortly need to be able to mix and match bits of the previous and next configurations to do a transition reclock, as such, we can no longer directly use the vbios data with any ease. This is probably nicer anyway in the long run, for a few reasons. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: found LP3 settingBen Skeggs2-7/+8
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb: note the memory voltage toggle, not using it yetBen Skeggs2-4/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: somewhat better attempt at 100770/10f604/610/614Ben Skeggs1-14/+47
Signed-off-by: Ben Skeggs <[email protected]> fb/gddr5/nve0: 100770 is like 10f604 Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: fixup delays a bitBen Skeggs1-2/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/bios: timing 2.0 entries can have subentriesBen Skeggs6-23/+34
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: note another semi-unknownBen Skeggs1-14/+17
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/fb/gddr5: modify mr8 with high bits of CL/WRBen Skeggs1-0/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: fix calculation of RDQS settingBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: switch off some other random bit at some pointBen Skeggs1-1/+1
As seen when comparing us vs nv on my GTX660 Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: punt all 10f910/914 accesses through ram_trainBen Skeggs1-12/+9
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: not all memory partitions are created equalBen Skeggs4-15/+76
As seen when comparing us vs nv on my GTX660. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb: typo in register nameBen Skeggs1-4/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/bios: make common code to handle ramcfg strap etcBen Skeggs8-91/+86
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: fix an assumption of sane memory controller layoutBen Skeggs1-7/+10
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fb/gddr5: fix behaviour of lp3 settingBen Skeggs2-2/+5
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs2-12/+22
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs1-1/+16
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs1-11/+87
Ordering from Android GK20A driver, names from binary driver strings. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: document more intr status bitsBen Skeggs1-5/+72
As per Android GK20A driver. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs1-2/+30
As per Android GK20A driver. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs1-15/+15
As per Android GK20A driver. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nve0/fifo: s/playlist/runlist/Ben Skeggs1-14/+20
As per Android GK20A driver. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvf0/gr: enable acceleration with our chsw ucodeBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nv108/gr: enable acceleration with our chsw ucodeBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvc0-/gr: handle fwmthd interrupts in ucodeBen Skeggs7-294/+308
Compute code in mesa triggers one of these, hanging the engine. Let's at least ack the request for now to avoid the hang. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvc0-/gr: fiddle some magic around strand initBen Skeggs7-1110/+1191
Fixes HUB_INIT timeout on GK110/GK208 when not using NVIDIA's ucode. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nv108/gr: initial support (need external fuc)Ben Skeggs13-10/+3074
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nv108/ce: enable copy enginesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nv108/fifo: initial supportBen Skeggs6-55/+115
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvf0/gr: remove a copy+pasto in ctx reglistBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nvc0-/gr: bring in some macros to abstract falcon isa differencesBen Skeggs12-3943/+4431
Need. A. Compiler... Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/falcon: use vmalloc to create firwmare copiesIlia Mirkin1-5/+15
Some firmware images may be large (64K), so using kmalloc memory is inappropriate for them. Use vmalloc instead, to avoid high-order allocation failures. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
2014-01-23drm/nouveau/gem: remove (now) unneeded pre-validate fence syncBen Skeggs1-6/+0
Now that nouveau_bo.c can handle sync when it actually needs to, we can remove this and avoid a double semaphore acquire when syncing in the command submission path. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/ttm: explicitly wait for bo idle before memcpy buffer moveBen Skeggs1-19/+18
Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/ttm: explicity sync with kernel channel before moving bufferBen Skeggs1-28/+13
The GEM code handles this currently, but that'll be removed. Signed-off-by: Ben Skeggs <[email protected]>
2014-01-23drm/nouveau/ttm: tidy up creation of temporary buffer move vmasBen Skeggs1-20/+21
Signed-off-by: Ben Skeggs <[email protected]>
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