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2023-01-17drm/amdgpu: correct query xgmi3x16 pcs error statusStanley.Yang2-3/+156
There is xgmi3x16 pcs error status for aldebaran, driver should check xgmi3x16 pcs error status field instead of gopx16 pcs error status field. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: support check xgmi/walf error mask bit for aldebaranStanley.Yang1-38/+64
The pcs error count should be determined by PCS ERROR status and PCS ERROR MASK registers, only PCS ERROR status register can not refect error counts accurately. Changed from V1: remove clean noncorrectable mask registers optimize query pcs error status Changed from V2: remove check mask_value bits correct set value corresponding bit Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: fix amdgpu_job_free_resources v2Christian König1-2/+8
It can be that neither fence were initialized when we run out of UVD streams for example. v2: fix typo breaking compile Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2324 Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Optimize gfx ras block initialization code for gfx v9_0YiPeng Chai1-21/+5
Use gfx ras common initialization interface to initialize gfx ras block. V2: Update function call due to amdgpu_gfx_ras_sw_init interface changes. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Fix coding styleThomas Zimmermann1-2/+2
Align a closing brace and remove trailing whitespaces. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrixJoshua Ashton1-2/+2
The YCC conversion matrix for RGB -> COLOR_SPACE_YCBCR2020_TYPE is missing the values for the fourth column of the matrix. The fourth column of the matrix is essentially just a value that is added given that the color is 3 components in size. These values are needed to bias the chroma from the [-1, 1] -> [0, 1] range. This fixes color being very green when using Gamescope HDR on HDMI output which prefers YCC 4:4:4. Fixes: 40df2f809e8f ("drm/amd/display: color space ycbcr709 support") Reviewed-by: Melissa Wen <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Calculate output_color_space after pixel encoding adjustmentJoshua Ashton1-2/+2
Code in get_output_color_space depends on knowing the pixel encoding to determine whether to pick between eg. COLOR_SPACE_SRGB or COLOR_SPACE_YCBCR709 for transparent RGB -> YCbCr 4:4:4 in the driver. v2: Fixed patch being accidentally based on a personal feature branch, oops! Fixes: ea117312ea9f ("drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded") Reviewed-by: Melissa Wen <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: use swap() helper macro in bios_parserDeepak R Varma1-9/+2
Use swap() helper macro instead of open coded swap instructions. The change also facilitates code cleanup and realignment for improved readability. Issue identified using swap.cocci Coccinelle semantic patch script. Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/pm/powerplay/smumgr/ci: use bitwise or for bitmasks additionDeepak R Varma1-1/+1
For bit mask addition, it is recommended to use or operator "|" instead of numerical addition as the former is quicker and cleaner. Change suggested by orplus.cocci Coccinelle semantic patch. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/pm/powerplay/hwmgr: use bitwise or for bitmasks additionDeepak R Varma1-4/+4
For bit mask addition, it is recommended to use or operator "|" instead of numerical addition as the former is quicker and cleaner. Change suggested by orplus.cocci Coccinelle semantic patch. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/pm/powerplay/smumgr: use bitwise or for additionDeepak R Varma2-2/+2
For bit mask addition, it is recommended to use or operator "|" instead of numerical addition as the former is quicker and cleaner. Change suggested by orplus.cocci Coccinelle semantic patch. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu/pm: update hwmon power documentationAlex Deucher1-1/+1
Power reporting is socket power. On APUs this includes the CPU. Update the documentation to clarify this. Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdkfd: Support process XNACK mode dynamic changePhilip Yang3-16/+15
Update queue qpd is done for the first queue creation of the process, if the device support XNACK mode per process, update qpd setup sh_mem_config based on the process XNACK mode, to support the process destroy all queues, change XNACK mode, and then create queues. Add helper macro KFD_SUPPORT_XNACK_PER_PROCESS to remove duplicate code and add new ASICs support in future. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd: Evaluate early init for all IP blocks even if one failsMario Limonciello1-1/+5
If early init fails for a single IP block, then no further IP blocks are evaluated. This means that if a user was missing more than one firmware binary they would have to keep adding binaries and re-probing until they discovered the ones missing. To make this easier, run early init for each IP block and report a single failure if not all passed. Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd: Remove needless break for legacy IP discovery MP0 9.0.0Mario Limonciello1-1/+0
There is already a "default" case in the switch block, so there is no need to have a break after the switch block. Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: fix cleaning up reserved VMID on releaseChristian König1-0/+1
We need to reset this or otherwise run into list corruption later on. Fixes: e44a0fe630c5 ("drm/amdgpu: rework reserved VMID handling") Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Adjust ras support check condition for special asicYiPeng Chai1-1/+16
[Why]: Amdgpu ras uses amdgpu_ras_is_supported to check whether the ras block supports the ras function. amdgpu_ras_is_supported uses .ras_enabled to determine whether the ras function of the block is enabled. But for special asic with mem ecc enabled but sram ecc not enabled, some ras blocks support poison mode but their ras function is not enabled on .ras_enabled, these ras blocks will run abnormally. [How]: If the ras block is not supported on .ras_enabled but the asic supports poison mode and the ras block has ras configuration, it can be considered that the ras block supports ras function. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Remove unnecessary ras block support checkYiPeng Chai1-3/+0
[Why]: For special asic with mem ecc enabled but sram ecc not enabled, some ras blocks can register their ras configuration to ras list, but these ras blocks are not enabled on .ras_enabled, so it can not get ras block object using amdgpu_ras_get_ras_block. [How]: Remove ras block support check. Even if the ras block checked is not in the ras list, it will return a null pointer and will have no effect. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Perform gpu reset after gfx finishes processing ras poison ↵YiPeng Chai4-3/+31
consumption on gfx_v11_0_3 Perform gpu reset after gfx finishes processing ras poison consumption on gfx_v11_0_3. V2: Move gfx poison consumption handler from hw_ops to ip function level. V3: Adjust the calling position of amdgpu_gfx_poison_consumation_handler. V4: Since gfx v11_0_3 does not have .hw_ops instance, the .hw_ops null pointer check in amdgpu_ras_interrupt_poison_consumption_handler needs to be adjusted. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Add gfx cp ecc error irq handling on gfx v11_0_3YiPeng Chai1-0/+47
V2: Optimize gfx_v11_0_set_cp_ecc_error_state function. V3: Define macro constant for me pipe instance address interval. V5: Register and handle gfx cp ecc error irq on gfx v11_0_3. V6: Remove invalid intermediate function call. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Add gfx ras poison consumption irq handling on gfx v11_0_3YiPeng Chai4-1/+79
Add gfx ras poison consumption irq handling on gfx v11_0_3. V2: Move ras poison consumption irq handling code of gfx v11_0_3 to gfx_v11_0_3.c. V5: Create dedicated irq handler for RLC_GC_FED_INTERRUPT. V6: Remove invalid function call. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headersYiPeng Chai2-0/+58
V2: Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register offset and shift masks. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Add gfx ras function on gfx v11_0_3YiPeng Chai6-0/+106
Add gfx ras function on gfx v11_0_3. V2: 1. Add separate source files for gfx v11_0_3. 2. Create a common function to initialize gfx ras block. V3: 1. Rename amdgpu_gfx_ras_block_init to amdgpu_gfx_ras_sw_init. 2. Adjust the calling position of amdgpu_gfx_ras_sw_init. 3. Remove gfx_v11_0_3_ras_ops. V4: Revert changes in amdgpu_ras_interrupt_poison_consumption_handler. V5: 1. Remove invalid include file in gfx_v11_0_3.c. 2. Reduce the number of parameters of amdgpu_gfx_ras_sw_init. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd: Fix renoir/green sardine MP0 IP version detectionMario Limonciello1-6/+3
The existing codebase never had a case for detecting MP0 version on Renoir and instead relied upon hardcoded chip name. This was missed as part of the changes to migrate all IP blocks to build filenames from `amdgpu_ucode.c`. Consequently, Renoir tries to fetch a binary with 11_0_3 in the filename and since it's supposed to have "renoir" in the filename fails to probe. The fbdev still works though so the series worked. Add a case for Renoir into the legacy table to ensure the right ASD and TA firmware load again. Reported-by: Ekene Akuneme <[email protected]> Reported-by: Nicholas Choi <[email protected]> Cc: Alex Hung <[email protected]> Fixes: 994a97447e38 ("drm/amd: Parse both v1 and v2 TA microcode headers using same function") Fixes: 54a3e032340e ("drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode"") Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: 3.2.218Aric Cyr1-1/+1
This version brings along following fixes: - Revert patches that caused regressions associated with audio and an old change that checks the DCN version. - Refactor DDC and HDP. - Move DPIA and DPCD logic to new files. - Updates to DMUB. - Optimization and bug fixes for SUBVP/DRR. - Drop legacy code. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: hdcp not enabled on connector 0hersen wu1-7/+0
[Why] incorrect skip when drm_connector.index = 0 within event_property_validate and update [How] handle hdcp validate and update for connector 0 Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: phase2 enable mst hdcp multiple displayshersen wu2-43/+122
[why] For MST topology with 1 physical link and multiple connectors (>=2), e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace set to enable the HDCP simultaneously on all connected outputs, the commit tail iteratively call the hdcp_update_display() for each display (connector). However, the hdcp workqueue data structure for each link has only one DM connector and encryption status members, which means the work queue of property_validate/update() would only be triggered for the last connector within this physical link, and therefore the HDCP property value of other connectors would stay on DESIRED instead of switching to ENABLED, which is NOT as expected. [how] Use array of AMDGPU_DM_MAX_DISPLAY_INDEX for both aconnector and encryption status in hdcp workqueue data structure for each physical link. For property validate/update work queue, we iterates over the array and do similar operation/check for each connected display. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Account for MPO planes in dcn32 mall alloc calculationsDillon Varone1-2/+3
[WHY?] Cannot only consider the MALL required from top pipes because of the MPO case. [HOW?] Only count a pipe if it fits the following criteria: 1) does not have a top pipe (is the topmost pipe for that plane) 2) it does have a top pipe, but that pipe is associated with a different plane Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Allow subvp on vactive pipes that are 2560x1440@60Alvin Lee2-1/+32
Enable subvp on specifically 1440p@60hz displays even though it can switch in vactive. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Request min clocks after disabling pipes on initAlvin Lee1-0/+21
[Description] - Request min clocks after disabling pipes on init - This optimizes for power savings during init sequence - Also handles the case where we boot up with no display connected Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: fix mapping to non-allocated addressBrandon Syu4-6/+19
[Why] There is an issue mapping non-allocated location of memory. It would allocate gpio registers from an array out of bounds. [How] Patch correct numbers of bounds for using. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Brandon Syu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Skip backlight control delay on external powered linksTony Tascioglu6-14/+17
[Why] When an eDP panel is powered externally from a different GPU, we can avoid waiting for hardware sequencing delays when switching the backlight on/off as the display backlight is no longer powered by the original source. [How] This commit extends the 'link_powered_externally' variable to allow bypassing hardware delays for additional backlight commands and force the backlight on/off when a link is powered by another GPU. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Felipe Clark <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Tony Tascioglu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: contional remove disable dig_fifo when blankCharlene Liu2-1/+3
keep dig_fifo enable for test pattern generation. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Remove DISPCLK dentist programming for dcn32Dillon Varone1-5/+91
[WHY?] For dcn32, SMU handles DISPCLK dentist programming. [HOW?] Only use calls to SMU to set DISPCLK. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Add extra mblk for DCCSaaem Rizvi1-5/+5
[Why] DCC meta was found to be detached from usable pixel data. Due to this DCC meta and the end of the fetched part of the frame will be on not be on the same mblk. Furthermore if the meta is not aligned to the mblk size, then we require an extra mblk in MALL to account for this. [How] Always add an additional mblk when DCC is enabled for detachment and misalignment. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: set active bit for desktop with VSDBv3Dillon Varone1-6/+14
When using freesync on desktop, need to set freesync active bit for AMD VSDBv3 infopacket. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Remove unused codeRodrigo Siqueira1-44/+0
Remove some code that is never used from freesync file. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Optimize link power-down when link powered externallyTony Tascioglu7-15/+29
[Why] When an eDP panel is powered externally by a different GPU, we don't need to wait for hardware sequencing delays when powering down a link, as the display is not dependent on the GPU being powered down. [How] This commit adds a variable 'link_powered_externally' to indicate when a link is being powered by another GPU. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Felipe Clark <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Tony Tascioglu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: fix an error check condition for synced pipesAurabindo Pillai1-2/+13
Checking for disabled master pipe on a timing synchronized pipe is incorrect in the case of ODM combine. This case is acceptable as long as the disabled master pipe is part of the ODM tree. Skip printing error message if this condition holds true. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17Revert "drm/amd/display: Demote Error Level When ODM Transition Supported"Aurabindo Pillai1-12/+3
This reverts commit e81b6a4427f3ca37859f5b9fdb6a66683bb84e2e. Reverting to put in a better solution which does not involve checking DCN version. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: move dp capability related logic to link_dp_capabilityWenjing Liu26-2263/+2380
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: move dp phy related logic to link_dp_phyWenjing Liu14-149/+210
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: move dp link training logic to link_dp_trainingWenjing Liu22-4119/+4545
[why] Extract dp link training logic out to their own files. link_dp_training - high level training sequence and helper functions. link_dp_training_8b_10b - dp1.x training link_dp_training_auxless - aux-less training link_dp_traininig_dpia - dpia training link_dp_training_fixed_vs_pe_retimer - fixed vs pe retimer training link_dp_training_128b_132b - dp2.1 training Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Remove SubVp support if src/dst rect does not equal stream ↵Saaem Rizvi1-0/+8
timing Current implementation of SubVP does not support cases where stream timing matched neither the destination rect nor the source rect. Will need to further debug to see how we can support these cases. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Change i2c speed for hdcpBhawanpreet Lakha1-1/+1
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] slower down the HW i2c speed when used by HW i2c. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: cleanup function args in dmlDillon Varone2-2/+2
Remove array size on array passed to CalculateDETSwathFillLatencyHiding. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Use DML for MALL SS and Subvp allocation calculationsDillon Varone7-237/+134
MALL SS and Subvp use the same calculations for determining the size of the required allocation for a given surface, which is already done in DML. Add an interface to extract this information from VBA variables and use in their respective helper functions. Also refactor existing code to remove stale workarounds. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Account for Subvp Phantoms in DML MALL surface calculationsDillon Varone3-4/+14
DML does not explicitly consider support for space in MALL required for subvp phantom pipes. This adds a check to make sure portion of phantom surface can fit in MALL. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Account for DCC Meta pitch in DML MALL surface calculationsDillon Varone3-4/+12
DML incorrectly uses surface width for determining DCC meta size in MALL allocation calculations. Meta pitch should be used instead. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amd/display: Optimize subvp and drr validationDillon Varone1-16/+26
Two issues existed: 1) Configs that support DRR, but have it disabled will fail subvp+vblank validation incorrectly. Use subvp+vblank path for this case. 2) Configs that support DRR and have it enabled can use higher voltage level than required if they also support subvp+vblank. Use lowest supported voltage level for this case. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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