aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2015-08-20x86/mm/pat: Add comments to cachemode translation tablesToshi Kani1-2/+5
Add comments to the cachemode translation tables to clarify that the default values are set as minimal supported mode, which are necessary to handle WC and WT fallback to UC- when they are not enabled. Signed-off-by: Toshi Kani <[email protected]> Cc: Jan Beulich <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20Merge tag 'for-linus-4.2-rc7-tag' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip Pull xen build fix from David Vrabel: "Fix i386 build with an (uncommon) configuration" * tag 'for-linus-4.2-rc7-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: x86/xen: make CONFIG_XEN depend on CONFIG_X86_LOCAL_APIC
2015-08-20Merge branch 'fortglx/4.3/time' of ↵Thomas Gleixner7-33/+102
https://git.linaro.org/people/john.stultz/linux into timers/core - A handful or y2038 related items - A walltime to monotonic limit - Small fixes for timespec_trunc() and timer_list output
2015-08-20Merge tag 'sound-4.2' of ↵Linus Torvalds6-1/+27
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "Here are a small collecton of sound fix patches. The most significant one is the disablement of newly introduced topology API. Its ABI couldn't be stabilized enough, so we decided to delay for 4.3 in the end. Other than that, all oneliner fixes: a USB-audio runtime PM fix and a couple of HD-audio quirks" * tag 'sound-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: ALSA: hda - Add dock support for Thinkpad W541 (17aa:2211) ALSA: usb-audio: Fix runtime PM unbalance ASoC: topology: Disable use from userspace ASoC: topology: Add Kconfig option for topology ALSA: hda - Fix the white noise on Dell laptop
2015-08-20Input: gpio_keys_polled - request GPIO pin as input.Vincent Pelletier1-1/+1
GPIOF_IN flag was lost in: Commit 633a21d80b4a("input: gpio_keys_polled: Add support for GPIO descriptors"). Without this flag, legacy code path (for non-descriptor GPIO declarations) would configure GPIO as output (0 meaning GPIOF_DIR_OUT | GPIOF_INIT_LOW). Cc: [email protected] Signed-off-by: Vincent Pelletier <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> Signed-off-by: Dmitry Torokhov <[email protected]>
2015-08-20Merge git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pendingLinus Torvalds4-23/+44
Pull SCSI target fixes from Nicholas Bellinger: "This contains a v4.2-rc specific RCU module unload regression bug-fix, a long-standing iscsi-target bug-fix for duplicate target_xfer_tags during NOP processing from Alexei, and two more small REPORT_LUNs emulation related patches to make Solaris FC host LUN scanning happy from Roland. There is also one patch not included that allows target-core to limit the number of fabric driver SGLs per I/O request using residuals, that is currently required as a work-around for FC hosts which don't honor EVPD block-limits settings. At this point, it will most likely become for-next material" * git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending: target: Fix handling of small allocation lengths in REPORT LUNS target: REPORT LUNS should return LUN 0 even for dynamic ACLs target/iscsi: Fix double free of a TUR followed by a solicited NOPOUT target: Perform RCU callback barrier before backend/fabric unload
2015-08-20Merge branch 'fixes' of ↵Linus Torvalds2-33/+48
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal Pull thermal fixes from Eduardo Valentin: "Last minute fixes on the thermal-soc tree. There is a fix of a long lasting bug in cpu cooling device, thanks for RMK for being pushing this" * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: thermal/cpu_cooling: update policy limits if clipped_freq < policy->max thermal/cpu_cooling: rename max_freq as clipped_freq in notifier thermal/cpu_cooling: rename cpufreq_val as clipped_freq thermal/cpu_cooling: convert 'switch' block to 'if' block in notifier thermal/cpu_cooling: quit early after updating policy thermal/cpu_cooling: No need to initialize max_freq to 0 thermal: cpu_cooling: fix lockdep problems in cpu_cooling thermal: power_allocator: do not use devm* interfaces
2015-08-20spi: mediatek: use BIT() to instead of SPI_CMD_*_OFFSETLeilk Liu1-17/+20
This patch removes SPI_CMD_*_OFFSET defines, and uses the BIT(x) defines instead. Signed-off-by: Leilk Liu <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2015-08-20spi: medaitek: revise quirks compatibility styleLeilk Liu1-18/+7
The quirks are true/false, so define these as bool. Signed-off-by: Leilk Liu <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2015-08-20spi: mediatek: fix spi incorrect endian usageLeilk Liu2-24/+16
TX_ENDIAN/RX_ENDIAN bits define whether to reverse the endian order of the data DMA from/to memory. The endian order should keep the same with cpu endian. Signed-off-by: Leilk Liu <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2015-08-20spi: ti-qspi: use 128 bit transfer mode where possibleVignesh R1-4/+30
TI QSPI has four 32 bit data regsiters which can be used to transfer 16 bytes of data at once. The register group QSPI_SPI_DATA_REG_3, QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is treated as a single 128-bit word for shifting data in and out. The bit at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out in case of 128 bit transfer mode. Therefore the first byte to be written to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. Instead of writing 1 byte at a time when interacting with spi-nor flash, make use of all the four registers so that 16 bytes can be transferred in one go. This reduces number of register writes and Word Complete interrupts for a given transfer message size, thereby increasing the write performance. Without this patch the raw flash write speed is ~100KB/s, with this patch the write speed increases to ~400 kB/s on DRA74 EVM. Signed-off-by: Vignesh R <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2015-08-20PCI: Drop references acquired by of_parse_phandle()Bjorn Helgaas2-0/+2
of_parse_phandle() returns a device_node pointer with the refcount incremented. We should dispose of this reference when we're finished. Drop the reference acquired by of_parse_phandle(). Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Lorenzo Pieralisi <[email protected]>
2015-08-20PCI/MSI: Remove unused pcibios_msi_controller() hookLorenzo Pieralisi1-16/+1
The pcibios_msi_controller() hook was only implemented by ARM, and it sets pci_bus->msi now, so it doesn't need this hook anymore. Remove the unused pcibios_msi_controller() hook. [bhelgaas: changelog, split into separate patch] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-20ARM/PCI: Remove msi_controller from struct pci_sys_dataLorenzo Pieralisi2-15/+0
ARM now uses pci_bus->msi to store the msi_controller pointer, so we don't need to save it in struct pci_sys_data, and we don't need to implement pcibios_msi_controller() to get it out of pci_sys_data. Remove msi_controller from struct pci_sys_data and pcibios_msi_controller(). [bhelgaas: changelog, split into separate patch] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Jingoo Han <[email protected]>
2015-08-20ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi()Lorenzo Pieralisi4-10/+20
ARM previously stored the msi_controller pointer in its sysdata, struct pci_sys_data, and implemented pcibios_msi_controller() to retrieve it. That made PCI host controller drivers specific to ARM because they had to put the msi_controller pointer in the ARM-specific pci_sys_data. There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the msi_controller pointer to the PCI core. Use this for all ARM systems and for the DesignWare and Xilinx PCI host controller drivers. This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6, Keystone, Layerscape, SPEAr13xx, and Xilinx drivers. [bhelgaas: changelog, split into separate patch] Suggested-by: Russell King <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jingoo Han <[email protected]> CC: Pratyush Anand <[email protected]> CC: Arnd Bergmann <[email protected]> CC: Simon Horman <[email protected]> CC: Russell King <[email protected]> CC: Thomas Petazzoni <[email protected]> CC: Thierry Reding <[email protected]> CC: Michal Simek <[email protected]> CC: Marc Zyngier <[email protected]>
2015-08-20PCI: Add pci_scan_root_bus_msi()Lorenzo Pieralisi2-2/+16
Add a pci_scan_root_bus_msi() interface so an arch can specify the MSI controller up front. This removes the need for a pcibios callback to set the MSI controller later. This is not exported because I'd like to replace the variety of "scan root bus" interfaces with a single, more extensible interface that can handle the MSI controller, domain, pci_ops, resources, etc. I hope this interface is temporary. [bhelgaas: changelog, split into separate patch] Suggested-by: Russell King <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Jingoo Han <[email protected]>
2015-08-20ARM/PCI: Replace panic with WARN messages on failuresLorenzo Pieralisi1-4/+6
In the ARM PCI bios32 layer, failures to dynamically allocate pci_sys_data for a PCI bus, or a PCI bus scan failure have to be considered serious warnings but they should not trigger a system panic so that at least the system is given a chance to be debugged. This patch replaces the panic statements with WARN() messages to improve error reporting in the ARM PCI bios32 layer. Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Jingoo Han <[email protected]> Acked-by: Marc Zyngier <[email protected]> CC: Russell King <[email protected]> CC: Marc Zyngier <[email protected]>
2015-08-20PCI: generic: Add arm64 supportJayachandran C1-1/+1
Make pci-host-generic driver (kernel option PCI_HOST_GENERIC) available on arm64. Signed-off-by: Jayachandran C <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-20PCI: Build setup-irq.o for arm64Jayachandran C1-0/+1
ARM64 requires setup-irq.o to provide pci_fixup_irqs() implementation. We are adding this now to support the pci-host-generic host controller, but we enable it for ARM64 PCI so that other host controllers can use this as well. Signed-off-by: Jayachandran C <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-20PCI: generic: Remove dependency on ARM-specific struct hw_pciJayachandran C1-19/+33
The generic OF-based host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Note that the ARM pcibios functions expect the PCI sysdata to be a pointer to a struct pci_sys_data. Add a struct pci_sys_data as the first element in struct gen_pci so that when we use a gen_pci pointer as sysdata, it is also a pointer to a struct pci_sys_data. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: changelog, move pcie_bus_configure_settings() before pci_bus_add_devices(), combine !PCI_PROBE_ONLY blocks] Tested-by: Lorenzo Pieralisi <[email protected]> Tested-by: Suravee Suthikulpanit <[email protected]> Tested-by: Pavel Fedin <[email protected]> Signed-off-by: Jayachandran C <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
2015-08-20xtensa: improve vmlinux.lds.S sed post-processingMax Filippov1-4/+5
Current sed script makes assumptions about the structure of rules that group .text sections in the vmlinux linker script. These assumptions get broken occasionally, e.g.: 779c88c94c34 "ARM: 8321/1: asm-generic: introduce.text.fixup input section", or 9bebe9e5b0f3 "kbuild: Fix .text.unlikely placement". Rewrite sed rules so that they don't depend on number/arrangement of text sections in *(...) blocks. Signed-off-by: Max Filippov <[email protected]>
2015-08-20clocksource/imx: Fix boot with non-DT systemsGuenter Roeck1-0/+1
Commit 6dd747825b20 ("ARM: imx: move timer resources into a structure") moved initialization parameters into a data structure, but neglected to set the irq field in that data structure for non-DT boots. This causes the system to hang if a non-DT boot is attempted. Fixes: 6dd747825b20 ("ARM: imx: move timer resources into a structure") Signed-off-by: Guenter Roeck <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Daniel Lezcano <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20ARC: add/fix some comments in code - no functional changeVineet Gupta6-22/+23
Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: change some branchs to jumps to resolve linkage errorsYuriy Kolerov3-9/+9
When kernel's binary becomes large enough (32M and more) errors may occur during the final linkage stage. It happens because the build system uses short relocations for ARC by default. This problem may be easily resolved by passing -mlong-calls option to GCC to use long absolute jumps (j) instead of short relative branchs (b). But there are fragments of pure assembler code exist which use branchs in inappropriate places and cause a linkage error because of relocations overflow. First of these fragments is .fixup insertion in futex.h and unaligned.c. It inserts a code in the separate section (.fixup) with branch instruction. It leads to the linkage error when kernel becomes large. Second of these fragments is calling scheduler's functions (common kernel code) from entry.S of ARC's code. When kernel's binary becomes large it may lead to the linkage error because scheduler may occur far enough from ARC's code in the final binary. Signed-off-by: Yuriy Kolerov <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: ensure futex ops are atomic in !LLSC configVineet Gupta1-0/+12
W/o hardware assisted atomic r-m-w the best we can do is to disable preemption. Cc: David Hildenbrand <[email protected]> Cc: Peter Zijlstra (Intel) <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Michel Lespinasse <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: Enable HAVE_FUTEX_CMPXCHGVineet Gupta1-0/+1
ARC doesn't need the runtime detection of futex cmpxchg op Cc: Peter Zijlstra (Intel) <[email protected]> Cc: Thomas Gleixner <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: make futex_atomic_cmpxchg_inatomic() return bimodalVineet Gupta1-9/+11
Callers of cmpxchg_futex_value_locked() in futex code expect bimodal return value: !0 (essentially -EFAULT as failure) 0 (success) Before this patch, the success return value was old value of futex, which could very well be non zero, causing caller to possibly take the failure path erroneously. Fix that by returning 0 for success (This fix was done back in 2011 for all upstream arches, which ARC obviously missed) Cc: Peter Zijlstra (Intel) <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Michel Lespinasse <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: futex cosmeticsVineet Gupta1-8/+9
Cc: Peter Zijlstra (Intel) <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Michel Lespinasse <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARC: add barriers to futex codeVineet Gupta1-11/+10
The atomic ops on futex need to provide the full barrier just like regular atomics in kernel. Also remove pagefault_enable/disable in futex_atomic_cmpxchg_inatomic() as core code already does that Cc: David Hildenbrand <[email protected]> Cc: Peter Zijlstra (Intel) <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Michel Lespinasse <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARCv2: IOC: Allow boot time disableAlexey Brodkin1-3/+4
Signed-off-by: Alexey Brodkin <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARCv2: SLC: Allow boot time disableVineet Gupta1-2/+19
Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin4-16/+125
In case of ARCv2 CPU there're could be following configurations that affect cache handling for data exchanged with peripherals via DMA: [1] Only L1 cache exists [2] Both L1 and L2 exist, but no IO coherency unit [3] L1, L2 caches and IO coherency unit exist Current implementation takes care of [1] and [2]. Moreover support of [2] is implemented with run-time check for SLC existence which is not super optimal. This patch introduces support of [3] and rework of DMA ops usage. Instead of doing run-time check every time a particular DMA op is executed we'll have 3 different implementations of DMA ops and select appropriate one during init. As for IOC support for it we need: [a] Implement empty DMA ops because IOC takes care of cache coherency with DMAed data [b] Route dma_alloc_coherent() via dma_alloc_noncoherent() This is required to make IOC work in first place and also serves as optimization as LD/ST to coherent buffers can be srviced from caches w/o going all the way to memory Signed-off-by: Alexey Brodkin <[email protected]> [vgupta: -Added some comments about IOC gains -Marked dma ops as static, -Massaged changelog a bit] Signed-off-by: Vineet Gupta <[email protected]>
2015-08-20x86/xen: make CONFIG_XEN depend on CONFIG_X86_LOCAL_APICDavid Vrabel1-2/+2
Since commit feb44f1f7a4ac299d1ab1c3606860e70b9b89d69 (x86/xen: Provide a "Xen PV" APIC driver to support >255 VCPUs) Xen guests need a full APIC driver and thus should depend on X86_LOCAL_APIC. This fixes an i386 build failure with !SMP && !CONFIG_X86_UP_APIC by disabling Xen support in this configuration. Users needing Xen support in a non-SMP i386 kernel will need to enable CONFIG_X86_UP_APIC. Signed-off-by: David Vrabel <[email protected]> Cc: <[email protected]>
2015-08-20Merge tag 'perf-core-for-mingo' of ↵Ingo Molnar38-21/+8858
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo: - Support Intel PT in several tools, enabling the use of the processor trace feature introduced in Intel Broadwell processors: (Adrian Hunter) # dmesg | grep Performance # [0.188477] Performance Events: PEBS fmt2+, 16-deep LBR, Broadwell events, full-width counters, Intel PMU driver. # perf record -e intel_pt//u -a sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.216 MB perf.data ] # perf script # then navigate in the tool output to some area, like this one: 184 1030 dl_main (/usr/lib64/ld-2.17.so) => 7f21ba661440 dl_main (/usr/lib64/ld-2.17.so) 185 1457 dl_main (/usr/lib64/ld-2.17.so) => 7f21ba669f10 _dl_new_object (/usr/lib64/ld-2.17.so) 186 9f37 _dl_new_object (/usr/lib64/ld-2.17.so) => 7f21ba677b90 strlen (/usr/lib64/ld-2.17.so) 187 7ba3 strlen (/usr/lib64/ld-2.17.so) => 7f21ba677c75 strlen (/usr/lib64/ld-2.17.so) 188 7c78 strlen (/usr/lib64/ld-2.17.so) => 7f21ba669f3c _dl_new_object (/usr/lib64/ld-2.17.so) 189 9f8a _dl_new_object (/usr/lib64/ld-2.17.so) => 7f21ba65fab0 calloc@plt (/usr/lib64/ld-2.17.so) 190 fab0 calloc@plt (/usr/lib64/ld-2.17.so) => 7f21ba675e70 calloc (/usr/lib64/ld-2.17.so) 191 5e87 calloc (/usr/lib64/ld-2.17.so) => 7f21ba65fa90 malloc@plt (/usr/lib64/ld-2.17.so) 192 fa90 malloc@plt (/usr/lib64/ld-2.17.so) => 7f21ba675e60 malloc (/usr/lib64/ld-2.17.so) 193 5e68 malloc (/usr/lib64/ld-2.17.so) => 7f21ba65fa80 __libc_memalign@plt (/usr/lib64/ld-2.17.so) 194 fa80 __libc_memalign@plt (/usr/lib64/ld-2.17.so) => 7f21ba675d50 __libc_memalign (/usr/lib64/ld-2.17.so) 195 5d63 __libc_memalign (/usr/lib64/ld-2.17.so) => 7f21ba675e20 __libc_memalign (/usr/lib64/ld-2.17.so) 196 5e40 __libc_memalign (/usr/lib64/ld-2.17.so) => 7f21ba675d73 __libc_memalign (/usr/lib64/ld-2.17.so) 197 5d97 __libc_memalign (/usr/lib64/ld-2.17.so) => 7f21ba675e18 __libc_memalign (/usr/lib64/ld-2.17.so) 198 5e1e __libc_memalign (/usr/lib64/ld-2.17.so) => 7f21ba675df9 __libc_memalign (/usr/lib64/ld-2.17.so) 199 5e10 __libc_memalign (/usr/lib64/ld-2.17.so) => 7f21ba669f8f _dl_new_object (/usr/lib64/ld-2.17.so) 200 9fc2 _dl_new_object (/usr/lib64/ld-2.17.so) => 7f21ba678e70 memcpy (/usr/lib64/ld-2.17.so) 201 8e8c memcpy (/usr/lib64/ld-2.17.so) => 7f21ba678ea0 memcpy (/usr/lib64/ld-2.17.so) - Fix annotation of vdso (Adrian Hunter) - Fix DWARF callchains in 'perf script' (Jiri Olsa) - Fix adding probes in kernel syscalls and listing which variables can be collected at kernel syscall function lines (Masami Hiramatsu) Build Fixes: - Fix 32-bit compilation error in util/annotate.c (Adrian Hunter) - Support static linking with libdw on Fedora 22 (Andi Kleen) Infrastructure changes: - Add a helper function to probe whether cpu-wide tracing is possible (Adrian Hunter) - Move vfs_getname storage to per thread area in 'perf trace' (Arnaldo Carvalho de Melo) Signed-off-by: Arnaldo Carvalho de Melo <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2015-08-20Merge branch 'perf/urgent' into perf/core, to pick up fixes before adding ↵Ingo Molnar604-4090/+7404
more changes Signed-off-by: Ingo Molnar <[email protected]>
2015-08-20Merge tag 'perf-urgent-for-mingo' of ↵Ingo Molnar4-4/+37
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent Pull perf/urgent fixes from Arnaldo Carvalho de Melo: - Fix buildid processing done at the end of a 'perf record' session, a problem that happened in workloads involving lots of small short-lived processes. That code was not asking the perf_session layer to order the events. Make the code more robust to handle some of the problems with such out-of-order events and fix 'perf record' to ask for ordered events on systems where we have perf_event_attr.sample_id_all. (Adrian Hunter) - Show backtrace when handling a SIGSEGV in 'perf top --stdio' (Arnaldo Carvalho de Melo) Signed-off-by: Arnaldo Carvalho de Melo <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2015-08-20PCI: imx6: Simplify a trivial if-return sequenceFabio Estevam1-10/+2
Simplify a trivial if-return sequence by combining it with a preceding function call. The semantic patch that makes this change is available in scripts/coccinelle/misc/simple_return.cocci. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Lucas Stach <[email protected]>
2015-08-20PCI: spear: Use BUG_ON() instead of condition followed by BUG()Fabio Estevam1-2/+1
Use BUG_ON() instead of an if condition followed by BUG(). The semantic patch that makes this change is available in scripts/coccinelle/misc/bugon.cocci. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Pratyush Anand <[email protected]>
2015-08-20PCI: dra7xx: Remove unneeded use of IS_ERR_VALUE()Fabio Estevam1-1/+1
There is no need to use the IS_ERR_VALUE() macro for checking the return value from pm_runtime_* functions. Test for a negative pm_runtime_get_sync() return value instead of using IS_ERR_VALUE(). The semantic patch that makes this change is available in scripts/coccinelle/api/pm_runtime.cocci. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Kishon Vijay Abraham I <[email protected]>
2015-08-20drm/edid: add function to help find SADsRussell King1-0/+19
Add a function to find the start of the SADs in the ELD. This complements the helper to retrieve the SAD count. [airlied: this fixes a build problem with the alsa eld helper which required this]. Signed-off-by: Russell King <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2015-08-20Merge branch 'drm-atmel-hlcdc-fixes' of ↵Dave Airlie1-1/+1
https://github.com/bbrezillon/linux-at91 into drm-fixes single atmel hlcdc fix. * 'drm-atmel-hlcdc-fixes' of https://github.com/bbrezillon/linux-at91: drm/atmel-hlcdc: Compile suspend/resume for PM_SLEEP only
2015-08-20irqchip/crossbar: Restore set_wake functionalityGrygorii Strashko1-2/+2
The TI crossbar irqchip doesn't provides any facility to configure the wakeup sources, but the conversion to hierarchical irqdomains set the irq_set_wake callback to irq_chip_set_wake_parent. The parent chip (OMAP wakeupgen) has no irq_set_wake function either so the call will fail with -ENOSYS. As a result the irq_set_wake() call in the resume path will trigger an 'Unbalanced wake disable' warning. Before the conversion the GIC irqchip was the top level irqchip and correctly flagged with IRQCHIP_SKIP_SET_WAKE. Restore the correct behaviour by removing the irq_set_type callback from the crossbar irqchip and set the IRQCHIP_SKIP_SET_WAKE flag which lets the irq_set_irq_wake() call from the driver succeed. [ tglx: Massaged changelog ] Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar...') Signed-off-by: Grygorii Strashko <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20irqchip/crossbar: Restore the mask on suspend behaviourGrygorii Strashko1-0/+1
The ARM GIC requires that all interrupts which are not used as a wakeup source have to be masked during suspend. The conversion of the crossbar irqchip to hierarchical irq domains failed to mark the crossbar irqchip with the IRQCHIP_MASK_ON_SUSPEND flag and therefor broke the suspend requirement of the GIC. Before the conversion the flags were visible because the GIC was the top level irqchip. After the conversion the crossbar irqchip is the top level irq chip whose flags are evaluated in suspend_device_irq(). As the flag is not set the masking of the non-wakeup irqs is not invoked which breaks suspend. Add the IRQCHIP_MASK_ON_SUSPEND flag to the crossbar irqchip, so the GIC interrupts get masked properly. [ tglx: Massaged changelog ] Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar...') Signed-off-by: Grygorii Strashko <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20ARM: OMAP: wakeupgen: Restore the irq_set_type() mechanismGrygorii Strashko1-0/+1
The conversion of the wakeupgen irqchip to hierarchical irq domains failed to provide a mechanism to properly set the trigger type of an interrupt. The wakeupgen irq chip itself has no mechanism and therefor no irq_set_type() callback. The code before the conversion relayed the trigger configuration directly to the underlying GIC. Restore the correct behaviour by setting the wakeupgen irq_set_type callback to irq_chip_set_type_parent(). This propagates the set_trigger() call to the underlying GIC irqchip. [ tglx: Massaged changelog ] Fixes: 7136d457f365 ('ARM: omap: convert wakeupgen to stacked domains') Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Tony Lindgren <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20irqchip/crossbar: Restore the irq_set_type() mechanismGrygorii Strashko1-0/+1
The conversion of the crossbar irqchip to hierarchical irq domains failed to provide a mechanism to properly set the trigger type of an interrupt. The crossbar irq chip itself has no mechanism and therefor no irq_set_type() callback. The code before the conversion relayed the trigger configuration directly to the underlying GIC. Restore the correct behaviour by setting the crossbar irq_set_type callback to irq_chip_set_type_parent(). This propagates the set_trigger() call to the underlying GIC irqchip. [ tglx: Massaged changelog ] Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar...') Signed-off-by: Grygorii Strashko <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20genirq: Introduce irq_chip_set_type_parent() helperGrygorii Strashko2-0/+18
This helper is required for irq chips which do not implement a irq_set_type callback and need to call down the irq domain hierarchy for the actual trigger type change. This helper is required to fix further wreckage caused by the conversion of TI OMAP to hierarchical irq domains and therefor tagged for stable. [ tglx: Massaged changelog ] Signed-off-by: Grygorii Strashko <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-20genirq: Don't return ENOSYS in irq_chip_retrigger_hierarchyGrygorii Strashko1-1/+1
irq_chip_retrigger_hierarchy() returns -ENOSYS if it was not able to find at least one .irq_retrigger() callback implemented in the IRQ domain hierarchy. That's wrong, because check_irq_resend() expects a 0 return value from the callback in case that the hardware assisted resend was not possible. If the return value is non zero the core code assumes hardware resend success and the software resend is not invoked. This results in lost interrupts on platforms where none of the parent irq chips in the hierarchy implements the retrigger callback. This is observable on TI OMAP, where the hierarchy is: ARM GIC <- OMAP wakeupgen <- TI Crossbar Return 0 instead so the software resend mechanism gets invoked. [ tglx: Massaged changelog ] Fixes: 85f08c17de26 ('genirq: Introduce helper functions...') Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Reviewed-by: Jiang Liu <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: [email protected] # 4.1 Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-08-19PCI: Tolerate hierarchies with no Root PortYijing Wang1-1/+6
We should not assume any particular hardware topology. Commit d0751b98dfa3 ("PCI: Add dev->has_secondary_link to track downstream PCIe links") relied on the assumption that every PCIe hierarchy is rooted at a Root Port. But we can't rely on any assumption about what hardware we will find; we just have to deal with the world as it is. On some platforms, PCIe devices (endpoints, switch upstream ports, etc.) appear directly on the root bus, and there is no Root Port in the PCI bus hierarchy. For example, Meelis observed these top-level devices on a Sparc V245: 0000:02:00.0 PCI bridge to [bus 03-0d] Switch Upstream Port 0001:02:00.0 PCI bridge to [bus 03] PCIe to PCI/PCI-X Bridge These devices *look* like they have links going upstream, but there really are no upstream devices. In set_pcie_port_type(), we used the parent device to figure out which side of a switch port has a link, so if the parent device did not exist, we dereferenced a NULL parent pointer. Check whether the parent device exists before dereferencing it. Meelis observed this oops on Sparc V245 and T2000. Ben Herrenschmidt says this is also possible on IBM PowerVM guests on PowerPC. [bhelgaas: changelog, comment] Link: http://lkml.kernel.org/r/[email protected] Reported-by: Meelis Roos <[email protected]> Tested-by: Meelis Roos <[email protected]> Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: David S. Miller <[email protected]>
2015-08-19perf top: Show backtrace when handling a SIGSEGV on --stdio modeArnaldo Carvalho de Melo1-2/+2
It was just freezing instead of informing about the SEGV, fix it and also print a backtrace, just like in the TUI mode and in 'perf trace'. Tested by provoking a NULL deref when pressing 'z': 0.31% libc-2.20.so [.] malloc_consolidate 0.31% ld-2.20.so [.] _dl_relocate_object 0.28% cc1 [.] ht_lookup 0.28% cc1 [.] ira_init_register_move_cost perf: Segmentation fault Obtained 7 stack frames. perf(dump_stack+0x32) [0x4d69f2] perf(sighandler_dump_stack+0x29) [0x4d6a89] /lib64/libc.so.6(+0x34960) [0x7f5064333960] perf() [0x438790] /lib64/libpthread.so.0(+0x752a) [0x7f50663dd52a] /lib64/libc.so.6(clone+0x6d) [0x7f50643ff22d] # Reported-by: Linus Torvalds <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: David Ahern <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Stephane Eranian <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2015-08-19spi: mediatek: remove redundant clock in prepare_hardware/unprepare_hardwareLeilk Liu1-17/+0
clock in prepare_hardware/unprepare_hardware is redundant with pm_runtime, so remove them. Signed-off-by: Leilk Liu <[email protected]> Signed-off-by: Mark Brown <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.