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Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Add support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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The thermal hardware description for the RZ/G1M SoC was added to its DTS
after the introduction of support for thermal zones, and included a
thermal-zones node from the beginning.
Hence there is no need to claim compatibility with
"renesas,rcar-thermal", which would be needed only for backwards
compatibility with kernels predating thermal zone support.
Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Lichee Pi Nano is a F1C100s board by Lichee Pi.
Add initial device tree for it.
Signed-off-by: Mesih Kilinc <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
Signed-off-by: Mesih Kilinc <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Add a node for the Camera Subsystem present on the Qualcomm
MSM8996 SoC.
Signed-off-by: Todor Tomov <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add VFE SMMU node.
Signed-off-by: Todor Tomov <[email protected]>
Reviewed-by: Vivek Gautam <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add pinctrls required for camera sensors:
- power down signal;
- reset signal;
- camera external clock.
Signed-off-by: Todor Tomov <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add pinctrls required for Camera Control Interface.
Signed-off-by: Todor Tomov <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add a node for the Camera Subsystem present on the Qualcomm
MSM8916 SoC.
Signed-off-by: Todor Tomov <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add IOMMU sub-node for VFE secure context bank.
Signed-off-by: Todor Tomov <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds a set of DTS files that support all PXA3xx based Raumfeld
audio hardware devices.
Common nodes are factored out into 'common' and 'tuneable-clock' include
files to keep the top-level DTS files smaller.
Signed-off-by: Daniel Mack <[email protected]>
[Robert: Reordered Makefile in alphabetical order]
Signed-off-by: Robert Jarzmik <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm Device Tree Changes for v4.21
* Add entry for Qualcomm TSENS thermal drivers
* Update msm8974 thermal entries
* Fix msm8974 Hammerhead magnetometer gpios
* Add SoC specific compatibles for SDHC nodes
* Remove Arrow SD600 eval board
* tag 'qcom-dts-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: qcom: Remove Arrow SD600 eval board
ARM: dts: qcom: Add SoC-specific string for sdhci-msm-v4 nodes
ARM: dts: qcom: msm8974-hammerhead: correct gpios property on magnetometer
ARM: dts: msm8974: thermal: Add "qcom,sensors" property
ARM: dts: msm8974: thermal: split address space into two
MAINTAINERS: Add entry for Qualcomm TSENS thermal drivers
Signed-off-by: Olof Johansson <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm ARM64 Updates for v4.21
* Add QCS404 base platform and nodes
* Add QCS404 EVB boards
* Add external SD and dependencies for MSM8998-mtp
* Add default scm compatible for MSM8998
* Fix XO clk name on MSM8998
* Add prng-ee nodes for SDM845 and MSM8996
* Add ADC die temp node for pm8998
* Fix documentation on QCOM ADC sample
* tag 'qcom-arm64-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (34 commits)
arm64: dts: qcom: msm8998: Fix compatible of scm node
arm64: dts: qcom: msm8998: Add SDC2 control pins
arm64: dts: qcom: msm8998-mtp: Add external SD
arm64: dts: qcom: msm8998: Add SDCC2
arm64: dts: qcom: msm8998: correct xo clock name
arm64: dts: qcom: pms405: Add pon and pwrkey nodes
arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2
arm64: dts: qcom: qcs404: Add BAM DMA node
arm64: dts: qcom: qcs404: add prng-ee node
arm64: dts: qcom: qcs404: Add remoteproc nodes
arm64: dts: qcom: qcs404: Add scm firmware node
arm64: dts: qcom: pms405: add gpios
arm64: dts: qcom: pms405: add rtc node
arm64: dts: qcom: qcs404: add spmi node
arm64: dts: qcom: pms405: add spmi node
arm64: dts: qcom: qcs404: Add sdcc1 node
arm64: dts: qcom: qcs404: Add TLMM pinctrl node
arm64: dts: qcom: qcs404: add smp2p nodes
arm64: dts: qcom: qcs404: Add PMS405 RPM regulators
arm64: dts: qcom: qcs404: Add RPM GLINK related nodes
...
Signed-off-by: Olof Johansson <[email protected]>
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There are more boards that can work with mmp2-dt than just Brownstone.
The OLPC XO-1.75 device tree root is compatible with "mrvl,mmp2" only.
The "mrvl,mmp2-brownstone" string is safe to remove: the Brownstone
device tree contains the "mrvl,mmp2" compatible string too.
Signed-off-by: Lubomir Rintel <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 4.21, please pull the following:
- Rafal relicenses a bunch of DTS files he wrote under the GPL 2.0+/MIT
license and adds proper SPDX license tags in the process
- Rene adds support for the Linksys EA6500 v2 Wi-Fi router based on
BCM4708 plus two BCM4360 and BCM4331 radios
- Phil documents and updates the vchiq mailbox compatible string in
order to establish a correct agreement between the Raspberry Pi
firmware and the ARM CPU's view of what an ARM CPU cache line size is,
he also fixes the mailbox "reg" property to be correctly expressed in
bytes
- Stefan updates the Raspberry Pi Zero DTS files to use SPDX tags
- Florian enables the SATA PHY and AHCI controller on the BCM63138 SoCs,
he also does a bit of refactoring of aliases for the Northstar Plus
DTS files
* tag 'arm-soc/for-4.21/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Describe Northstar pins mux controller
ARM: dts: BCM5301X: Add basic DT for Linksys EA6500 V2
ARM: dts: bcm2835-rpi-zero: Switch to SPDX identifier
ARM: dts: bcm283x: Correct mailbox register sizes
ARM: dts: bcm283x: Correct vchiq compatible string
dt-bindings: soc: Document "brcm,bcm2836-vchiq"
ARM: dts: NSP: Move aliases to bcm-nsp.dtsi
ARM: dts: BCM53573: Relicense SoC file to the GPL 2.0+ / MIT
ARM: dts: BCM63xx: Enable SATA AHCI and PHY for BCM963138DVT
ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
ARM: dts: BCM53573: Relicense Tenda AC9 file to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Relicense BCM47094 file to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Relicense BCM47081/BCM4709 files to the GPL 2.0+ / MIT
Signed-off-by: Olof Johansson <[email protected]>
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i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
[[email protected]: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <[email protected]>
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The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
[[email protected]: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <[email protected]>
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pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
[[email protected]: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <[email protected]>
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Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
[[email protected]: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <[email protected]>
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Mark as opp-suspend required devfreq Operating Performance Points to
fix resuming issues on Exynos 4 boards.
The patch is based on earlier work by Tobias Jakobi.
Suggested-by: Tobias Jakobi <[email protected]>
Suggested-by: Chanwoo Choi <[email protected]>
Reviewed-by: Chanwoo Choi <[email protected]>
Signed-off-by: Lukasz Luba <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The P2888 processor module contains a TI TMP451 temperature sensor with
two channels. These are used to measure the temperatures at different
locations on the module.
Signed-off-by: Thierry Reding <[email protected]>
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The power and force recovery buttons found on Jetson Xavier are hooked
up to two Tegra GPIOs. The power button can also function as a wake-up
source.
Signed-off-by: Thierry Reding <[email protected]>
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The AON GPIO controller is in an always-on power partition and typically
provides pins for functions that need to always work, such as the power
key for example.
Signed-off-by: Thierry Reding <[email protected]>
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The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <[email protected]>
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The RTC on Tegra194 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <[email protected]>
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Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <[email protected]>
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The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <[email protected]>
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The RTC on Tegra186 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <[email protected]>
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Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <[email protected]>
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In order for the correct interrupt type to be configured, the event
action for the power key needs to be "asserted".
Signed-off-by: Thierry Reding <[email protected]>
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Enable these thermal zones to be able to monitor their temperatures and
control the fan to cool down the system if necessary.
Signed-off-by: Thierry Reding <[email protected]>
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The NVIDIA Tegra194 SoC defines six thermal zones. Define all of them in
device tree.
Signed-off-by: Thierry Reding <[email protected]>
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Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies
from the PMIC to the display block. Also enable the display hub which is
responsible for instantiating the display controllers. Finally, enable
the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <[email protected]>
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Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.
Signed-off-by: Thierry Reding <[email protected]>
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Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.
Signed-off-by: Thierry Reding <[email protected]>
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Add initial version of device tree file for Facebook Backpack CMM
(Chasis Management Module) ast2500 BMC.
Signed-off-by: Tao Ren <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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This is the layout used by Facebook BMC systems. It describes the fixed
flash layout of a 32MB mtd device.
Signed-off-by: Tao Ren <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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The BMC can read the RTC battery voltage via ADC
channel 12.
Signed-off-by: Matt Spinler <[email protected]>
Reviewed-by: Lei YU <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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Add iio-hwmon-battery using adc channel 12 and enable adc to make
adc running. This channel is used to read RTC battery voltage.
Note with Romulus hardware design, it requires GPIOR3 to be pulled
high to read the voltage, otherwise the reading is 0.
When GPIOR3 is high, it consumes battery and impacts the battery life.
So it is left for user space to toggle the GPIO when trying to read the
voltage.
Signed-off-by: Lei YU <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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The Romulus USB bus is connected to the Power9's PCIe USB controller.
Signed-off-by: Joel Stanley <[email protected]>
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This adds the required LPC node with phandles to the reserved memory
region and the mtd device.
Signed-off-by: Joel Stanley <[email protected]>
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This allows userspace to switch away from bitbanging to use kernel
FSI with the coprocessor.
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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This replaces the FSI compatible with the ColdFire FSI compatible.
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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