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2020-04-28drm/amd/display: fix rn soc bb updateDmytro Laktyushkin1-43/+28
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: check if REFCLK_CNTL register is presentDmytro Laktyushkin1-1/+2
Check before programming the register since it isn't present on all IPs using this code. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Add DML variable for future asicsJoshua Aberback3-0/+3
Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: clean up some header pathsAnthony Koo5-9/+15
[Why] Some include paths don't need to have relative paths And some types missing [How] make some changes to headers and modify include path Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Fix DMUB meta offset for new load methodNicholas Kazlauskas1-3/+5
[Why] The new metadata offset is located at the end of the firmware binary without any additional padding. Firmware state is currently larger than 1024 bytes so new firmware state will hang when trying to access any data above 1024 bytes. [How] Specify the correct offset based on legacy vs new loading method. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Do not disable pipe split if mode is not supportedSung Lee1-2/+7
[WHY] If mode is not supported, pipe split should not be disabled. This may cause more modes to fail. [HOW] Check for mode support before disabling pipe split. This commit was previously reverted as it was thought to have problems, but those issues have been resolved. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: 3.2.82Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: bump version for invalidate L2 before SDMA IBsMarek Olšák1-1/+2
This fixes GPU hangs due to cache coherency issues. Bump the driver version. Split out from the original patch. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: invalidate L2 before SDMA IBs (v2)Marek Olšák2-1/+29
This fixes GPU hangs due to cache coherency issues. v2: Split the version bump to a separate patch Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add tiling flags from MesaMarek Olšák1-0/+4
DCC_INDEPENDENT_128B is needed for displayble DCC on gfx10. SCANOUT is not needed by the kernel, but Mesa uses it. Signed-off-by: Marek Olšák <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu/vcn2.5: wait for tiles off after unpauseJames Zhu1-3/+3
Wait for tiles off after unpause to fix transcode timeout issue. It is a work around. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/powerplay: avoid using pm_en before it is initialized revisedTiecheng Zhou1-2/+4
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to soc15_asic_reset (for V320 usecase, Vega10 asic), in which: 1) soc15_asic_reset_method calls to pp_get_asic_baco_capability (pm_en) 2) soc15_asic_baco_reset calls to pp_set_asic_baco_state (pm_en) pm_en is used in the above two cases while it has not yet been initialized So avoid using pm_en in the above two functions for V320 passthrough. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Tiecheng Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"Tiecheng Zhou1-2/+1
This reverts commit c5207876232649ca5e5ddd6f966d2da75ffded8f. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Tiecheng Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdkfd: Put ASIC revision into HSA capabilityJoseph Greathouse4-1/+16
In order to surface the ASIC revision to user level, we want to put it into the HSA topology. This can be because different ASIC revisions may require user-level software to do different things (e.g. patch code for things that are changed in later hardware revisions). The ASIC revision from the hardware is maximum of 4 bits at this time, so put it into 4 of the open bits in the HSA capability. Then user-level software can use this capability information to know -- for each ASIC -- what revision-based things must be done. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amd/display: remove conversion to bool in dc_link_ddc.cJason Yan1-1/+1
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:602:28-33: WARNING: conversion to bool not needed here Reviewed-by: Christian König <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amd/display: remove conversion to bool in dcn20_mpc.cJason Yan1-1/+1
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c:455:70-75: WARNING: conversion to bool not needed here Reviewed-by: Christian König <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: remove conversion to bool in amdgpu_device.cJason Yan1-1/+1
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3004:68-73: WARNING: conversion to bool not needed here Reviewed-by: Christian König <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: decouple EccErrCnt query and clear operationGuchun Chen1-4/+79
Due to hardware bug that when RSMU UMC index is disabled, clear EccErrCnt at the first UMC instance will clean up all other EccErrCnt registes from other instances at the same time. This will break the correctable error count log in EccErrCnt register once querying it. So decouple both to make error count query workable. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: switch to SMN interface to operate RSMU index modeGuchun Chen1-5/+24
This makes consistent with other regsiters' access in this module. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: drop redundant cg/pg ungate on runpm enterEvan Quan1-3/+0
CG/PG ungate is already performed in ip_suspend_phase1. Otherwise, the CG/PG ungate will be performed twice. That will cause gfxoff disablement is performed twice also on runpm enter while gfxoff enablemnt once on rump exit. That will put gfxoff into disabled state. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: move kfd suspend after ip_suspend_phase1Evan Quan1-2/+2
This sequence change should be safe as what did in ip_suspend_phase1 is to suspend DCE only. And this is a prerequisite for coming redundant cg/pg ungate dropping. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: sw pstate switch should only be for vega20Jonathan Kim1-1/+3
Driver steered p-state switching is designed for Vega20 only. Also simplify early return for temporary disable due to SMU FW bug. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-27drm/amdgpu: Remove unneeded semicolonZheng Bin1-1/+1
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2534:2-3: Unneeded semicolon Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zheng Bin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
2020-04-24amdgpu/dc: remove redundant assignment to variable 'option'Colin Ian King1-2/+1
The variable option is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu/gmc: Use consistent variable on unlocksColin Ian King2-2/+2
Currently the error returns paths are unlocking lock kiq->ring_lock however it seems this should be dev->gfx.kiq.ring_lock as this is the lock that is being locked and unlocked around the ring operations. This looks like a bug, but it's not. The kiq is just a local variable pointing to the same structure. Make it consistent. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amd/display: remove redundant assignment to variable retColin Ian King1-1/+1
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: protect ring overrunYintian Tao7-12/+61
Wait for the oldest sequence on the ring to be signaled in order to make sure there will be no command overrun. v2: fix coding stype and remove abs operation v3: remove the initialization of variable r Signed-off-by: Yintian Tao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: extent threshold of waiting FLR_COMPLETEMonk Liu2-2/+2
to 5s to satisfy WHOLE GPU reset which need 3+ seconds to finish Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: for nv12 always need smu ipMonk Liu1-2/+1
because nv12 SRIOV support one vf mode Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: skip sysfs node not belong to one vf modeMonk Liu1-20/+28
Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: enable one vf mode for nv12Monk Liu3-15/+52
Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: clear the messed up checking logicMonk Liu1-8/+3
for ARCTURUS+ ASICS, we always support SW_SMU for bare-metal and for SRIOV one_vf_mode Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used laterMonk Liu1-0/+3
Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: sriov is forbidden to call disable DPMMonk Liu1-0/+3
Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: skip cg/pg set for SRIOVMonk Liu1-0/+7
Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-24drm/amdgpu: ignore TA ucode for SRIOVMonk Liu1-0/+2
Signed-off-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: retire legacy vega10 sos version checkHawking Zhang1-27/+1
retired those early sos version used in vega10 bring up phase Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: switch to helper function to init sos ucodeHawking Zhang2-84/+6
call common helper function to init sos ucode, instead of duplicate codes per ip version Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: add helper function to init sos ucodeHawking Zhang2-0/+72
driver already had psp_firmware_header struture to deal with different layout of sos ucode. the sos micorcode initialization could be common one. Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: switch to helper function to init asd ucodeHawking Zhang4-75/+5
call common helper function to initialize asd ucode Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: add helper function to init asd ucodeHawking Zhang2-0/+38
asd is unified ucode across asic. it is not necessary to keep its software structure to be ip specific one Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: retire unused check_fw_loading statusHawking Zhang6-544/+0
The driver can't access UCODE_DATA/ADDR registers on production boards. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: remove unnecessary tOS version checkHawking Zhang3-16/+4
tOS version is available through debugfs interface Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: retire support_vmr_ring interfaceHawking Zhang5-66/+30
vmr ring is dedicated for sriov vf (i.e.guest driver in sriov), which is general communication interface between driver and psp fw accross all ip version. it is not correct to make it as ip specific callback. it is even worse to check specific tOS version per IP version (like psp_v11/v12). Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: shrink critical section in amdgpu_amdkfd_gpuvm_free_memory_of_gpuBernard Zhao1-7/+7
Reduce the mem->lock`s protected code area, no need to protect pr_debug. This also simplifies error handling. Signed-off-by: Bernard Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: Init data to avoid oops while reading pp_num_states.limingyu1-1/+4
For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1), the amdgpu will expose pp_num_states to the /sys directory. In this moment, read the pp_num_states file will excute the amdgpu_get_pp_num_states func. In our case, the data hasn't been initialized, so the kernel will access some ilegal address, trigger the segmentfault and system will reboot soon: uos@uos-PC:~$ cat /sys/devices/pci0000\:00/0000\:00\:00.0/0000\:01\:00 .0/pp_num_states Message from syslogd@uos-PC at Apr 22 09:26:20 ... kernel:[ 82.154129] Internal error: Oops: 96000004 [#1] SMP This patch aims to fix this problem, avoid that reading file triggers the kernel sementfault. Signed-off-by: limingyu <[email protected]> Signed-off-by: zhoubinbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: remove set but not used variable 'priority'YueHaibing1-2/+0
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c: In function amdgpu_job_submit: drivers/gpu/drm/amd/amdgpu/amdgpu_job.c:148:26: warning: variable priority set but not used [-Wunused-but-set-variable] commit 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init") left behind this, remove it. Reviewed-by: Christian König <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm: amdgpu: fix kernel-doc struct warningRandy Dunlap1-1/+1
Fix a kernel-doc warning of missing struct field desription: ../drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:92: warning: Function parameter or member 'vm' not described in 'amdgpu_vm_eviction_lock' Fixes: a269e44989f3 ("drm/amdgpu: Avoid reclaim fs while eviction lock") Signed-off-by: Randy Dunlap <[email protected]> Cc: Signed-off-by: Alex Sierra <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: David (ChunMing) Zhou <[email protected]> Cc: [email protected] Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm: amd/display: fix Kconfig help textRandy Dunlap1-6/+2
Fix help text: indent one tab + 2 spaces; end a sentence with a period; and collapse short lines of text to one line. Fixes: 23c61b4599c4 ("drm/amd: Fix Kconfig indentation") Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Randy Dunlap <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: request reg_val_offs each kiq read regYintian Tao7-29/+41
According to the current kiq read register method, there will be race condition when using KIQ to read register if multiple clients want to read at same time just like the expample below: 1. client-A start to read REG-0 throguh KIQ 2. client-A poll the seqno-0 3. client-B start to read REG-1 through KIQ 4. client-B poll the seqno-1 5. the kiq complete these two read operation 6. client-A to read the register at the wb buffer and get REG-1 value Therefore, use amdgpu_device_wb_get() to request reg_val_offs for each kiq read register. v2: fix the error remove v3: fix the print typo v4: remove unused variables Signed-off-by: Yintian Tao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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