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2013-12-11ARM: tegra: remove legacy DMA entries from DTStephen Warren3-39/+0
Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11ARM: tegra: remove legacy clock entries from DTStephen Warren3-32/+6
Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11USB: EHCI: tegra: use reset frameworkStephen Warren1-3/+11
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Alan Stern <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11Input: tegra-kbc - use reset frameworkStephen Warren1-3/+10
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Dmitry Torokhov <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11serial: tegra: convert to standard DMA DT bindingsStephen Warren1-18/+6
By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Acked-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11serial: tegra: use reset frameworkStephen Warren1-4/+10
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11spi: tegra: convert to standard DMA DT bindingsStephen Warren2-62/+34
By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]>
2013-12-11spi: tegra: use reset frameworkStephen Warren4-15/+42
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11staging: nvec: use reset frameworkStephen Warren2-4/+12
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Marc Dietrich <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11i2c: tegra: use reset frameworkStephen Warren1-3/+10
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Wolfram Sang <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11ASoC: tegra: convert to standard DMA DT bindingsStephen Warren8-60/+42
By passing no flags when calling snd_dmaengine_pcm_register() from tegra_pcm.c, we end up using dma_request_slave_channel() rather than dmaengine_pcm_compat_request_channel(), and hence rely on the standard DMA DT bindings and stashing the DMA slave ID away during channel allocation. This means there's no need to use a custom DT property to store the slave ID. So, remove all the code that parsed it. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]>
2013-12-11ASoC: tegra: allocate AHUB FIFO during probe() not startup()Stephen Warren1-44/+47
The Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only when an audio stream starts playback. This is theoretically nice for resource sharing, but makes no practical difference for any configuration the drivers currently support. However, this deferral prevents conversion to the standard DMA DT bindings, since conversion requires knowledge of the specific DMA channel to be allocated, which in turn depends on which specific FIFO was allocated. For this reason, move the FIFO allocation into probe() to allow later conversion to the standard DMA DT bindings. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]>
2013-12-11ASoC: tegra: call pm_runtime APIs around register accessesStephen Warren1-0/+32
Call pm_runtime_get_sync() before all register accesses; the HW requires clocks to be running when accessing registers. This hasn't been needed to date, since all register IO was performed while playback was active, and hence the ASoC core had already called pm_runtime_get(). However, an imminent future commit will allocate and set up the FIFOs and routing during probe(), when that "protection" won't be in place. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]>
2013-12-11ASoC: tegra: use reset frameworkStephen Warren3-34/+41
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. This change also renames "clock"/"clk" to "modules"/"mod" in symbols related to entries in configlink_clocks[], since: - We don't care about clock handles any more, but rather reset handles, so the old name isn't applicable. - It really is a list of modules on the bus, about which we currently only care about reset handles. If we start caring about any other aspect of the modules in the future, we won't have to rename all these symbols again. Note: The addition of "depends COMMON_CLOCK" is something that was missing before, not a new requirement. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Mark Brown <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11dma: tegra: register as an OF DMA controllerStephen Warren1-3/+36
Call of_dma_controller_register() so that DMA clients can look up the Tegra DMA controller using standard APIs. This requires the of_xlate() function to save off the DMA slave ID, and for tegra_dma_slave_config() not to over-write this information; once DMA client drivers are converted to dma_request_slave_channel() and DT-based lookups, they won't set this field of struct dma_slave_config anymore. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11dma: tegra: use reset frameworkStephen Warren1-3/+10
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Dan Williams <[email protected]> Acked-by: Vinod Koul <[email protected]>
2013-12-11ARM: tegra: pass reset to tegra_powergate_sequence_power_up()Stephen Warren4-8/+16
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-By: Terje Bergstrom <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Thierry Reding <[email protected]>
2013-12-11drm/tegra: use reset frameworkStephen Warren5-6/+39
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <[email protected]> Acked-By: Terje Bergstrom <[email protected]>
2013-12-11pci: tegra: use reset frameworkStephen Warren1-14/+36
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. The old Tegra-specific API used a struct clock to represent the module to reset. Some of the clocks retrieved during probe() were only used for reset purposes, and indeed aren't even true clocks. So, there's no need to get() them any more. Signed-off-by: Stephen Warren <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Thierry Reding <[email protected]>
2013-12-11clk: tegra: implement a reset driverStephen Warren6-6/+57
The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-By: Peter De Schrijver <[email protected]>
2013-12-11ARM: tegra: select the reset frameworkStephen Warren1-0/+2
The Tegra clock driver is built unconditionally when Tegra support is enabled. In order to avoid having to ifdef the forthcoming reset driver implementation, have ARCH_TEGRA select RESET_CONTROLLER. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11ARM: tegra: update DT files to add DMA propertiesStephen Warren3-0/+119
This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2013-12-11ARM: tegra: update DT files to add reset propertiesStephen Warren4-4/+266
An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <[email protected]>
2013-12-11ARM: tegra: document use of standard DMA DT bindingsStephen Warren9-29/+73
Update all the Tegra DT bindings to require the standard dmas/dma-names properties rather than non-standard nvidia,dma-request-selector property. This is a DT-ABI-incompatible change. It is the second of two changes required for me to consider the Tegra DT bindings as stable, the other being the previous conversion to the common reset bindings. Signed-off-by: Stephen Warren <[email protected]>
2013-12-11ARM: tegra: document reset properties in DT bindingsStephen Warren21-9/+181
Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <[email protected]> Acked-By: Terje Bergstrom <[email protected]>
2013-12-11ARM: tegra: add missing clock documentation to DT bindingsStephen Warren28-42/+173
Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <[email protected]> Acked-By: Terje Bergstrom <[email protected]>
2013-12-11Merge tag 'clk-tegra-for-3.14' into for-3.14/dmas-resets-reworkStephen Warren20-3013/+5091
Tegra clk branch for 3.14
2013-12-11Merge tag 'asoc-dma-v3.14' into for-3.14/dmas-resets-reworkStephen Warren3-22/+123
ASoC: dma: Generic ASoC dmaengine driver enhancements This is the work so far on dmaengine for v3.14, it is being cross merged into the Tegra tree to support a large DMA overhaul there. The main additions are a change in the DMA request API which allows better interaction at system startup using deferred probes and methods for overriding the default device and channel names used to request DMA.
2013-12-11Merge branch 'for-3.14/deps-from-dma-of' into for-3.14/dmas-resets-reworkStephen Warren3-23/+36
This merges git://git.infradead.org/users/vkoul/slave-dma.git topic/of
2013-12-11Merge branch 'for-3.14/deps-from-dma-defer_probe' into ↵Stephen Warren3-10/+48
for-3.14/dmas-resets-rework This merges git://git.infradead.org/users/vkoul/slave-dma.git topic/defer_probe
2013-12-11Merge remote-tracking branches 'regulator/fix/as3722' and ↵Mark Brown2-2/+2
'regulator/fix/pfuze100' into regulator-linus
2013-12-11drm/i915: Parametrize the dphy and other spec specific parametersShobhit Kumar2-15/+28
The values of these parameters will be different for differnet panel based on dsi rate, lane count, etc. Remove the hardcodings and make these as parameters whch will be initialized in panel specific sub-encoder implementaion. This will also form groundwork for planned generic panel sub-encoder implemntation based on VBT design enhancments to support multiple panels v2: Mask away the port_bits before use Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Remove redundant DSI PLL enablingShobhit Kumar1-3/+0
DSI PLL will get configured during crtc_enable using ->pre_pll_enable and no need to do in ->mode_set Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Reorganize the DSI enable/disable sequenceShobhit Kumar2-33/+79
Basically ULPS handling during enable/disable has been moved to pre_enable and post_disable phases. PLL and panel power disable also has been moved to post_disable phase. The ULPS entry/exit sequneces as suggested by HW team is as follows - During enable time - set DEVICE_READY --> Clear DEVICE_READY --> set DEVICE_READY And during disable time to flush all FIFOs - set ENTER_SLEEP --> EXIT_SLEEP --> ENTER_SLEEP Also during disbale sequnece sub-encoder disable is moved to the end after port is disabled. v2: Based on comments from Ville - Detailed epxlaination in the commit messgae - Moved parameter changes out into another patch - Backlight enabling will be a new patch v3: Updated as per Jani's comments - Removed the I915_WRITE_BITS as it is not needed - Moved panel_reset and send_otp_cmds hooks to dsi_pre_enable - Moved disable_panel_power hook to dsi_post_disable - Replace hardcoding with AFE_LATCHOUT v4: Make intel_dsi_device_ready and intel_dsi_clear_device_ready static Signed-off-by: Yogesh Mohan Marimuthu <[email protected]> Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar1-10/+20
Basically check for both +ive and -ive deviation from target clock and pick the one with minimal error. If we get a direct match, break from loop to acheive some optimization. v2: Use signed variable for target and calculated dsi clock values Signed-off-by: Vijayakumar Balakrishnan <[email protected]> Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Compute dsi_clk from pixel clockShobhit Kumar1-58/+31
Pixel clock based calculation is recommended in the MIPI host controller documentation v2: Based on review comments from Jani and Ville - Use dsi_clk in KHz rather than converting in Hz and back to MHz - RR formula is retained though not used but return dsi_clk in KHz now - Moved the m-n-p changes into a separate patch - Removed the parameter check for intel_dsi->dsi_clock_freq. This will be bought back in if needed when appropriate panel drivers are done v3: Removed the unused mnp calculation from static table Signed-off-by: Vijayakumar Balakrishnan <[email protected]> Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Use FLISDSI interface for band gap resetShobhit Kumar4-39/+25
v2: Rebased on latest code Signed-off-by: Shobhit Kumar <[email protected]> Signed-off-by: Yogesh Mohan Marimuthu <[email protected]> Reviewed-by: Jani Nikula<[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Add more dev ops for MIPI sub encoderShobhit Kumar2-1/+13
Some panels require one time programming if they do not contain their own eeprom for basic register initialization. The sequence is Panel Reset --> Send OTP --> Enable Pixel Stream --> Enable the panel v2: Based on review comments from Jani and Ville - Updated the commit message with more details - Move the new parameters out of this patch Signed-off-by: Yogesh Mohan Marimuthu <[email protected]> Signed-off-by: Shobhit Kumar <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Decrease gen2 vco frequency minimum to 908 MHzVille Syrjälä1-3/+3
On my 855 machine the BIOS uses the following DPLL settings: DPLL 0x90016000 FP0 = 0x61207 FP1 = 0x21207 With the 66MHz SSC refclock, that puts the BIOS generated VCO frequency at ~908 MHz, which is lower than the 930 MHz limit we have currently. This also results in the pixel clock coming out significantly higher than the requested 65 MHz when we try to recompute it. Reduce the the VCO limit to 908 MHz. Combined with the earlier SSC reference clock accuracy fix, this results in the pixel clock coming out as 65.08 MHz which is quite close to the target. For some reason the BIOS uses 64.881 MHz, which isn't quite as close. This makes kms_flip wf_vblank-ts-check pass for the first time on this machine \o/ Cc: Bruno Prémont <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Bruno Prémont <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Fix 66 MHz LVDS SSC freq for gen2Ville Syrjälä2-11/+10
Store the SSC refclock frequency in kHz to get more accuracy. Currently we're pretending that 66 MHz is ~66000 kHz, when in fact it is actually ~66667 kHz. By storing the less rounded kHz value we get a much better accuracy for out pixel clock calculations. Cc: Bruno Prémont <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Bruno Prémont <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Increase gen2 vco frequency limit to 1512 MHzVille Syrjälä1-3/+3
Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen. The VBT mode is as follows: 0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa The BIOS uses the following DPLL settings: DPLL = 0x90020000 FP0 = 0x2140e FP1 = 0x21207 That puts the BIOS generated VCO frequency at 1512 MHz, which is higher than the 1400 MHz limit we have currently. Let's bump the VCO limit to 1512 MHz and see what happens. Cc: Bruno Prémont <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Bruno Prémont <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Change N divider minimum from 3 to 2 for gen2Ville Syrjälä1-3/+3
Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen. The VBT mode is as follows: 0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa The BIOS uses the following DPLL settings: DPLL = 0x90020000 FP0 = 0x2140e FP1 = 0x21207 We can't generate that pixel clock currently as we're limiting the N divider to at least 3, whereas the BIOS uses a value of 2. Let's reduce the N minimum to 2 and see what happens. Cc: Bruno Prémont <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Bruno Prémont <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Extract p2 divider correctly for gen2 LVDS dual channelVille Syrjälä1-2/+7
In order to determine the correct p2 divider for LVDS on gen2, we need to check the CLKB mode from the LVDS port register to determine if we're dealing with single or dual channel LVDS. Cc: Bruno Prémont <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Bruno Prémont <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Record BB_ADDR for every ringVille Syrjälä3-8/+9
Every ring seems to have a BB_ADDR registers, so include them all in the error state. v2: Also include the _UDW on BDW Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: Use 32bit read for BB_ADDRVille Syrjälä1-1/+1
The BB_ADDR register is documented to be 32bits at least since SNB. Prior to that the high 32bits were listed as MBZ, so using a 64bit read doesn't seem worth anything. Also the simulator doesn't like the 64bit read. So just switch to using a 32bit read instead. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: fix VDD override off waitPaulo Zanoni1-1/+3
If we're disabling the VDD override bit and the panel is enabled, we don't need to wait for anything. If the panel is disabled, then we need to actually wait for panel_power_cycle_delay, not panel_power_down_delay, because the power down delay was already respected when we disabled the panel. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11drm/i915: don't touch the VDD when disabling the panelPaulo Zanoni2-10/+2
I don't see a reason to touch VDD when we're disabling the panel: since the panel is enabled, we don't need VDD. This saves a few sleep calls from the vdd_on and vdd_off functions at every modeset. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69693 Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> [danvet: Fix the patch mangle wiggle has done ... Spotted by Paulo. Also drop the runtime_pm_put call which now has to go due to different patch ordering. Also from Paul.] Signed-off-by: Daniel Vetter <[email protected]>
2013-12-11ASoC: dmaengine: fix deferred probe detectionStephen Warren1-1/+1
Check the return value of dma_request_slave_channel_reason() to see if deferred probe happens, not the variable the return value will be assigned to later. Reported-by: kbuild test robot <[email protected]> Fixes: 5eda87b890f8 ("ASoC: dmaengine: support deferred probe for DMA channels") Signed-off-by: Stephen Warren <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2013-12-11Revert "8390 : Replace ei_debug with msg_enable/NETIF_MSG_* feature"David S. Miller16-426/+302
This reverts commit 99023e90fe5c147ea0665bda86764ea44f08a622. Accidently checked this into 'net' instead of 'net-next'. Signed-off-by: David S. Miller <[email protected]>
2013-12-118390 : Replace ei_debug with msg_enable/NETIF_MSG_* featureMatthew Whitehead16-302/+426
Removed the shared ei_debug variable. Replaced it by adding u32 msg_enable to the private struct ei_device. Now each 8390 ethernet instance has a per-device logging variable. Changed older style printk() calls to more canonical forms. Tested on: ne, ne2k-pci, smc-ultra, and wd hardware. V4.0 - Substituted pr_info() and pr_debug() for printk() KERN_INFO and KERN_DEBUG V3.0 - Checked for cases where pr_cont() was most appropriate choice. - Changed module parameter from 'debug' to 'msg_enable' because debug was no longer the best description. V2.0 - Changed netif_msg_(drv|probe|ifdown|rx_err|tx_err|tx_queued|intr|rx_status|hw) to netif_(dbg|info|warn|err) where possible. Signed-off-by: Matthew Whitehead <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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