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2014-09-15drm/nouveau/fb/ram: Support strided regsRoy Spliet2-9/+38
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nv50/fb/ram: Store the number of partitions in the designated fieldsRoy Spliet2-10/+9
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nv50/kms: Set VBLANK time in modeset scriptRoy Spliet1-3/+8
Solves blinking on reclocking memory. The value set is an underestimate, but with non-reduced vblanking this should give us plenty of time Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: Add rammap support for version 1.0Roy Spliet1-0/+4
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gf100-/pwr/memx: block host and fifo around reclockBen Skeggs4-474/+632
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/memx: fix command ordering around block/unblockBen Skeggs7-462/+461
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/memx: rename fb off/on to block/unblockBen Skeggs6-22/+22
More accurate as to the function of the opcodes. Not only is FB disabled, but the host is prevented from touching the GPU. An upcoming patch for Kepler will also halt PFIFO (as NVIDIA does). Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: Pause the GPU before reclockingRoy Spliet3-26/+66
V2: always call post correctly even if pre fails V3: move function prototype to nva3.h Signed-off-by: Roy Spliet <[email protected]>
2014-09-15drm/nouveau/gpio: rename g92 class to g94Emil Velikov7-30/+30
nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <[email protected]> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: [email protected] # 3.16+ Signed-off-by: Emil Velikov <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104-/fb/ram: move fb enable/disable to same place as nvidiaBen Skeggs1-5/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104/fb/ram: twiddle some more bits when reclockingBen Skeggs1-1/+98
*when* this is done is only a rough approximation of what the binary driver does.. need to investigate more to see if it matters Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: parse another large chunk of random memory config dataBen Skeggs2-1/+24
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104-/fb/ram: perform certain steps only when bios data differsBen Skeggs1-19/+34
Awful, awful. But, on the GK106 I have, some upcoming patches show that this is actually necessary after all. Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104-/fb/ram: parse ramcfg data for all frequencies up-frontBen Skeggs2-48/+89
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104-/fb/ram: use parsed timing data in mr routinesBen Skeggs2-6/+11
All the other chipsets should be moved over to this too. It's not needed yet for the upcoming commits, so left this step as it'll conflict badly with Roy's GT21x reclocking work. Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: parse freq ranges and timing id into ramcfg structBen Skeggs7-26/+47
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: memset dcb struct to zero before parsingBen Skeggs1-0/+1
Fixes type/mask calculation being based on uninitialised data for VGA outputs. Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104/fb/ram: make use of training data provided by vbiosBen Skeggs1-43/+138
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: add support for parsing table at BIT 'M' v2 + 0x09Ben Skeggs3-0/+168
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios: add support for parsing table at BIT 'M' v2 + 0x05Ben Skeggs3-1/+170
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104/fb/ram: fix register for second set of training dataBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104/fb/ram: more random magic in fb initBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gk104/fb/ram: skip table entry for mode we're already inBen Skeggs1-11/+12
NVIDIA binary driver appears to, not sure if it's for a good reason, but grasping at straws for some GDDR5 reclocking issues here. Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/fb/sddr2: Generate MR valuesRoy Spliet3-0/+98
V2: Always disable DLL reset Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/fb/sddr3: Expand MR generationRoy Spliet1-10/+33
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/pwr/memx: Match blob's fb access behaviourRoy Spliet2-427/+446
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/memx: Return debugging informationRoy Spliet6-1412/+1438
Time measured from disabling FB to re-enabling, PPWR_IN reveals status of heads at the end of script. Helps debug various issues (like flicker). Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/memx: Make FB disable and enable explicitRoy Spliet6-6/+43
Needs to be done after wait-for-VBLANK, and NVA3 requires register writes in between. Rather than hard-coding register writes, just split out fb_disable and fb_enable. v2. Squashed "fb/ramnve0: disable fb before reclocking" Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/pwr/memx: Implement "wait for VBLANK"Roy Spliet9-994/+1356
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/therm/nv84+: do not expose non-calibrated internal temp sensorMartin Peres1-1/+6
Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/therm: make sure the temperature settings are sane on nv84+Martin Peres4-1/+35
One of my nv92 has a calibrated internal sensor but it displays 0°C as the default values use sw calibration values to force the temperature to 0. Since we cannot read the temperature from the adt7473 present on this board, let's re-enable the internal reading! Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/subdev: add a pfuse subdev v2Martin Peres12-0/+363
We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: Set intermediate core clock on reclockingRoy Spliet3-14/+51
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: For PLL clocks always make sure the PLL is not in useRoy Spliet1-0/+9
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: Abort when PLL doesn't lockRoy Spliet1-1/+5
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: HOST clockRoy Spliet2-8/+78
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: Set PLL refclkRoy Spliet3-29/+48
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nva3/clk: Parse clock control registers more accuratelyRoy Spliet1-4/+28
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau: Fix duplicate definition of NV04_PFB_BOOT_0_*Pierre Moreau3-32/+24
Signed-off-by: Pierre Moreau <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau: Display Nouveau boot options at launchPierre Moreau9-6/+37
It can help to remove any ambiguity about which options were passed to Nouveau, especially in case the user had some options set in /etc/modprobe.d/*.conf that he forgot about, as they won't appear in a dmesg. Signed-off-by: Pierre Moreau <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr: wait for scrubbers to finish before uploading new ucodeBen Skeggs1-3/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/fuc: make $r1-$r10 registers callee-saved in kernel.fucMartin Peres5-736/+749
Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr/fuc: add ld/st macrosMartin Peres1-0/+10
Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr: add helpers for delay-to-ticks and ticks-to-delayMartin Peres9-2284/+2446
Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr: add some arith functions (mul32_32_64, subu64 and addu64)Martin Peres10-1735/+1919
Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/pwr: fix the timers implementation with concurent processesMartin Peres5-990/+1133
The problem with the current implementation is that adding a timer improperly checked which process would time up first by not taking into account how much time elapsed since their timer got scheduled. Rework the re-scheduling decision t fix this. The catch with this fix is that we are limited to scheduling timers of up to 2^31 ticks to avoid any potential overflow. Since we are unlikely to need to wait for more than a second, this won't be a problem :) Another possible fix would be to decrement the timeouts of all processes but it would duplicate a lot of code and dealing with edge cases wasn't pretty last time I checked. Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/ppwr: enable ppwr on gm107Martin Peres2-1/+5
For some reason, it is now required to wait a 20 µs after the 0x200 reset of the engine. Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/gm107/therm: add PWM fan support v2Martin Peres7-6/+106
v2: change the copyright ownership from "Nouveau Community" to myself, as per Illia's recommendation. Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/therm/fan: do not use the pwm mode when the vbios tells us to ↵Martin Peres1-1/+7
use toggle Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-09-15drm/nouveau/bios/fan: add support for maxwell's fan management table v2Martin Peres4-1/+111
Re-use the therm-exported fan structure with only two minor modifications: - pwm_freq: u16 -> u32; - add fan_type (toggle or PWM) v2: - Do not memset the table to 0 as it erases the pre-set default values Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
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