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2017-12-04drm/amd/display: Cleanup code that enables freesyncLeo (Sunpeng) Li1-36/+19
This is a follow-up patch to: Bhawanpreet Lakha Atomic freesync ASSERT fix Changes: - Combine to use one iterator - Use new DRM iterators. Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Atomic freesync ASSERT fixBhawanpreet Lakha1-0/+27
Changes to atomic set property for freesync. Now In set property, just set the freesync variables and return 0. Based on the variables call mod_freesync_set_user_enable() inside commit_tail Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: add mod_freesync_user_enable to dm_connector_stateAlex Deucher1-0/+1
We don't currently expose variable refresh rate, but add the state to the connector state to make it easier to maintain the support for it from a hw support perspective while we figure out the uapi for drm. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: DMCU FW loading from PSPAnthony Koo4-7/+202
Update the programming sequence to allow DMCU firmware to be loaded by PSP. This code detects whether the firmware is loaded and does a check to verify the expected interface version and checks for correct response from micro controller. Added registry key method to allow force loading of firmware from kernel mode driver for test purposes. This is old method of firmware loading without PSP. Moved some init sequences into dc/dmcu. Changed loading sequence to initialize IRAM after firmware completely loaded. Firmware will now disable features that use IRAM until initialized. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Set cursor position as per address.Yongqiang Sun1-3/+4
In case of pipe split, cursor position should also be programmed as per cursor address. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Explicit casting for grph object idsHarry Wentland1-6/+6
C++ compilers don't like the implicit conversion Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: cleaning up hubp for dcnYue Hin Lau3-192/+193
removing duplicate functions, renaming struct mi_regs, etc. Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Clean some unneeded defines from ddc_service_types.hHarry Wentland1-33/+0
Remove defines we no longer need Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Cleanup some fail labels in dcn10_resourceHarry Wentland1-24/+13
Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Adding DCN1 registersMikita Lipski1-3/+30
Registers added to definition list that are required for multi display synchronization Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Check cursor address before program.Yongqiang Sun1-1/+2
Program cursor attributes during set mode is only needed in case of pipe slipt, bottom pipe should be programmed same as top pipe. Need to program if address is 0. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Move lock to front end program.Yongqiang Sun3-52/+29
Moved lock and unlock to apply_ctx_to_surface, since all the front end programming is within apply_ctx_to_surface. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/display: Add APU cap in dc_capsAnthony Koo5-0/+6
Some features should only be enabled on APUs or should not be enabled on APUs. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: delete duplicated code.Rex Zhu1-2/+0
the variable ref_clock was assigned same value twice in same function. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/pp: delete an outdated comment in amd_powerplay.cRex Zhu1-3/+0
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/pp: implement notify_smu_memory_info on PowerplayRex Zhu1-0/+36
Used to set up smu power logging. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: add new pp function point notify_smu_memory_infoRex Zhu2-0/+11
Used to set up smu power logging. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: add header kgd_pp_interface.hRex Zhu5-267/+293
move powerplay and amdgpu shared structures and definitions to kgd_pp_interface.h. This is the interface between the base driver and powerplay. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: move struct amd_powerplay to amdgpu.hRex Zhu2-7/+7
Clean up the interface. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/powerplay: move functions to amd_pm_funcs tableRex Zhu3-108/+90
those functions are exported to DC Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.hRex Zhu2-143/+144
Move the display/power interfaces to one place. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: remove extra parameter from amdgpu_ttm_bind() v2Christian König4-6/+6
We always use the BO mem now. v2: minor rebase Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: don't wait interruptible while binding GART spaceChristian König1-1/+1
Display can't seem to handle this correctly. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: fix pin domain compatibility checkChristian König1-1/+1
We need to test if any domain fits, not all of them. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: always bind pinned BOsChristian König1-7/+7
We always need to bind pinned BOs, not just when the caller requested the address. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: use the actual placement for pin accountingChristian König1-0/+2
This allows us to specify multiple possible placements again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: retry init if it fails due to exclusive mode timeout (v3)pding2-2/+23
The exclusive mode has real-time limitation in reality, such like being done in 300ms. It's easy observed if running many VF/VMs in single host with heavy CPU workload. If we find the init fails due to exclusive mode timeout, try it again. v2: - rewrite the condition for readable value. v3: - fix typo, add comments for sleep Acked-by: Alex Deucher <[email protected]> Signed-off-by: pding <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu/virt: implement wait_reset callbacks for vi/aipding2-0/+7
Reviewed-by: Monk Liu <[email protected]> Signed-off-by: pding <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/powerplay: describe the PCIE link speed in right GT/sEvan Quan3-9/+9
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu/virt: add wait_reset virt opspding2-0/+18
Driver can use this interface to check if there's a function level reset done in hypervisor. It's helpful when IRQ handler for reset is not ready, or special handling is required. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: pding <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu/virt: add function to check MMIO (v2)pding2-0/+9
MMIO space can be blocked on virtualised device. Add this function to check if MMIO is blocked or not. Todo: need a reliable method such like communation with hypervisor. v2: - add comments inline Signed-off-by: pding <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: avoid soft lockup when waiting for RLC serdes (v2)pding2-0/+16
Normally all waiting get timeout if there's one. Release the lock and return immediately when timeout happens. v2: - set the se_sh to broadcase before return Acked-by: Alex Deucher <[email protected]> Signed-off-by: pding <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: change redundant init logs to debug levelpding24-50/+47
When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: pding <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:implement ctx query2Monk Liu2-0/+45
this query will give flag bits to indicate what happend on the given context Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:don't change ctx->reset_couner upon queryMonk Liu2-2/+4
reset_counter marks the reset counter number once the context is created, shouldn't be changed due to query. To keep U/K interface on the ctx_query and keep ctx's reset_counter logic compatible with GPU RESET feature, now use another var named "reset_counter_query" to replace the original checked & updated in amdgpu_ctx_query. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: Remove job->s_entity to avoid keeping reference to stale pointer.Andrey Grodzovsky5-22/+22
Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: Fix deadlock during GPU reset.Andrey Grodzovsky3-47/+29
Bug: Kfifo is limited at size, during GPU reset it would fill up to limit and the pushing thread (producer) would wait for the scheduler worker to consume the items in the fifo while holding reservation lock on a BO. The gpu reset thread on the other hand blocks the scheduler during reset. Before it unblocks the sceduler it might want to recover VRAM and so will try to reserve the same BO the producer thread is already holding creating a deadlock. Fix: Switch from kfifo to SPSC queue which is unlimited in size. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: Add SPSC queue to scheduler.Andrey Grodzovsky1-0/+121
It is intended to sabstitute the bounded fifo we are currently using. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:cleanup job reset routine(v2)Monk Liu3-4/+33
merge the setting guilty on context into this function to avoid implement extra routine. v2: go through entity list and compare the fence_ctx before operate on the entity, otherwise the entity may be just a wild pointer Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:skip job for guilty ctx in parser_initMonk Liu1-0/+6
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:pass ctx->guilty address to entity initMonk Liu2-1/+2
this way the real interested guilty is connected to entity->guilty pointer, and we can use entity->pointer later in gpu recovery procedure Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amd/scheduler:introduce guilty pointer memberMonk Liu10-11/+13
this member will be used later, it will points to the real var inside of context and CS_SUBMIT & gpu schdduler can decide if skip a job depends on context->guilty or *entity->guilty Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:add hang_limit for sched(v2)Monk Liu3-3/+8
since gpu_scheduler source domain cannot access amdgpu variable so need create the hang_limit membewr for sched, and it can refer it for the upcoming GPU RESET patches v2: make hang_limit a parameter of sched_init() Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu:cleanup force_completionMonk Liu3-27/+11
cleanups, now only operate on the given ring Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: Avoid accessing job->entity after the job is scheduled.Andrey Grodzovsky4-23/+18
Bug: amdgpu_job_free_cb was accessing s_job->s_entity when the allocated amdgpu_ctx (and the entity inside it) were already deallocated from amdgpu_cs_parser_fini. Fix: Save job's priority on it's creation instead of accessing it from s_entity later on. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm: rcar-du: Clip planes to screen boundariesLaurent Pinchart3-33/+62
Unlike the KMS API, the hardware doesn't support planes exceeding the screen boundaries or planes being located fully off-screen. We need to clip plane coordinates to support the use case. Fortunately the DRM core offers a drm_atomic_helper_check_plane_state() helper that validates the scaling factor and clips the plane coordinates. Use it to implement the plane atomic check and use the clipped source and destination rectangles from the plane state instead of the unclipped source and CRTC coordinates to configure the device. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2017-12-04drm: rcar-du: Share plane atomic check code between Gen2 and Gen3Laurent Pinchart3-31/+22
The plane atomic check implementation is identical on Gen2 (DU planes) and Gen3 (VSP planes), but two separate functions exist as they operate on different data structures. Refactor the code to share the implementation. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Kieran Bingham <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2017-12-04v4l: vsp1: Start and stop DRM pipeline independently of planesLaurent Pinchart1-10/+27
The KMS API supports enabling a CRTC without any plane. To enable that use case, we need to start the pipeline when configuring the LIF, instead of when enabling the first plane. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Kieran Bingham <[email protected]> Reviewed-by: Kieran Bingham <[email protected]> Acked-by: Mauro Carvalho Chehab <[email protected]>
2017-12-04drm: rcar-du: Remove unused CRTC suspend/resume functionsKieran Bingham1-35/+0
An early implementation of suspend-resume helpers are available in the CRTC module, however they are unused and no longer needed. With suspend and resume handled by the core DRM atomic helpers, we can remove the unused functions. Signed-off-by: Kieran Bingham <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]>
2017-12-04drm: rcar-du: Implement system suspend/resume supportKieran Bingham2-3/+16
To support system suspend operations we must ensure the hardware is stopped, and resumed explicitly from the suspend and resume handlers. Implement suspend and resume functions using the DRM atomic helper functions. Signed-off-by: Kieran Bingham <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]>
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