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2017-12-06drm/amd/display: Report pitch_alignment for DCNAndrew Jiang2-1/+2
Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: combine output signal and signalEric Yang2-11/+6
output signal used to be a public member to be used by DM to override the stream signal. Now since there is no longer separation between public and private part of stream, they are combined. The overriding was not working properly as well, which is addressed by this change Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: A few more color indentation changesHarry Wentland6-165/+96
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Remove unused register read in program_pwlHarry Wentland1-3/+0
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Bunch more color indentation cleanupsHarry Wentland2-89/+69
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Remove extra arr_points elementHarry Wentland5-17/+3
arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.16Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: always call set output tfEric Yang1-1/+7
Temporary solution to fix gamma adjustment not working. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Fixed not set scaler bug.Yongqiang Sun1-1/+3
New scaler parameter assign to dpp is after early return, cause next flip scaler not program. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.15Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Remove unused OPP functions from interfaceEric Bernstein1-9/+0
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix dcn10_hubbub_wm_read_stateKen Chalmers1-8/+18
The ALLOW_SR registers might not always be available. Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Add transfer function to dc_surface_updateSivapiriyanKumarasamy1-0/+2
Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: send display_count msg so SMU can enter S0i2Hersen Wu5-2/+23
SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by: Hersen Wu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Modified front end initiail in init_hwYongqiang Sun5-17/+74
Optimized front end initial sequence, reset MPC module properly. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: add warning on long reg_waitDmytro Laktyushkin1-1/+6
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: remove unnecessary waits in dcn10Dmytro Laktyushkin3-32/+3
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix uninitialized variable warningDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix regamma programmingDmytro Laktyushkin4-25/+6
When new coefficients match cached we would skip setting regamma mode Also, when doing a stream update we would program regamma for all pipes, even thos that are not yet powered on. This resulted in never setting regamma since we would cache before the pipe is powered. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Fix some more color indentationsHarry Wentland4-61/+36
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Bunch of indentation cleanups in color stuffHarry Wentland2-112/+68
Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Refactor disable front end pipes.Yongqiang Sun5-138/+154
There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.14Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: renaming dpp function to follow naming conventionYue Hin Lau3-42/+43
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Yuehin Lau <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.13Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: call set csc_default if enable adjustment is falseYue Hin Lau4-6/+6
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Add OPP DPG blank functionEric Bernstein3-62/+51
Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.12Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: cache pwl params and scl_data to avoid extra programmingDmytro Laktyushkin5-38/+30
This saves us about 5000 reg writes per full update. This translates to about 40000 writes over the course of single eDP bootup. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Don't use dc_link in link_encoderAndrew Jiang10-55/+57
dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Both timing_sync and multisync need stream_count > 1Harry Wentland1-1/+2
Previous code threw a warning about misleading indentation Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Add tg_init interface.Yongqiang Sun4-1/+15
Clear OPTC underflow status when init_hw. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Enalbe blank data double buffer after mpc disconnected.Yongqiang Sun2-5/+16
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: get remote dpcd caps for timing validationEric Yang4-3/+30
Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Only update dchub if hubbub is availableYue Hin Lau1-1/+2
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Call ipp_program_bias_and_scale only if availableEric Bernstein2-9/+10
Also move some register definitions to common DCN regs. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.11Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: hubbub function flipping true and falseYue Hin Lau2-3/+3
no logic change Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Do post_update_surfaces on new stateCharlene Liu1-4/+4
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: function renaming for hubbubYue Hin Lau3-37/+43
following the naming convention with correct prefix Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: create new function prototype update_dchub for dcnYue Hin Lau2-2/+6
dcn version of update_dchub now uses hubbub instead of hwseq Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu/virt: remove redundant variable pf2vf_verColin Ian King1-2/+0
Variable pf2vf_ver is assigned but never read, it is redundant and hence can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 'pf2vf_ver' is never read Reivewed-by: Horace Chen <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/amdgpu: fix UVD mc offsetsPiotr Redlewski5-4/+8
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König <[email protected]> Signed-off-by: Piotr Redlewski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Multi display synchronization logicMikita Lipski11-66/+456
This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu: Implement BO size validation V2Andrey Grodzovsky1-0/+41
Validates BO size against each requested domain's total memory. v2: Make GTT size check a MUST to allow fall back to GTT. Rmove redundant NULL check. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu: cleanup vm_size handlingChristian König6-24/+17
It's pointless to have the same value twice, just always use max_pfn. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE resultChristian König15-113/+113
Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu: use dep_sync for CS dependency/syncobjChunming Zhou1-2/+2
Otherwise, they could be optimized by scheduled fence. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu/gfx8: Fix compute ring failure after resettingXiangliang.Yu1-3/+7
Do ring clear before ring test, otherwise compute ring test will fail after gpu resetting. Still can't find the root cause, just workaround it. Signed-off-by: Xiangliang.Yu <[email protected]> Acked-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/ttm: remove ttm_bo_unreserve_ticketChristian König2-14/+1
Just another alias for ttm_bo_unreserve. Signed-off-by: Christian König <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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