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2011-05-24mmc: quirks: Add/remove quirks conditional support.Andrei Warkentin1-4/+36
Conditional add/remove quirks for MMC and SD. Signed-off-by: Andrei Warkentin <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: Add new VUB300 USB-to-SD/SDIO/MMC driverTony Olech4-0/+2545
Add a driver for Elan Digital System's VUB300 chip which is a USB connected SDIO/SDmem/MMC host controller. A VUB300 chip enables a USB 2.0 or USB 1.1 connected host computer to use SDIO/SD/MMC cards without the need for a directly connected, for example via PCI, SDIO host controller. Signed-off-by: Anthony F Olech <[email protected]> [cjb: various punctuation and style fixes] Tested-by: Chris Ball <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci-pxa: Add quirks for DMA/ADMA to match h/wPhilip Rakity1-1/+6
32 Bit DMA/ADMA Access 32 Bit Size Support ADMA End Descriptor in current chain (no need for dummy entry) Signed-off-by: Philip Rakity <[email protected]> Tested-by: Chris Ball <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: core: duplicated trial with same freq in mmc_rescan_try_freq()Jaehoon Chung1-1/+1
mmc_rescan_try_freq() tries to init two times with the last frequency. For example, if host->f_min is 400KHz, we see the message below: mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz Andy Ross says that he didn't try this code on a board with an f_min that exactly matches one of the table entries, which explains why the bug wasn't detected. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Cc: Andy Ross <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: core: add support for eMMC Dual Data RatePhilip Rakity4-19/+33
eMMC voltage change not required for 1.8V. 3.3V and 1.8V vcc are capable of doing DDR. vccq of 1.8v is not required. Signed-off-by: Philip Rakity <[email protected]> Reviewed-by: Arindam Nath <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: core: eMMC signal voltage does not use CMD11Philip Rakity3-5/+6
eMMC chips do not use CMD11 when changing voltage. Add extra argument to call to indicate if CMD11 needs to be sent. Signed-off-by: Philip Rakity <[email protected]> Reviewed-by: Arindam Nath <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci-pxa: add platform code for UHS signalingPhilip Rakity1-0/+41
Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: Philip Rakity <[email protected]> Reviewed-by: Arindam Nath <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci: add hooks for setting UHS in platform specific codePhilip Rakity2-15/+20
Allow platform specific code to set UHS registers if implementation requires speciial platform specific handling Signed-off-by: Philip Rakity <[email protected]> Reviewed-by: Arindam Nath <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: core: clear MMC_PM_KEEP_POWER flag on resumeEliad Peller1-0/+1
Since the MMC_PM_KEEP_POWER flag should be set on each suspend, it should also cleared on each resume. Upon resuming, we have to know if power was kept (for re-initialization, etc.), so clear it just after resuming. Signed-off-by: Eliad Peller <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: dw_mmc: fixed wrong regulator_enable in suspend/resumeJaehoon Chung1-3/+3
regulator_enable() was incorrectly placed in the suspend function instead of the resume function. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Acked-by: Will Newton <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhi: allow powering down controller with no card insertedGuennadi Liakhovetski2-0/+10
Supply a link to TMIO private data for platforms to implement their own card detection. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: tmio: runtime suspend the controller, where possibleGuennadi Liakhovetski3-6/+78
The TMIO MMC controller cannot be powered off to save power, when no card is plugged in, because then it will not be able to detect a new card-insertion event. On some implementations, however, it is possible to switch to using another source to detect card insertion. This patch adds support for such implementations. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhi: support up to 3 interrupt sourcesMagnus Damm1-11/+28
Convert the SDHI code to support more than a single interrupt source. Needed to support hardware that uses GIC instead of INTC as interrupt controller. Will also allow us to remove the irq forwarding workaround from the INTC code in the future. Signed-off-by: Simon Horman <[email protected]> Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhi: print physical base address and clock rateMagnus Damm1-2/+4
Instead of printing out useless information such as the virtual base address and one of 4 interrupts, convert the SDHI probe() to print out physical base address together with clock rate. We do have a struct device so make use of dev_info(). Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhi: no need for special interrupt flagsMagnus Damm1-2/+1
Modify the SDHI driver to get rid of unwanted irq flags. IRQF_DISABLED unused, see include/linux/interrupt.h IRQF_TRIGGER_FALLING only relevant on external IRQ pins, but since SDHI is internal in the SoC this can go away. Needed to support SDHI on sh73a0 that comes with a GIC that errors out with the IRQF_TRIGGER_FALLING setting. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: tmio/sdhi: break out interrupt request/freeMagnus Damm4-21/+37
Move request_irq()/free_irq() from the shared code in tmio_mmc.c into the SDHI/tmio specific portion in sh_mobile_sdhi.c and tmio_mmc_pio.c. This is ground work to allow us to adjust the SDHI code with IRQ flags and number of interupt sources. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: protect the tmio_mmc driver against a theoretical raceGuennadi Liakhovetski2-6/+57
The MMC subsystem does not guarantee, that host driver .request() and .set_ios() callbacks are serialised. Such concurrent calls, however, do not have to be meaningfully supported, drivers just have to make sure to avoid any severe problems. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: add runtime and system power-management support to the MMCIF driverGuennadi Liakhovetski1-9/+69
Adding support for runtime power-management to the MMCIF driver allows it to save power as long as no card is present. To also allow to turn off the power domain at that time, we release DMA channels during that time, since on some sh-mobile systems the DMA controller(s) and the MMCIF block belong to the same power domain. System-wide power management has been tested with experimental PM patches on AP4-based systems. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: Add runtime and system-wide PM to the TMIO MMC driverGuennadi Liakhovetski5-19/+86
Add runtime and system-wide power management to the TMIO MMC driver in PIO and DMA modes, allowing it to properly save and restore its state during system suspend. Runtime PM is very crude ATM, because the controller has to be powered on all the time to detect card hotplug events. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sh_mmcif: protect against a theoretical raceGuennadi Liakhovetski1-8/+42
The MMC subsystem does not guarantee that host driver .request() and .set_ios() callbacks are serialised. Such concurrent calls, however, do not have to be meaningfully supported, drivers just have to make sure to avoid any severe problems. Signed-off-by: Guennadi Liakhovetski <[email protected]> Cc: Simon Horman <[email protected]> Cc: Magnus Damm <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdio: optimized SDIO IRQ handling for single irqStefan Nilsson XK2-1/+33
If there is only 1 function interrupt registered it is possible to improve performance by directly calling the irq handler and avoiding the overhead of reading the CCCR registers. Signed-off-by: Per Forlin <[email protected]> Acked-by: Ulf Hansson <[email protected]> Reviewed-by: Nicolas Pitre <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: mmc_test: minor clean up, use t = &test.area everywhereAndy Shevchenko1-31/+44
Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: card: fix potential null dereference of 'idata'Vladimir Motyka1-5/+6
When allocation of idata failed there was a null dereference. Also avoid calling kfree where it isn't needed. Signed-off-by: Vladimir Motyka <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci: add support for retuning mode 1Arindam Nath3-3/+118
Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci: add support for programmable clock modeArindam Nath3-15/+70
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci: enable preset value after uhs initializationArindam Nath3-0/+44
According to the Host Controller spec v3.00, setting Preset Value Enable in the Host Control2 register lets SDCLK Frequency Select, Clock Generator Select and Driver Strength Select to be set automatically by the Host Controller based on the UHS-I mode set. This patch enables this feature. Since Preset Value Enable makes sense only for UHS-I cards, we enable this feature after successfull UHS-I initialization. We also reset Preset Value Enable next time before initialization. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: add support for tuning during uhs initializationArindam Nath6-1/+182
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: report correct speed and capacity of uhs cardsArindam Nath3-4/+24
Since only UHS-I cards respond with S18A set in response to ACMD41, we set the card as ultra-high-speed after successfull initialization. We need to decide whether a card is SDXC based on the C_SIZE field of CSDv2.0 register. According to Physical Layer spec v3.01, the minimum value of C_SIZE for SDXC card is 00FFFFh. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: set current limit for uhs cardsArindam Nath4-0/+86
We decide on the current limit to be set for the card based on the Capability of Host Controller to provide current at 1.8V signalling, and the maximum current limit of the card as indicated by CMD6 mode 0. We then set the current limit for the card using CMD6 mode 1. As per the Physical Layer Spec v3.01, the current limit switch is only applicable for SDR50, SDR104, and DDR50 bus speed modes. For other UHS-I modes, we set the default current limit of 200mA. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: add support for uhs bus speed mode selectionArindam Nath5-3/+132
This patch adds support for setting UHS-I bus speed mode during UHS-I initialization procedure. Since both the host and card can support more than one bus speed, we select the highest speed based on both of their capabilities. First we set the bus speed mode for the card using CMD6 mode 1, and then we program the host controller to support the required speed mode. We also set High Speed Enable in case one of the UHS-I modes is selected. We take care to reset SD clock before setting UHS mode in the Host Control2 register, and then re-enable it as per the Host Controller spec v3.00. We then set the clock frequency for the UHS-I mode selected. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sdhci: reset sdclk before setting high speed enableArindam Nath1-3/+24
As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: add support for driver type selectionArindam Nath9-30/+190
This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-25ARM: arch-shmobile: sh7372: add renesas_usbhs irq supportKuninori Morimoto1-0/+2
renesas_usbhs is remake version of r8a66597 Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25sh_mobile_meram: Safely disable MERAM operation when not initializedDamian1-1/+2
If the MERAM platform data is defined, but the MERAM has not been properly initaliazed we need to safely fall back to non-MERAM operation. Signed-off-by: Damian Hobson-Garcia <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: sh73a0: mark DMA slave ID 0 as invalidMagnus Damm1-0/+1
This makes it possible to leave DMA slave IDs in the platform data at default 0 value without hitting DMA channel allocation error paths. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: mark DMA slave ID 0 as invalidGuennadi Liakhovetski1-0/+1
This makes it possible to leave DMA slave IDs in the platform data at default 0 value without hitting DMA channel allocation error paths. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: Enable DMAEngine for SDHI on AG5EVMMagnus Damm1-0/+4
Add SDHI0 and SDHI1 slave ids for RX and TX to enable DMA Engine support for SDHI on the AG5EVM board. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: Enable DMAEngine for MMCIF on AG5EVMMagnus Damm1-0/+9
Simply add MMCIF slave ids for RX and TX to enable DMA Engine support for the AG5EVM board. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: sh73a0 DMA Engine support for SY-DMACMagnus Damm3-1/+277
Add SY-DMAC support via shdma.c to the sh73a0 SoC including slave ids, platform data and clock bindings. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25dmaengine: shdma: Update SH_DMAC_MAX_CHANNELS to 20Magnus Damm1-1/+1
Update SH_DMAC_MAX_CHANNELS to support the 20 DMA channels included in the sh73a0 SY-DMAC hardware. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25dmaengine: shdma: Fix SH_DMAC_MAX_CHANNELS handlingMagnus Damm1-8/+23
Fix the shdma.c handing of SH_DMAC_MAX_CHANNELS to avoid overwriting the chan_irq[] and chan_flag[] arrays in the case of pdata->channel_num is larger than SH_DMAC_MAX_CHANNELS. With this patch applied up to SH_DMAC_MAX_CHANNELS will be used by the shdma.c driver. If more channels are available in the platform data the user will be notified on the console. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25dmaengine: shdma: Make second memory window optionalMagnus Damm1-3/+8
This patch makes the shdma.c driver allow slave operation on DMA hardware mapped with a single I/O-memory window. The dmae_set_dmars() function is adjusted to use the first memory window in case of a missing DMARS window. At probe() time the code is updated to enable DMA_SLAVE only if slave information is passed with the platform data. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: Tidy up after SH7372 pm changes.Paul Mundt1-1/+1
Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: sh7372 Core Standby CPUIdleMagnus Damm1-2/+31
This patch ties in the previously added sh7372 sleep mode known as Core Standby together with the shared SH-Mobile ARM CPUIdle implementation. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: CPUIdle supportMagnus Damm3-0/+96
This patch adds a shared SH-Mobile ARM specific CPUIdle implementation supporting WFI only at this point. It serves as a common point for late registration of the arch-specific CPUIdle code, and supports adding extra sleep modes using the callback shmobile_cpuidle_setup() together with shmobile_cpuidle_modes[]. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: sh7372 Core Standby Suspend-to-RAMMagnus Damm6-0/+345
Add sh7372 Core Standby sleep mode support and tie it in with the shared SH-Mobile ARM suspend code. The Core Standby mode is the lightest sh7372-specific sleep mode, cutting power to the ARM core excluding the L2 cache. Any interrupt source can be used for wakeups. The low level portion of this code is based on the TI OMAP sleep code in sleep34xx.S, thanks to them. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25ARM: mach-shmobile: Suspend-to-RAM supportMagnus Damm3-0/+51
This patch adds a simple Suspend-to-RAM implementation for SH-Mobile ARM. The struct shmobile_suspend_ops are kept global to allow cpu-specific code to override the callbacks if needed. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
2011-05-25Merge branch 'mb862xxfb-for-next' of git://git.denx.de/linux-2.6-agustPaul Mundt6-12/+425
2011-05-24mmc: sd: query function modes for uhs cardsArindam Nath2-10/+62
SD cards which conform to Physical Layer Spec v3.01 can support additional Bus Speed Modes, Driver Strength, and Current Limit other than the default values. We use CMD6 mode 0 to read these additional card functions. The values read here will be used during UHS-I initialization steps. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
2011-05-24mmc: sd: add support for signal voltage switch procedureArindam Nath7-17/+284
Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <[email protected]> Reviewed-by: Philip Rakity <[email protected]> Tested-by: Philip Rakity <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Signed-off-by: Chris Ball <[email protected]>
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