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2018-07-09drm/i915/gvt: Make PTE iterator 64K entry awareChangbin Du1-2/+6
64K PTE is special, only PTE#0, PTE#16, PTE#32, ... PTE#496 are used in the page table. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Split ppgtt_alloc_spt into two partsChangbin Du1-22/+40
We need a interface to allocate a pure shadow page which doesn't have a guest page associated with. Such shadow page is used to shadow 2M huge gtt entry. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Add GTT clear_pse operationChangbin Du2-0/+20
Add clear_pse operation in case we need to split huge gtt into small pages. v2: correct description. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Add software PTE flag to mark special 64K splited entryChangbin Du2-0/+24
This add a software PTE flag on the Ignored bit of PTE. It will be used to identify splited 64K shadow entries. v2: fix mask definition. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDEChangbin Du2-21/+51
This change help us detect the real entry type per PSE and IPS setting. For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA. v2: Extend IPS mmio control to Gen10. (Matthew Auld) Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTTChangbin Du1-1/+28
The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA from GEN8 which can control IPS enabling. v3: MMIO control for IPS is not removed from gen9 but gen10 (Matthew Auld) v2: IPS of all engines must be enabled together for gen9. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Add PTE IPS bit operationsChangbin Du2-0/+20
Add three IPS operation functions to test/set/clear IPS in PDE. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-07-09drm/i915/gvt: Add new 64K entry typeChangbin Du2-4/+23
Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very different from 2M/1G entry. 64K entry is controlled by IPS bit in upper PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE level. Which means, 64K entries can also processed by get_pse_type(). v2: Make it bisectable. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915: Enable KVMGT for BXT.Colin Xu1-0/+2
Enable KVMGT for BXT. is_supported_device() acting as the gatekeeper of GVT-g init. If all supported platforms share the same configurations for some specific feature, platform check will rely on this check only. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Add mmio handler for for BXT.Colin Xu1-45/+344
Leverage most SKL/KBL mmio init info and add different mmio to BXT specific function init_bxt_mmio_info(). Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable dma_buf support for BXT.Colin Xu2-4/+12
Handle dma_buf on BXT as SKL and KBL. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable virtual display support for BXT.Colin Xu2-1/+42
Virtual monitor on BXT start from port B. Unlike SKL/KBL, digital display port connectivity is detected via GEN8_DE_PORT_ISR so emulate monitor state change by setting it. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable force wake support for BXT.Colin Xu1-2/+4
BXT forcewake is handled in the same way as SKL/KBL. v2: Add missing inhibit_context restore for BXT. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable cmd_parser support for BXT.Colin Xu1-25/+14
Handle BXT cmd_parser as SKL/KBL. v2: All supported platforms share the same routines. Remove the platform check by now and let is_supported_device() be the gate keeper. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable mmio context init and switch for BXT.Colin Xu1-5/+11
Handle pending tlb flush, mocs/mmio switch and context as KBL. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable irq initialization for BXT.Colin Xu1-9/+5
Initialize BXT irq handler as SKL/KBL. v2: All supported platforms share the same irq ops and map. Remove the platform check by now and let is_supported_device() be the gate keeper. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable gtt initialization for BXT.Colin Xu1-7/+2
Initialize BXT gtt as SKL/KBL. v2: All supported platforms share the same gtt ops. Remove the platform check by now and let is_supported_device() be the gate keeper. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Enable device info initialization for BXT.Colin Xu1-12/+9
Initialize BXT device info as SKL/KBL. v2: All supported platforms share the same device configuration. Remove the platform check by now and let is_supported_device() be the gate keeper. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Add MEDIA_POOL_STATE for BXT.Colin Xu1-0/+4
As referred in PRM for Broxton Graphics on 01.org Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-13drm/i915/gvt: Add D_BXT device type define for BXT.Colin Xu2-5/+8
Broxton belongs to GEN9 family so add to SKL and GEN9 plus. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-11drm/i915/gvt: use array to avoid potential buffer overflowXinyun Liu2-11/+7
Array 'pdp_pair' of size 1 may use index value(s) 1..7. Changed to pdps[8] to avoid confusion. Signed-off-by: Xinyun Liu <xinyun.liu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-11drm/i915/gvt: removed unnecessary boundary checkXinyun Liu1-1/+1
type is already checked in the function entry. So it is unnecessary to check it again. Signed-off-by: Xinyun Liu <xinyun.liu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-11drm/i915/gvt: Avoid dereference a potential null pointerXinyun Liu1-1/+2
Add sanity check for up_irq_info. Signed-off-by: Xinyun Liu <xinyun.liu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-07Merge tag 'drm-intel-next-2018-06-06' into gvt-nextZhenyu Wang87-2315/+3239
Backmerge for recent request->hw_context change and new vGPU huge page capability definition. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-06-06drm/i915: Update DRIVER_DATE to 20180606Rodrigo Vivi1-2/+2
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-06-06drm/i915/gtt: Fix typo in fill_px() macroChris Wilson1-2/+2
The macro declared the ppgtt parameter but implicitly used the local vm instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180606205128.25952-1-chris@chris-wilson.co.uk
2018-06-06drm/i915: Mark i915.inject_load_failure as being hitChris Wilson1-5/+5
When we reach the magic value and do inject a fault into our module load, mark the module option as being hit. Since we fail from inside pci probe, the module load isn't actually aborted and the module (and parameters) are left lingering. igt can then inspect the parameter on its synchronous completion of modprobe to see if the fault injection was successful, and will keeping on injecting new faults until the module succeeds in loading having surpassed the number of fault points. v2: Reset to 0 after being hit; Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180606144153.4244-1-chris@chris-wilson.co.uk
2018-06-05drm/i915/gtt: Rename i915_hw_ppgtt base memberChris Wilson32-390/+390
In the near future, I want to subclass gen6_hw_ppgtt as it contains a few specialised members and I wish to add more. To avoid the ugliness of using ppgtt->base.base, rename the i915_hw_ppgtt base member (i915_address_space) as vm, which is our common shorthand for an i915_address_space local. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180605153758.18422-1-chris@chris-wilson.co.uk
2018-06-05drm/i915/error: Fixup inactive/active countingChris Wilson1-2/+2
The inactive counter was over the active list, and vice versa. Fortuitously this should not cause a problem in practice as they shared the same array and clamped the number of entries they would write. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180605160623.30163-1-chris@chris-wilson.co.uk
2018-06-05drm/i915/guc: Don't leak stage descriptor pool on init failureMichal Wajdeczko1-1/+4
In case of failure during GuC clients creation, we forget to cleanup earlier pool allocation. Use proper teardown to fix that. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiarski@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180605120547.16468-1-michal.wajdeczko@intel.com
2018-06-05drm/i915/pmu: Do not assume fixed hrtimer periodTvrtko Ursulin2-20/+55
As Chris has discovered on his Ivybridge, and later automated test runs have confirmed, on most of our platforms hrtimer faced with heavy GPU load can occasionally become sufficiently imprecise to affect PMU sampling calculations. This means we cannot assume sampling frequency is what we asked for, but we need to measure the interval ourselves. This patch is similar to Chris' original proposal for per-engine counters, but instead of introducing a new set to work around the problem with frequency sampling, it swaps around the way internal frequency accounting is done. Instead of accumulating current frequency and dividing by sampling frequency on readout, it accumulates frequency scaled by each period. v2: * Typo in commit message, comment on period calculation and USEC_PER_SEC. (Chris Wilson) Testcase: igt/perf_pmu/*busy* # snb, ivb, hsw Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180605140253.3541-1-tvrtko.ursulin@linux.intel.com
2018-06-05drm/i915/trace: Context field needs to be 64-bit wideTvrtko Ursulin1-10/+10
Underlaying field is u64 so the tracepoint needs to be as well. v2: * Re-order binary packet for 64-bit alignment. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180605134124.25672-1-tvrtko.ursulin@linux.intel.com
2018-06-05drm/i915/trace: Remove engine out of the context sandwichTvrtko Ursulin1-15/+15
In the string tracepoint representation we ended up with the engine sandwiched between context hardware id and context fence id. Move the two pieces of context data together for redability. Binary records are left as is, that is both fields remaing under the existing name and ordering. v2: * Do not consolidate the printk format, just reorder. (Lionel) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180525082642.18246-2-tvrtko.ursulin@linux.intel.com
2018-06-05drm/i915/trace: Describe engines as class:instance pairsTvrtko Ursulin1-42/+65
Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. This will be more readable, more future proof and more stable for userspace consumption. v2: * Use u16 for class and instance. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: svetlana.kukanova@intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180525082642.18246-1-tvrtko.ursulin@linux.intel.com
2018-06-05drm/i915: Swap magics and use SZ_1MChris Wilson1-1/+1
Since the kernel provides SZ_1M, use it in preference of 1 << 20. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180605135746.8020-1-chris@chris-wilson.co.uk
2018-06-05drm/i915: Correctly handle error path in i915_gem_init_hwMichal Wajdeczko1-0/+6
In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() v2: pulled out from the series Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180605122443.23776-1-michal.wajdeczko@intel.com
2018-06-05drm/i915/vma: Move the bind_count vs pin_count assertion to a helperChris Wilson1-2/+14
To spare ourselves a long line later, refactor the repeated check of bind_count vs pin_count to a helper. v2: Fix up the commentary! Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180605094107.31367-1-chris@chris-wilson.co.uk
2018-06-05drm/i915/gtt: Teach restore-gtt to walk the ggtt vma list not the object listChris Wilson1-13/+10
In preparation, for having non-vma objects stored inside the ggtt, to handle restoration of the GGTT following resume, we need to walk over the ggtt address space rebinding vma, as opposed to walking over bound objects looking for ggtt entries. v2: Skip objects only bound for the aliasing_ppgtt Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20180605082856.19221-1-chris@chris-wilson.co.uk
2018-06-05drm/i915/ringbuffer: Make context pin/unpin symmetricChris Wilson1-24/+43
Currently, we have a special routine for pinning the context state at the start of activity tracking, but lack the complementary unpin routine. Create it to to ease later patches that want to do partial teardown on error, and, not least, to improve the readability of the code. Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180605085348.3018-1-chris@chris-wilson.co.uk
2018-06-05drm/i915: Add new vGPU cap info bit VGT_CAPS_HUGE_GTTChangbin Du3-6/+9
This adds a new vGPU cap info bit VGT_CAPS_HUGE_GTT, which is to detect whether the host supports shadowing of huge gtt pages. If host does support it, remove the page sizes restriction for vGPU. Signed-off-by: Changbin Du <changbin.du@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525770425-5373-1-git-send-email-changbin.du@intel.com
2018-06-04drm/i915/icl: Don't update enabled dbuf slices struct until updated in hwMahesh Kumar1-1/+0
Do not update number of enabled dbuf slices in dev_priv struct until we actually enable/disable dbuf slice in hw. This is leading to never updating dbuf slices and resulting in DBuf slice mismatch warning. Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed") Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180517132626.5885-1-mahesh1.kumar@intel.com
2018-06-04drm/i915/perf: fix ctx_id read with GuC & ICLLionel Landwerlin3-32/+97
One thing we didn't really understand about the OA report is that the ContextID field (dword 2) is copy of the context descriptor (dword 1). On Gen8->10 and without using GuC we didn't notice the issue because we only checked the 21bits of the ContextID field in the OA reports which matches exactly the hw_id stored into the context descriptor. When using GuC submission we have an issue of a non matching hw_id because GuC uses bit 20 of the hw_id to signal proxy submission. This change introduces a mask to compare only the relevant bits. On ICL the context descriptor format has changed and we failed to address this. On top of using a mask we also need to shift the bits properly. v2: Reuse lrc_desc rather than recomputing part of it (Chris/Michel) v3: Always pin the context we're filtering with (Chris) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252 BSpec: 1237 Testcase: igt/perf/gen8-unprivileged-single-ctx-counters Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180602112946.30803-3-lionel.g.landwerlin@intel.com Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org
2018-06-04drm/i915: drop one bit on the hw_id when using gucLionel Landwerlin3-4/+14
We currently using GuC as a proxy to the hardware. When Guc is used in such mode, it consumes the bit 20 of the hw_id to indicate that the workload was submitted by proxy. So far we probably haven't seen the issue because we need to allocate 1048576+ contexts to hit this issue. Still, we should avoid allocating the hw_id on that bit and restriction to bits [0:19] (i.e 20bits instead of 21). v2: Leave the max hw_id computation in i915_gem_context.c (Michel) v3: Be consistent on if/else usage (Chris) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> BSpec: 1237 Reviewed-by: Michel Thierry <michel.thierry@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180602112946.30803-2-lionel.g.landwerlin@intel.com
2018-06-04drm/i915/gtt: Remove obsolete switch_mm hooks for gen8+Chris Wilson1-49/+0
As the ppgtt for execlists is tightly coupled to the executing context, and not switch separately, we no longer use the ppgtt->switch_mm hooks on gen8+. Remove them. References: 79e6770cb1f5 ("drm/i915: Remove obsolete ringbuffer emission for gen8+") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180604131552.29370-1-chris@chris-wilson.co.uk
2018-06-04drm/i915: Move i915_gem_fini to i915_gem.cMichal Wajdeczko3-22/+23
We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. v2: rebased, pulled out from the series Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180604090032.20840-1-michal.wajdeczko@intel.com
2018-06-01drm/i915/icl: Calculate link clock using the new registersArkadiusz Hiler1-2/+7
Start using the new registers for ICL and on. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare4-0/+101
PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. This gets a little tricky for ICL since there is no register bit that maps directly to the link clock. So this patch creates a separate function in intel_dpll_mgr.c to obtain the write array PLL Params and compares the set pll_params with the table to get the corresponding link clock. v2: - Fix the encoder type check (DK). - Improve our error checking, return a sane value (Mika, Paulo). - Fix table entries (Paulo). Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> [Paulo: implement v2] Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180523224444.19017-1-paulo.r.zanoni@intel.com
2018-06-01drm/i915/icl: Add Icelake PCH detectionAnusha Srivatsa1-0/+2
This patch adds the support to detect PCH_ICP. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-10-paulo.r.zanoni@intel.com
2018-06-01drm/i915/icl: Map VBT DDC Pin to BSpec DDC PinRadhakrishna Sripada2-8/+33
On ICL we need to map VBT DDC Pin to BSpec DDC Pin. Adding ICL Pin Values. According to VBT Block 2 (General Bytes Definition) DDC Bus +----------+-----------+--------------------+ | DDI Type | VBT Value | BSpec Mapped Value | +----------+-----------+--------------------+ | DDI-A | 0x1 | 0x1 | | DDI-B | 0x2 | 0x2 | | PORT-1 | 0x4 | 0x9 | | PORT-2 | 0x5 | 0xA | | PORT-3 | 0x6 | 0xB | | PORT-4 | 0x7 | 0xC | +----------+-----------+--------------------+ Cc: James Ausmus <james.ausmus@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Paulo: checkpatch fixes.] Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-9-paulo.r.zanoni@intel.com
2018-06-01drm/i915/icl: Add register definition for DFLEXDPMLEManasi Navare1-0/+5
DFLEXDPMLE register is required to tell the FIA hardware which main links of DP are enabled on TCC Connectors. FIA uses this information to program PHY to Controller signal mapping. This register is applicable in both TC connector's Alternate mode as well as DP connector mode. v2: * Remove _ICL prefix since the reg is first introduced in ICL (Paulo) * s/ICL/icl in commit message (Lucas) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1527275032-4555-1-git-send-email-manasi.d.navare@intel.com
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