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2015-09-23drm/amdgpu: Sprinkle drm_modeset_lock_all to appease locking checksAlex Deucher1-0/+4
In commit 7a3f3d6667f5f9ffd1517f6b21d64bbf5312042c Author: Daniel Vetter <[email protected]> Date: Thu Jul 9 23:44:28 2015 +0200 drm: Check locking in drm_for_each_connector I added locking checks to drm_for_each_connector but failed that through drm_helper_connector_dpms -> drm_helper_choose_encoder_dpms it's used in a few more places in the amdgpu resume/suspend code. Fix them up. Note that we could use the connector iterator macros in there too, but that's for the future. Port of radeon commit: drm/radeon: Sprinkle drm_modeset_lock_all to appease locking checks Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/radeon: Sprinkle drm_modeset_lock_all to appease locking checksDaniel Vetter1-0/+4
In commit 7a3f3d6667f5f9ffd1517f6b21d64bbf5312042c Author: Daniel Vetter <[email protected]> Date: Thu Jul 9 23:44:28 2015 +0200 drm: Check locking in drm_for_each_connector I added locking checks to drm_for_each_connector but failed that through drm_helper_connector_dpms -> drm_helper_choose_encoder_dpms it's used in a few more places in the radeon resume/suspend code. Fix them up. Note that we could use the connector iterator macros in there too, but that's for the future. Reported-and-tested-by: Borislav Petkov <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: sync ce and me with SWITCH_BUFFER(2)monk.liu3-92/+23
we used to adopt wait_reg_mem to let CE wait before DE finish page updating, but from Tonga+, CE doesn't support wait_reg_mem package so this logic no longer works. so here is another approach to do same thing: Insert two of SWITCH_BUFFER at both front and end of vm_flush can guarantee that CE not go further to process IB_const before vm_flush done. Insert two of SWITCH_BUFFER also works on CI, so remove legency method to sync CE and ME v2: Insert double SWITCH_BUFFER at front of vm flush as well. Signed-off-by: monk.liu <[email protected]> Reviewed-by: Christian König <[email protected]>
2015-09-23drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()Dan Carpenter1-1/+1
args->size is a u64. arg->pitch and args->height are u32. The multiplication will overflow instead of using the high 32 bits as intended. Reviewed-by: Christian König <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: info leak in amdgpu_gem_metadata_ioctl()Dan Carpenter1-0/+5
There is no limit on args->data.data_size_bytes so we could read beyond the end of the args->data.data[] array. Reviewed-by: Christian König <[email protected]> Reported-by: Ilja Van Sprundel <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: integer overflow in amdgpu_info_ioctl()Dan Carpenter1-2/+3
The "alloc_size" calculation can overflow leading to memory corruption. Reviewed-by: Christian König <[email protected]> Reported-by: Ilja Van Sprundel <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: unwind properly in amdgpu_cs_parser_init()Dan Carpenter1-34/+51
The amdgpu_cs_parser_init() function doesn't clean up after itself but instead the caller uses a free everything function amdgpu_cs_parser_fini() on failure. This style of error handling is often buggy. In this example, we call "drm_free_large(parser->chunks[i].kdata);" when it is an unintialized pointer or when "parser->chunks" is NULL. I fixed this bug by adding unwind code so that it frees everything that it allocates. I also mode some other very minor changes: 1) Renamed "r" to "ret". 2) Moved the chunk_array allocation to the start of the function. 3) Removed some initializers which are no longer needed. Reviewed-by: Christian König <[email protected]> Reported-by: Ilja Van Sprundel <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: Fix max_vblank_count value for current display enginesAlex Deucher1-1/+1
The value was much too low, which could cause the userspace visible vblank counter to move backwards when the hardware counter wrapped around. Ported from radeon commit: b0b9bb4dd51f396dcf843831905f729e74b0c8c0 Reviewed-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: use kmemdup rather than duplicating its implementationAndrzej Hajda1-3/+1
The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320 Signed-off-by: Andrzej Hajda <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: fix UVD suspend and resume for VI APULeo Liu1-8/+12
User space passed the same handle before suspend and after resume, so we have remove the session and handle destroy, and keep the firmware untouched. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: fix the UVD suspend sequence orderLeo Liu3-6/+6
Fixes suspend issues with UVD. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: make UVD handle checking more strictLeo Liu1-27/+41
Invalid messages can crash the hw otherwise Ported from radeon commit a1b403da70e038ca6c6c6fe434d1d873546873a3 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: Disable UVD PGLeo Liu1-1/+2
This causes problems with multiple suspend/resume cycles. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: more scheduler cleanups v2Christian König11-76/+87
Embed the scheduler into the ring structure instead of allocating it. Use the ring name directly instead of the id. v2: rebased, whitespace cleanup Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Chunming Zhou<[email protected]>
2015-09-23drm/amdgpu: cleanup fence queue init v2Christian König2-2/+2
Move the fence related stuff into amdgpu_fence.c v2: rework commit message, cause this is actually not a bug Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou<[email protected]> Reviewed-by: Junwei Zhang <[email protected]>
2015-09-23drm/amdgpu: rename fence->scheduler to sched v2Christian König10-22/+22
Just to be consistent with the other members. v2: rename the ring member as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> (v1) Reviewed-by: Chunming Zhou<[email protected]>
2015-09-23drm/amdgpu: cleanup entity initChristian König3-19/+25
Reorder the fields and properly return the kfifo_alloc error code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Chunming Zhou<[email protected]>
2015-09-23drm/amdgpu: refine the scheduler job type conversionJunwei Zhang3-4/+6
Use container_of rather than casting. Reviewed-by: Christian König <[email protected]> Reviewed-by: David Zhou <[email protected]> Signed-off-by: Junwei Zhang <[email protected]>
2015-09-23drm/amdgpu: refine the job naming for amdgpu_job and amdgpu_sched_jobJunwei Zhang8-69/+71
Use consistent naming across functions. Reviewed-by: Christian König <[email protected]> Reviewed-by: David Zhou <[email protected]> Signed-off-by: Junwei Zhang <[email protected]>
2015-09-23drm/amdgpu: use only one reservation object for each VM v2Christian König2-30/+9
Reduces the locking and fencing overhead. v2: add comment why we need the duplicates list in the GEM op. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-09-23drm/amdgpu: validate duplicates in the CS as wellChristian König1-14/+20
This allows for multiple BOs to have the same reservation object. Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: export reservation_object from dmabuf to ttm (v2)Christian König24-52/+70
Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c. Port of radeon commit 831b6966a60fe72d85ae3576056b4e4e0775b112. v2: fix up kfd. Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: fix overflow on 32bit systemsChristian König1-1/+1
mem->start is a long, so this can overflow on 32bit systems. Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: remove process_job callback from the schedulerChristian König3-24/+7
Just free the resources immediately after submitting the job. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-09-23drm/amdgpu: move scheduler fence callback into fence v2Christian König2-11/+12
And call the processed callback directly after submitting the job. v2: split adding error handling into separate patch. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-09-23drm/amdgpu: signal scheduler fence when hw submission fails v3Christian König1-0/+3
Otherwise the resource blocked by it will never be reclaimed. v2: add DRM_ERROR. v3: fix typo in commit message Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Chunming Zhou<[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-09-23drm/amdgpu: add tracepoint for scheduler (v2)Chunming Zhou2-1/+45
track sched job status like the length of job queue and hw job queue. v2: fix build after rebase Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Christian König <[email protected]>
2015-09-23drm/amdgpu: use write confirm for vm_flush()Christian König1-1/+2
Make sure the CP waits for the write to be confirmed before invalidating. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: execution barrier after fence v2Anatoli Antonovitch1-0/+12
Insert wait for reg mem after EOP to fix potential issue with vm context switch v2: move wait to vm_flush() use equal instead of greater than. Signed-off-by: Anatoli Antonovitch <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-23drm/amdgpu: add option to disable semaphoresChristian König3-1/+21
Provide module parameter to enable/disable them. Still enabled by default. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-11Merge branch 'linux-4.3' of ↵Dave Airlie3-4/+5
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next three nouveau regression fixes. * 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/device: enable c800 quirk for tecra w50 drm/nouveau/clk/gt215: Unbreak engine pausing for GT21x/MCP7x drm/nouveau/gr/nv04: fix big endian setting on gr context
2015-09-11drm/nouveau/device: enable c800 quirk for tecra w50Ben Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]>
2015-09-11drm/nouveau/clk/gt215: Unbreak engine pausing for GT21x/MCP7xRoy Spliet1-1/+1
Typo that snuck in with commit 6979c6303a4abf263753cd9d577d79f05c6e8c47 Signed-off-by: Roy Spliet <[email protected]> Reported-by: Pierre Moreau <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2015-09-11drm/nouveau/gr/nv04: fix big endian setting on gr contextIlia Mirkin1-3/+3
Broken since "gr: convert user classes to new-style nvkm_object" Tested on a PPC64 G5 + NV34 Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2015-09-11Merge tag 'topic/drm-fixes-2015-09-09' of ↵Dave Airlie2-21/+117
git://anongit.freedesktop.org/drm-intel into drm-next bunch of drm fixes. * tag 'topic/drm-fixes-2015-09-09' of git://anongit.freedesktop.org/drm-intel: drm/dp: Add dp_aux_i2c_speed_khz module param to set the assume i2c bus speed drm/dp: Adjust i2c-over-aux retry count based on message size and i2c bus speed drm/dp: Define AUX_RETRY_INTERVAL as 500 us drm/atomic: Fix bookkeeping with TEST_ONLY, v3.
2015-09-11Merge tag 'drm-intel-next-fixes-2015-09-10' of ↵Dave Airlie9-32/+54
git://anongit.freedesktop.org/drm-intel into drm-next Fixes headed for v4.3-rc1, including Maarten's DP MST state checker fix you requested. * tag 'drm-intel-next-fixes-2015-09-10' of git://anongit.freedesktop.org/drm-intel: drm/i915: Allow DSI dual link to be configured on any pipe drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOS drm/i915: Fix CSR MMIO address check drm/i915: Limit the number of loops for reading a split 64bit register drm/i915: Fix broken mst get_hw_state. drm/i915: Pass hpd_status_i915[] to intel_get_hpd_pins() in pre-g4x uapi/drm/i915_drm.h: fix userspace compilation. drm/i915: Always mark the object as dirty when used by the GPU
2015-09-11drm/qxl: validate monitors config modesJonathon Jongsma2-26/+42
Due to some recent changes in drm_helper_probe_single_connector_modes_merge_bits(), old custom modes were not being pruned properly. In current kernels, drm_mode_validate_basic() is called to sanity-check each mode in the list. If the sanity-check passes, the mode's status gets set to to MODE_OK. In older kernels this check was not done, so old custom modes would still have a status of MODE_UNVERIFIED at this point, and would therefore be pruned later in the function. As a result of this new behavior, the list of modes for a device always includes every custom mode ever configured for the device, with the largest one listed first. Since desktop environments usually choose the first preferred mode when a hotplug event is emitted, this had the result of making it very difficult for the user to reduce the size of the display. The qxl driver did implement the mode_valid connector function, but it was empty. In order to restore the old behavior where old custom modes are pruned, we implement a proper mode_valid function for the qxl driver. This function now checks each mode against the last configured custom mode and the list of standard modes. If the mode doesn't match any of these, its status is set to MODE_BAD so that it will be pruned as expected. Signed-off-by: Jonathon Jongsma <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
2015-09-10drm/i915: Allow DSI dual link to be configured on any pipeGaurav K Singh1-5/+4
Just like single link MIPI panels, similarly for dual link panels, pipe to be configured is based on the DVO port from VBT Block 2. In hardware, Port A is mapped with Pipe A and Port C is mapped with Pipe B. This issue got introduced in - commit 7e9804fdcffc650515c60f524b8b2076ee59e710 Author: Jani Nikula <[email protected]> Date: Fri Jan 16 14:27:23 2015 +0200 drm/i915/dsi: add drm mipi dsi host support Cc: [email protected] # v4.0 Signed-off-by: Gaurav K Singh <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]>
2015-09-10drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOSVille Syrjälä2-13/+31
If one disables DDR DVFS in the BIOS, Punit will apparently ignores all DDR DVFS request. Currently we assume that DDR DVFS is always operational, which leads to errors in dmesg when the DDR DVFS requests time out. Fix the problem by gently prodding Punit during driver load to find out whether it will respond to DDR DVFS requests. If the request times out, we assume that DDR DVFS has been permanenly disabled in the BIOS and no longer perster the Punit about it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91629 Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Tested-by: Clint Taylor <[email protected]> Signed-off-by: Jani Nikula <[email protected]>
2015-09-10drm/i915: Fix CSR MMIO address checkTakashi Iwai1-1/+1
Fix a wrong logical AND (&&) used for the range check of CSR MMIO. Spotted nicely by gcc -Wlogical-op flag: drivers/gpu/drm/i915/intel_csr.c: In function ‘finish_csr_load’: drivers/gpu/drm/i915/intel_csr.c:353:41: warning: logical ‘and’ of mutually exclusive tests is always false [-Wlogical-op] Fixes: eb805623d8b1 ('drm/i915/skl: Add support to load SKL CSR firmware.') Cc: <[email protected]> # v4.2 Signed-off-by: Takashi Iwai <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Signed-off-by: Jani Nikula <[email protected]>
2015-09-09drm/i915: Limit the number of loops for reading a split 64bit registerChris Wilson1-5/+5
In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit reads. Due to the nature of the registers we try to read in this manner, they may increment between the two instruction (e.g. a timestamp counter). To keep the result accurate, we repeat the read if we detect an overflow (i.e. the upper value varies). However, some hardware is just plain flaky and may endless loop as the the upper 32bits are not stable. Just give up after a couple of tries and report whatever we read last. v2: Use the most recent values when erring out on an unstable register. Reported-by: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906 Signed-off-by: Chris Wilson <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jani Nikula <[email protected]> Cc: [email protected] Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Jani Nikula <[email protected]>
2015-09-08drm/i915: Fix broken mst get_hw_state.Maarten Lankhorst2-5/+10
connector->encoder is initialized as NULL. Fix this by setting it in during pre enable. MST connectors are not read out during initial hw readout, and have no fixed encoder mappings. So it's harmless to return false when the connector has never been assigned to an encoder. Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Ander Conselvan de Oliveira <[email protected]> Signed-off-by: Jani Nikula <[email protected]>
2015-09-05Merge branch 'drm-next-4.3' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie22-52/+127
into drm-next A few more fixes for amdgpu from the last few days: - Fix several copy paste typos - Resume from suspend fixes for VCE - Fix the GPU scheduler warning in kfifo_out - Re-enable GPUVM fault interrupts which were inadvertently disabled - GPUVM page table hang fix when paging * 'drm-next-4.3' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: rename gmc_v8_0_init_compute_vmid drm/amdgpu: fix vce3 instance handling drm/amdgpu: remove ib test for the second VCE Ring drm/amdgpu: properly enable VM fault interrupts drm/amdgpu: fix warning in scheduler drm/amdgpu: fix buffer placement under memory pressure drm/amdgpu/cz: fix cz_dpm_update_low_memory_pstate logic drm/amdgpu: fix typo in dce11 watermark setup drm/amdgpu: fix typo in dce10 watermark setup drm/amdgpu: use top down allocation for non-CPU accessible vram drm/amdgpu: be explicit about cpu vram access for driver BOs (v2)
2015-09-04drm/amdgpu: rename gmc_v8_0_init_compute_vmidAlex Deucher1-3/+3
It should be gfx_v8_0_init_compute_vmid since it's part of the gfx block. Acked-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-04drm/amdgpu: fix vce3 instance handlingAlex Deucher1-6/+42
Need to properly handle the instances for the idle checks and soft reset. Acked-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-04drm/amdgpu: remove ib test for the second VCE RingLeo Liu1-0/+4
it seems the VCE ring 1 ib test not reliable, remove it for now. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-and-Reviewed-by: Sonny Jiang <[email protected]>
2015-09-04drm/amdgpu: properly enable VM fault interruptsChristian König2-15/+18
This fixes not printing VM faults. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-09-04drm/amdgpu: fix warning in schedulerAlex Deucher1-2/+3
This should never happen so warn when the count does not equal the expected size. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-09-04Merge tag 'drm-intel-next-fixes-2015-09-02' of ↵Dave Airlie12-82/+147
git://anongit.freedesktop.org/drm-intel into drm-next i915 display fixes headed for v4.3. Mostly SKL, but some regression fixes too. * tag 'drm-intel-next-fixes-2015-09-02' of git://anongit.freedesktop.org/drm-intel: i915: Set ddi_pll_sel in DP MST path drm/i915: Don't use link_bw for PLL setup drm/i915: Preserve SSC earlier drm/i915/skl: Adding DDI_E power well domain drm/i915: eDP can be present on DDI-E drm/i915/skl: Enable DDI-E drm/i915: Enable HDMI on DDI-E drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 drm/i915: Check DP link status on long hpd too drm/i915: set CDCLK if DPLL0 enabled during resuming from S3
2015-09-04Merge branch 'drm-rockchip-2015-08-26' of ↵Dave Airlie2-9/+348
https://github.com/markyzq/kernel-drm-rockchip into drm-next Here are some fixes and some new features for rockchip drm, tested on popmetal rk3288 board, can you land them? * 'drm-rockchip-2015-08-26' of https://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: vop: support plane scale drm/rockchip: vop: restore vop registers when resume drm/rockchip: vop: Default enable win2/3 area0 bit drm/rockchip: vop: Add yuv plane support drm/rockchip: vop: Fix window dest start point drm/rockchip: vop: Fix virtual stride calculation
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