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2020-01-10drm/amd/display: Fix compilation warnings on i386Mikita Lipski1-2/+2
[why] Compilation error "undefined reference to `__udivdi3'" was thrown on i386 architecture. [how] Use div_u64 for unsigned long division instead of a divide operator. Reported-by: Randy Dunlap <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: fix documentation of drm_dp_mst_add_affected_dsc_crtcsAlex Deucher1-1/+1
the parameter is the mst manager, not the port. Reviewed-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amdgpu/display: protect new DSC code with CONFIG_DRM_AMD_DC_DCNAlex Deucher3-1/+17
Otherwise we get undefined symbols. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm: add dp helper to initialize remote aux channel.David (Dingchen) Zhang3-0/+17
[why] We need to minimally initialize the remote aux channel, e.g. the crc work struct of remote aux to dump the sink's DPRX CRCs in MST setup. [how] Add helper that only initializes the crc work struct of the remote aux, hooke crc work queue to 'drm_dp_aux_crc_work'. Then call this helper in DP MST port initialization. This, plus David Francis' patch [1], fix the issue of MST remote aux DPCD CRCs read. [1] https://patchwork.kernel.org/patch/11217941/ Cc: Leo Li <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: David (Dingchen) Zhang <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Trigger modesets on MST DSC connectorsMikita Lipski1-0/+33
Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing. Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset, for each crtc that shares a MST topology with that stream and supports DSC, add that crtc (and all affected connectors and planes) to the atomic state and set mode_changed on its state v2: Do this check only on Navi and before adding connectors and planes on modesetting crtcs v3: Call the drm_dp_mst_add_affected_dsc_crtcs() to update all affected CRTCs Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCsMikita Lipski2-0/+64
[why] Whenever a connector on an MST network is changed or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing. [how] Adding helper to trigger modesets on MST DSC connectors by setting mode_changed flag on CRTCs in the same topology as affected connector v2: use drm_dp_mst_dsc_aux_for_port function to verify if the port is DSC capable v3: - added _must_check attribute - removed topology manager check - fix typos and indentations Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Recalculate VCPI slots for new DSC connectorsMikita Lipski1-5/+71
[why] Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector. [how] The function iterates through all the active streams to find, which have DSC enabled, then recalculates PBN for it and calls drm_dp_helper_update_vcpi_slots_for_dsc to update connector's VCPI slots. v2: - use drm_dp_mst_atomic_enable_dsc per port to enable/disable DSC v3: - Iterate through connector states from the state passed - On each connector state get stream from dc_state, instead CRTC state Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Check return value of drm helperMikita Lipski1-45/+54
If driver fails to update update VCPI allocation during compute_mst_dsc_configs_for_state - fail the function by return early. Signed-off-by: Mikita Lipski <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: MST DSC compute fair shareDavid Francis5-2/+376
If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network Implement an algorithm to determine the correct DSC config for each stream The algorithm: This [ ] ( ) represents the range of bandwidths possible for a given stream. The [] area represents the range of DSC configs, and the () represents no DSC. The bandwidth used increases from left to right. First, try disabling DSC on all streams [ ] (|) [ ] (|) Check this against the bandwidth limits of the link and each branch (including each endpoint). If it passes, the job is done Second, try maximum DSC compression on all streams that support DSC [| ] ( ) [| ] ( ) If this does not pass, then enabling this combination of streams is impossible Otherwise, divide the remaining bandwidth evenly amongst the streams [ | ] ( ) [ | ] ( ) If one or more of the streams reach minimum compression, evenly divide the reamining bandwidth amongst the remaining streams [ |] ( ) [ |] ( ) [ | ] ( ) [ | ] ( ) If all streams can reach minimum compression, disable compression greedily [ |] ( ) [ |] ( ) [ ] (|) Perform this algorithm on each full update, on each MST link with at least one DSC stream on it After the configs are computed, call dcn20_add_dsc_to_stream_resource on each stream with DSC enabled. It is only after all streams are created that we can know which of them will need DSC. Do all of this at the end of amdgpu atomic check. If it fails, fail check; This combination of timings cannot be supported. v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc configurations v3: Use dc_dsc_policy structure to get min and max bpp rate for DSC configuration Acked-by: Lyude Paul <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Add PBN per slot calculation for DSCMikita Lipski2-0/+10
[why] Need to calculate VCPI slots differently for DSC to take in account current link rate, link count and FEC. [how] Add helper to get pbn_div from dc_link Acked-by: Lyude Paul <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Rename drm_dp_mst_atomic_check_topology_stateMikita Lipski1-3/+3
[why] drm_dp_mst_atomic_check_topology_state() should be renamed to reflect more specific type of check. Since it is verifying payload allocation limit it should be renamed into drm_dp_mst_atomic_check_vcpi_alloc_limit() Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add branch bandwidth validation to MST atomic checkMikita Lipski2-2/+65
[why] Adding PBN attribute to drm_dp_vcpi_allocation structure to keep track of how much bandwidth each Port requires. Adding drm_dp_mst_atomic_check_bw_limit to verify that state's bandwidth needs doesn't exceed available bandwidth. The funtion is called in drm_dp_mst_atomic_check after drm_dp_mst_atomic_check_topology_state to fully verify that the proposed topology is supported. v2: Fixing some typos and indenting v3: Return correct error enums if no bw space available Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add DSC enablement helpers to DRMMikita Lipski2-0/+66
Adding a helper function to be called by drivers outside of DRM to enable DSC on the MST ports. Function is called to recalculate VCPI allocation if DSC is enabled and raise the DSC flag to enable. In case of disabling DSC the flag is set to false and recalculation of VCPI slots is expected to be done in encoder's atomic_check. v2: squash separate functions into one and call it per port v3: Fix comment typos Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Manually overwrite PBN divider for calculating timeslotsMikita Lipski5-6/+13
[why] For DSC case we cannot use topology manager's PBN divider variable. The default divider does not take FEC into account. Therefore the driver has to calculate its own divider based on the link rate and lane count its handling, as it is hw specific. [how] Pass pbn_div as an argument, which is used if its more than zero, otherwise default topology manager's pbn_div will be used. Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Write DSC enable to MST DPCDDavid Francis1-1/+18
Rework the dm_helpers_write_dsc_enable callback to handle the MST case. Use the cached dsc_aux field. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Validate DSC caps on MST endpointsDavid Francis2-1/+29
During MST mode enumeration, if a new dc_sink is created, populate it with dsc caps as appropriate. Use drm_dp_mst_dsc_aux_for_port to get the raw caps, then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amd/display: Initialize DSC PPS variables to 0David Francis2-0/+6
For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage. memset to 0 to avoid this Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add new quirk for Synaptics MST hubsMikita Lipski3-0/+36
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not support virtual DPCD registers, but do support DSC. The DSC caps can be read from the physical aux, like in SST DSC. These hubs have many different DEVICE_IDs. Add a new quirk to detect this case. v2: Fix error when checking return of drm_dp_read_desc Reviewed-by: Wenjing Liu <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add helpers for MST DSC and virtual DPCD auxDavid Francis2-0/+145
Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED register might have to be written on the leaf port's DPCD, its parent's DPCD, or the MST manager's DPCD. This function finds the correct aux for the job. As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD is a DP feature new in DP v1.4, which exposes certain DPCD registers on virtual ports. v2: Remember to unlock mutex on all paths v3: Refactor to match coding style and increase brevity v4: - Check DSC capable MST sink connected directly to the device. - Check branch's port_parent to be set Cc: Lyude Paul <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Fill branch->num_portsDavid Francis1-0/+2
This field on drm_dp_mst_branch was never filled It is initialized to zero when the port is kzallocced. When a port is added to the list, increment num_ports, and when a port is removed from the list, decrement num_ports. v2: remember to decrement on port removal v3: don't explicitly init to 0 v4: move decrement of num_ports to unlink_port function Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add MST support to DP DPCD R/W functionsDavid Francis2-20/+22
Instead of having drm_dp_dpcd_read/write and drm_dp_mst_dpcd_read/write as entry points into the aux code, have drm_dp_dpcd_read/write handle both. This means that DRM drivers can make MST DPCD read/writes. v2: Fix spacing v3: Dump dpcd access on MST read/writes v4: Fix calling wrong function on DPCD write v5: delete deprecated include of drmP.h Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Parse FEC capability on MST portsDavid Francis2-0/+5
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating if FEC can be supported up to that point in the MST network. The bit is the first byte of the ENUM_PATH_RESOURCES ack reply, bottom-most bit (refer to section 2.11.9.4 of DP standard, v1.4) That value is needed for FEC and DSC support Store it on drm_dp_mst_port Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/dp_mst: Add PBN calculation for DSC modesDavid Francis7-11/+25
With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate function for this v3: In the equation divide bpp by 16 as it is expected not to leave any remainder v4: Added DSC test parameters for selftest Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-09drm/amdkfd: Improve kfd_process lookup in kfd_ioctlFelix Kuehling2-4/+28
Use filep->private_data to store a pointer to the kfd_process data structure. Take an extra reference for that, which gets released in the kfd_release callback. Check that the process calling kfd_ioctl is the same that opened the file descriptor. Return -EBADF if it's not, so that this error can be distinguished in user mode. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: Reduce HDMI pixel encoding if max clock is exceededThomas Anderson1-22/+23
For high-res (8K) or HFR (4K120) displays, using uncompressed pixel formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the "interesting" modes would be disabled, leaving only low-res or low framerate modes. This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS clock is exceeded. Verified that 8K30 and 4K120 are now available and working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Thomas Anderson <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: add event type check before restart the authenticationXiaodong Yan1-2/+7
[Why] Some combined docks will always trigger CP_IRQ but there's nothing the driver needs to take care of, but the CP_IRQ breaks the original hdcp state and triggers the driver to restart the authentication. [How] Add the event type check before restart the authentication or resend the stream management Signed-off-by: Xiaodong Yan <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: Add delay after h' watchdog timeout eventMichael Strauss1-4/+4
[WHY] Some monitors trigger HDCP2.x timeout after reinitializing (e.g. toggling HDR) by taking longer than expected to return h' (h prime) Previously the 200ms watchdog timer retry count would hit MAX_NUM_OF_ATTEMPTS (4), causing fallback to HDCP1.x [HOW] Adding a 1s delay after an h' watchdog timeout provides enough time for affected monitors to return h' in time without hitting MAX_NUM_OF_ATTEMPTS Signed-off-by: Michael Strauss <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: rx_validation failed resume from sleepJing Zhou1-4/+16
[why] Most DP/HDMI monitors need more time to response rx_validation request. [how] Add generic 1000ms delay. Signed-off-by: Jing Zhou <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: Return correct Error code for validate h_primeBhawanpreet Lakha1-1/+1
[Why] We are returning incorrect error code for validate h prime [How] Return the right Error code Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: Fix hdcp1 create sessionBhawanpreet Lakha1-1/+2
[Why] PSP needs session ID to destroy a session, In the case where we fail create session we don't have a session ID [How] Set the session ID before returning Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/display: fix psp return condition for hdcp moduleBhawanpreet Lakha1-1/+1
We are returning SUCCESS when hdcp_status != Success. Fix it. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd: use list_for_each_entry for list iteration.Wambui Karuga1-15/+4
list_for_each() can be replaced by the more concise list_for_each_entry() here for iteration over the lists. This change was reported by coccinelle. Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/radeon: remove unnecessary braces around conditionals.Wambui Karuga6-21/+18
As single statement conditionals do not need to be wrapped around braces, the unnecessary braces can be removed. Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/radeon: remove boolean checks in if statements.Wambui Karuga8-16/+16
Remove unnecessary variable comparisions to true/false in if statements and check the value of the variable directly. Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07Revert "drm/amdgpu: Set no-retry as default."Alex Deucher1-2/+2
This reverts commit 51bfac71cade386966791a8db87a5912781d249f. This causes stability issues on some raven boards. Revert for now until a proper fix is completed. Bug: https://gitlab.freedesktop.org/drm/amd/issues/934 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017 Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gfx: simplify old firmware warningAlex Deucher2-4/+2
Put it on one line to avoid whitespace issues when printing in the log. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gmc10: use common invalidation engine helperAlex Deucher2-16/+5
Rather than open coding it. This also changes the free masks to better reflect the usage by other components. Acked-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gmc: move invaliation bitmap setup to common codeAlex Deucher4-41/+42
So it can be shared with newer GMC versions. Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: updated UMC error address record with correct channel indexJohn Clements1-33/+32
defined macros for repetitive for loops Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: resolved bug in UMC RAS CE queryJohn Clements1-12/+20
switch CE counter register access' to use SMN disable UMC indexing mode Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: cleanup the interfaces for powergate setting through SMUEvan Quan3-35/+37
Provided an unified entry point. And fixed the confusing that the API usage is conflict with what the naming implies. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: issue proper hdp flush for table transferringEvan Quan5-10/+30
Guard the content consistence between the view of GPU and CPU during the table transferring. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: refine code to support no-dpm caseEvan Quan3-1/+20
With "dpm=0", there will be no DPM enabled. The code needs to be refined to support this. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2Evan Quan11-47/+117
By this, we can avoid to pass in the VRAM address on every table transferring. That puts extra unnecessary traffics on SMU on some cases(e.g. polling the amdgpu_pm_info sysfs interface). V2: document what the driver table is for and how it works Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: cache the watermark settings on system memoryEvan Quan6-16/+24
So that we do not need to allocate a piece of VRAM for it. This is a preparation for coming change which unifies the VRAM address for all driver tables interaction with SMU. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/smu: custom pstate profiling clock frequence for navi series asicsKevin Wang2-3/+50
add navi10 & navi14 pstate profiling clock value support. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN from VFZhigang Luo1-10/+12
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VFZhigang Luo1-7/+11
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhubZhigang Luo2-37/+44
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub ↵Zhigang Luo2-37/+48
from VF Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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