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2022-09-14dt-bindings: pinctrl: qcom,sm6125-pinctrl: extend exampleKrzysztof Kozlowski1-13/+33
Extend example with children for pin configuration and indent it with 4-spaces. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-14dt-bindings: pinctrl: qcom,sm6125-pinctrl: do not require function on non-GPIOsKrzysztof Kozlowski1-2/+10
Certain pins, like SDcard related, do not have functions and such should not be required: sdc1-clk-pins: 'function' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-14dt-bindings: pinctrl: qcom,sm6125-pinctrl: fix matching pin configKrzysztof Kozlowski1-1/+2
Matching PMIC GPIOs config nodes within a '-state' node by '.*' pattern does not work as expected because of linux,phandle in the DTB: 'pins' is a required property 'function' is a required property 'rx', 'tx' do not match any of the regexes: 'pinctrl-[0-9]+' [[59]] is not of type 'object' Make the schema stricter and expect such nodes to be followed with a '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-14dt-bindings: pinctrl: qcom,sm6115-pinctrl: fix indentation in exampleKrzysztof Kozlowski1-40/+40
Bindings example should be indented with 4-spaces. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Iskren Chernev <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-14dt-bindings: pinctrl: qcom,sm6115-pinctrl: require function on GPIOsKrzysztof Kozlowski1-1/+10
Require function on GPIOs (so not on SD card pins). Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Iskren Chernev <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-14dt-bindings: pinctrl: qcom,sm6115-pinctrl: fix matching pin configKrzysztof Kozlowski1-5/+6
Matching PMIC GPIOs config nodes within a '-state' node by '.*' pattern does not work as expected because of linux,phandle in the DTB: 'pins' is a required property 'function' is a required property 'rx', 'tx' do not match any of the regexes: 'pinctrl-[0-9]+' [[59]] is not of type 'object' Make the schema stricter and expect such nodes to be followed with a '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Iskren Chernev <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-09pinctrl: cy8c95x0: Use 'default' in all switch-cases (part 2)Andy Shevchenko1-2/+2
Move the default values to the 'default' case in the switches. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: pistachio: Correct the fwnode_irq_get() return value checkAndy Shevchenko1-0/+6
fwnode_irq_get() may return all possible signed values, such as Linux error code or 0. Fix the code to handle this properly. Fixes: 1074e1d23a5c ("pinctrl: pistachio: Switch to use fwnode instead of") Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: qcom: spmi-gpio: Make irqchip immutableManivannan Sadhasivam1-10/+28
The irqchip implementation used inside the gpiochips are not supposed to be changed during runtime. So let's make the one inside the spmi-gpio gpiochip immutable. This fixes the below warning during boot: gpio gpiochip0: (c440000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Acked-by: Marc Zyngier <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] [switched two lines as indicated by Johan] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: meson: Switch to use fwnode instead of of_nodeAndy Shevchenko2-5/+6
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: microchip-sgpio: Correct the fwnode_irq_get() return value checkAndy Shevchenko1-2/+3
fwnode_irq_get() may return all possible signed values, such as Linux error code. Fix the code to handle this properly. Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)") Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: ingenic: Switch to use fwnode instead of of_nodeAndy Shevchenko1-14/+17
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08dt-bindings: pinctrl: qcom: sm6115: Add reserved rangesIskren Chernev1-0/+2
Ideally this and similar common properties will be inherited so you won't need to paste them in every pinctrl binding. Signed-off-by: Iskren Chernev <[email protected]> Reviewed-by: Caleb Connolly <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: imx8m: kconfig: Fix build error on test compileFrancesco Dolcini1-0/+4
PINCTRL_IMX depends on OF, however the dependency is missed when selected by PINCTRL_IMX8M* (it does not follow the indirect 'select' statements), select it explicitly. Cc: Arnd Bergmann <[email protected]> Cc: Linus Walleij <[email protected]> Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Fixes: 87c2a29a6bf1 ("pinctrl: imx8m: kconfig: Depends on SOC_IMX8M") Signed-off-by: Francesco Dolcini <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Correct comment styleAndy Shevchenko1-20/+20
In a few comments the style is not aligned with the rest. Correct them. While at it, drop unneeded blank lines and deduplicate 'Author'. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: use bits.h macros for all masksAndy Shevchenko1-9/+9
Make use of the GENMASK() (far less error-prone, far more concise). Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Override IRQ for one of the expanders on Galileo Gen 1Andy Shevchenko1-0/+48
ACPI table on Intel Galileo Gen 1 has wrong pin number for IRQ resource of the I²C GPIO expander. Since we know what that number is and luckily have GPIO bases fixed for SoC's controllers, we may use a simple DMI quirk to match the platform and retrieve GpioInt() pin on it for the expander in question. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: support ACPI device found on Galileo Gen1Andy Shevchenko1-0/+7
Add support of the expander found on Intel Galileo Gen1 board. The platform information comes from ACPI. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Make use of device propertiesAndy Shevchenko2-8/+10
Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Add mod_devicetable.h include. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Implement ->pin_dbg_show()Andy Shevchenko1-8/+32
The introduced callback ->pin_dbg_show() is useful for debugging. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Use 'default' in all switch-casesAndy Shevchenko1-6/+8
Move the default values to the 'default' case in the switches. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Remove custom ->set_config()Andy Shevchenko1-25/+1
Since we have pin configuration getter and setter provided, there is no need to duplicate that in the custom ->set_config(). Instead, switch to gpiochip_generic_config(). Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Remove useless conditionalsAndy Shevchenko1-14/+0
The pin control framework checks pin boundaries before calling the respective driver's callbacks. Hence no need to check for pin boundaries, the respective conditionals won't be ever true. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Remove device initializationAndy Shevchenko1-28/+0
The Cypress CY8C95x0 chips have an internal EEPROM that defines initial configuration. It might be that bootloader or other entity wrote the platform related setup into it. Don't override it in the driver. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Enable GPIO rangeAndy Shevchenko1-4/+18
Since it's a pin control, GPIO counterpart needs to know the mapping between pin numbering and GPIO numbering. Enable this by calling gpiochip_add_pin_range() at the chip addition time. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Drop unneeded npins assignmentAndy Shevchenko1-1/+0
The npins field is assigned twice. Remove the first occurrence. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Fix pin control name to enable more than oneAndy Shevchenko1-2/+1
The Cypress GPIO expander is an I²C discrete component. Hence the platform may contain more than one of a such. Currently this has limitations in the driver due to same name used for all chips of a type. Replace this with device instance specific name. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Fix return value in cy8c95x0_detect()Andy Shevchenko1-1/+1
It's an obvious typo in never tested piece of code that successful detection shouldn't fail. Fix that. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: Allow IRQ chip core to handle numberingAndy Shevchenko1-1/+0
No need to assign first line number for IRQ chip. Let IRQ core to decide. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-08pinctrl: cy8c95x0: make irq_chip immutableAndy Shevchenko1-13/+19
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Patrick Rudolph <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-05pinctrl: berlin: fix spelling typo in commentJiangshan Yi1-1/+1
Fix spelling typo in comment. Reported-by: k2ci <[email protected]> Signed-off-by: Jiangshan Yi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03pinctrl: pistachio: Switch to use fwnode instead ofAndy Shevchenko1-12/+11
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03pinctrl: at91: use dev_dbg() instead of printk()Claudiu Beznea1-2/+2
Use dev_dbg() instead of printk(KERN_DEBUG) to avoid the following checkpatch.pl warning: "Prefer [subsystem eg: netdev]_dbg([subsystem]dev, ... then dev_dbg(dev, ... then pr_debug(... to printk(KERN_DEBUG ...". Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03pinctrl: at91: move gpio suspend/resume calls to driver's contextClaudiu Beznea3-74/+36
Move gpio suspend/resume execution local to driver and let it execute as close as possible to the moment the machine specific PM code is executed (by setting it to .noirq member of dev_pm_ops). With this the at91_pinctrl_gpio_suspend()/at91_pinctrl_gpio_resume() calls were removed from arch/arm/mach-at91/pm.c and also a header has been removed. The patch has been checked on sama5d3_xplained, sam9x60ek, sama5d2_xplained, sama7g5ek boards. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03pinctrl: at91: use kernel-doc style for documentation of at91_gpio_chipClaudiu Beznea1-7/+19
Use kernel-doc style for documentation of struct at91_gpio_chip. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03pinctrl: mcp23s08: Drop assignment of default number of OF cellsAndy Shevchenko1-3/+0
The GPIO library code will assign default value for number of OF cells, no need to repeat this in the driver. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-09-03Merge tag 'renesas-pinctrl-for-v6.1-tag1' of ↵Linus Walleij1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.1 - Document pin control support for the RZ/Five SoC.
2022-08-31pinctrl: imx8m: kconfig: Depends on SOC_IMX8MFrancesco Dolcini1-4/+4
Change PINCTRL_IMX8M* dependency from just ARCH_MXC to SOC_IMX8M, likewise is done for other PINCTRL_IMX* kconfig. This avoid polluting the config when SOC_IMX8M is not enabled. Signed-off-by: Francesco Dolcini <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-31pinctrl: amd: change dev_warn to dev_dbg for additional feature supportBasavaraj Natikar1-2/+2
Use dev_dbg instead of dev_warn for additional support of pinmux feature. Signed-off-by: Basavaraj Natikar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-31pinctrl: aspeed: Force to disable the function's signalBilly Tsai1-10/+1
When the driver want to disable the signal of the function, it doesn't need to query the state of the mux function's signal on a pin. The condition below will miss the disable of the signal: Ball | Default | P0 Signal | P0 Expression | Other -----+---------+-----------+-----------------------------+---------- E21 GPIOG0 SD2CLK SCU4B4[16]=1 & SCU450[1]=1 GPIOG0 -----+---------+-----------+-----------------------------+---------- B22 GPIOG1 SD2CMD SCU4B4[17]=1 & SCU450[1]=1 GPIOG1 -----+---------+-----------+-----------------------------+---------- Assume the register status like below: SCU4B4[16] == 1 & SCU4B4[17] == 1 & SCU450[1]==1 After the driver set the Ball E21 to the GPIOG0: SCU4B4[16] == 0 & SCU4B4[17] == 1 & SCU450[1]==0 When the driver want to set the Ball B22 to the GPIOG1, the condition of the SD2CMD will be false causing SCU4B4[17] not to be cleared. Signed-off-by: Billy Tsai <[email protected]> Acked-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-26pinctrl: nuvoton: Use 'unsigned int' instead of just 'unsigned'.Jilin Yuan1-4/+4
'unsigned int' should be clearer than 'unsigned'. Signed-off-by: Jilin Yuan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-26dt-bindings: pinctrl: Add missing (unevaluated|additional)Properties on ↵Rob Herring10-0/+15
child nodes In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-26pinctrl: amd: Pick some different unicode symbolsMario Limonciello1-14/+14
Feedback from Kent had showed some better selections for symbols to use for pinctrl-amd debugfs output. Adopt some of those instead. Fixes: e8129a076a50 ("pinctrl: amd: Use unicode for debugfs output") Suggested-by: Kent Gibson <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-26pinctrl: fixup for "i2c: Make remove callback return void"Stephen Rothwell1-3/+1
Fix up the build. Signed-off-by: Stephen Rothwell <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-26Merge branch 'i2c/make_remove_callback_void-immutable' of ↵Linus Walleij622-1762/+660
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux into devel This branch is needed to make the i2c driver remove() callback in new driver compile properly. Signed-off-by: Linus Walleij <[email protected]>
2022-08-25dt-bindings: pinctrl: mt8186: Fix 'reg-names' for pinctrl nodesAllen-KH Cheng1-7/+7
The mt8186 contains 8 GPIO physical address bases that correspond to the 'reg-names' of the pinctrl driver. The 'reg-names' entries in bindings are ordered incorrectly, though. The system crashes due of an erroneous address when the regulator initializes. We fix the 'reg-names' for the pinctrl nodes and the pinctrl-mt8186 example in bindings. Fixes: 338e953f1bd1 ("dt-bindings: pinctrl: mt8186: add pinctrl file and binding document") Co-developed-by: Guodong Liu <[email protected]> Signed-off-by: Guodong Liu <[email protected]> Signed-off-by: Allen-KH Cheng <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25pinctrl: mediatek: add mt8188 driverHui.Liu4-0/+3945
Add pinctrl driver support for MediaTek SoC mt8188. Signed-off-by: Hui.Liu <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25dt-bindings: pinctrl: mediatek: add support for mt8188Hui.Liu2-0/+1506
Add the pinctrl header file on MediaTek mt8188. Add the new binding document for pinctrl on MediaTek mt8188. Signed-off-by: Hui.Liu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driverSrinivas Kandagatla3-0/+217
Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SC8280XP. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindingsSrinivas Kandagatla1-0/+133
Add device tree binding Documentation details for Qualcomm SC8280XP LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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