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2017-04-12drm/i915/gvt: remove redundant ring id check which cause significant CPU ↵Changbin Du1-6/+0
misprediction From perf data, found a significant overhead at ring id check in the function get_opcode. This inline function is frequently used. Since Intel static predictor will predict the branch to fall through so the prediction most fail. This is wasting CPU pipeline resource. We do not need check the engine id everywhere, it should be reliable. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-04-12drm/i915/gvt: remove redundant platform check for mocs load/restoreChangbin Du1-6/+0
The platform check is done outside, no need check again. Platform doesn't include mocs should not invoke this two functions. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-04-12drm/i915/gvt: Align render mmio list to cachelineChangbin Du1-2/+2
Make the global mmio list be cacheline aligned to improve performance. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-04-06drm/i915/gvt: cleanup some too chatty scheduler messageZhenyu Wang1-9/+1
It's too chatty to have three places to tell us which one is next vgpu for schedule. My log file was bloated to eat all disk space.. Cc: Ping Gao <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: control the scheduler by timeslice usagePing Gao1-2/+7
The timeslice usage will determine vGPU whether has chance to schedule or not at every vGPU switch checkpoint. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: create an idle vGPUPing Gao3-1/+69
vGPU resource is allocated by scheduler. To account for non-allocated free cycles, we create an idle vGPU as the placeholder similar to idle task concept, which is useful to handle some corner cases in scheduling policy. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: add basic function for weight controlPing Gao1-0/+59
This method tries to guarantee precision in second level, with the adjustment conducted in every 100ms. At the end of each vGPU switch calculate the sched time and subtract it from the time slice allocated; the allocated time slice for every 100ms together with remaining timeslice, will be used to decide how much timeslice allocated to this vGPU in the next 100ms slice, with the end goal to guarantee weight ratio in second level. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: define weight according to vGPU typePing Gao4-7/+33
The weight defines proportional control of physical GPU resource shared between vGPUs. So far the weight is tied to a specific vGPU type, i.e when creating multiple vGPUs with different types, they will inherit different weights. e.g. The weight of type GVTg_V5_2 is 8, the weight of type GVTg_V5_4 is 4, so vGPU of type GVTg_V5_2 has double vGPU resource of vGPU type GVTg_V5_4. TODO: allow user control the weight setting in the future. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: factor out the schedulerPing Gao1-30/+36
Factor out the scheduler to a more clear structure, the basic logic is to find out next vGPU first and then schedule it. vGPUs were ordered in a LRU list, scheduler scan from the LRU list head and choose the first vGPU who has pending workload. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: add some statistic routine for schedulerPing Gao3-25/+48
Add some statistic routine to collect the time when vGPU is scheduled in/out and the time of the last ctx submission. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: use hrtimer replace delayed_work in schedulerPing Gao4-16/+41
Currently the scheduler is triggered by delayed_work, which doesn't provide precision at microsecond level. Move to hrtimer instead for more accurate control. Signed-off-by: Ping Gao <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: remove the redundant info NULL checkTina Zhang1-7/+0
The variable info is never NULL, which is checked by the caller. This patch removes the redundant info NULL check logic. Fixes: 695fbc08d80f ("drm/i915/gvt: replace the gvt_err with gvt_vgpu_err") Signed-off-by: Tina Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-30drm/i915/gvt: adjust mem size for low resolution typeZhenyu Wang1-1/+1
From commit d1a513be1f0a ("drm/i915/gvt: add resolution definition for vGPU type"), small type has been restricted to small resolution, so not require larger high GM size any more. Change to smaller 384M for more VM creation with vGPU enabled which still perform reasonable workload. Fixes: d1a513be1f0a ("drm/i915/gvt: add resolution definition for vGPU type") Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: remove workload from intel_shadow_wa_ctx structureTina Zhang3-13/+22
intel_shadow_wa_ctx is a field of intel_vgpu_workload. container_of() can be used to refine the relation-ship between intel_shadow_wa_ctx and intel_vgpu_workload. This patch removes the useless dereference. v2. add "drm/i915/gvt" prefix. (Zhenyu) Signed-off-by: Tina Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Turn on KBL platform support.Xu Han1-0/+2
Turn on KBL WS platform support in gvt-g. More platforms would be enabled, after validate. Signed-off-by: Xu Han <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Add KBL dispatch logic in each function.Xu Han8-26/+43
Extend function dispatch logic to support KBL platform. Signed-off-by: Xu Han <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Update save/restore list to compatible KBL platform.Xu Han1-0/+12
Add some KBL specially registers to save/restore list. Signed-off-by: Xu Han <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Update MMIO handle policy to compatible KBL platform.Xu Han1-198/+211
Update MMIO handle policy to KBL platform. Signed-off-by: Xu Han <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Add KBL platform definition.Xu Han1-9/+10
Add KBL platform definition. Signed-off-by: Xu Han <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: Add mdev device attribute groupZhenyu Wang1-0/+32
This adds initial attribute group for mdev to hold vGPU related for each mdev device, currently just vGPU id is shown. v2: rename group name as "intel_vgpu" Signed-off-by: Zhenyu Wang <[email protected]> Reviewed-by: Kevin Tian <[email protected]>
2017-03-29drm/i915/gvt: make dpcd_fix_data supports DP1.2Pei Zhang1-1/+2
GVT-g will emulate a fixed DPCD data to VM for DP/eDP panel. Update this data to latest DP1.2 with the maximum lane bandwidth of 5.4G/s to support 4K resolution in VM. V3: modify patch comment V2: add inline comment to describe the dpcd_fix_data. Signed-off-by: Pei Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29drm/i915/gvt: emulate SKL_FUSE_STATUS and LCPLL_CTL for virtual monitor ↵Weinan Li1-1/+12
detection Initialize the correct vreg for virtual monitor. Set PG0/1/2 distribution and fuse download done in SKL_FUSE_STATUS. Set PLL_ENABLE and PLL_LOCK in LCPLL_CTL. Guest may need to check these registers for display monitor detection on Skylake platforms. Signed-off-by: Weinan Li <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-03-29Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queuedDaniel Vetter1-4/+4
Backmerge drm-next one more because Dave fumbled the conflict resolution slightly and I didn't notice it. We need Zhenyu's hotfix before he can assemble the gvt pull ... Signed-off-by: Daniel Vetter <[email protected]>
2017-03-29drm/i915/gvt: fix error return check for copy_gma_to_hva()Zhenyu Wang1-4/+4
From commit 73dec95e6ba3 ("drm/i915: Emit to ringbuffer directly"), copy_gma_to_hva() now returns copied data length instead of 0, so need to change error return check for that. Note: Looks this is caused by backmerge conflict resolving, so 4.11-rc4 is not impacted as commit 73dec95e6ba3 ("drm/i915: Emit to ringbuffer directly") is not in 4.11. But need to fix this before I can apply 4.12 stuff against drm-intel-next correctly. Fixes: e5c1ff14757a ("Backmerge tag 'v4.11-rc4' into drm-next") Cc: Dave Airlie <[email protected]> Cc: Tina Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2017-03-28drm/i915/dp: reduce link M/N parametersJani Nikula1-0/+11
Several major vendor USB-C->HDMI converters, in particular the DA200, fail to recover a 5.4 GHz 1 lane signal if the link N is greater than 0x80000. The link M and N depend on the pixel clock and link clock ratio. With current code link N exceeds 0x80000 only when link clock >= 540000 kHz. Except for the eDP intermediate link clocks, at least the four least significant bits are always zero. Just one bit shift right would be enough to bring even the DP 1.4 810000 kHz link clock under 0x80000 link N. The pixel clock for modes that require a link clock >= 540000 kHz would also have several least significant bits zero. Unless the user provides a mode with an odd pixel clock value, we can reduce the numbers to reach the goal, with no loss in precision. The DP spec even mentions sources making choices that "allow for static and relatively small Mvid and Nvid values", thus reducing the link M/N regardless of the sink in question seems justified. Everything here is based on the work and information gathered by Clint Taylor <[email protected]>. This is just an iteration to reduce the parameters regardless of lane count, link rate, or sink. Reference: http://patchwork.freedesktop.org/patch/msgid/[email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578 Tested-by: Mads <[email protected]> Tested-by: PJ <[email protected]> Tested-by: François Guerraz <[email protected]> Tested-by: Lev Popov <[email protected]> Tested-by: Igor Krivenko <[email protected]> Tested-by: Clint Taylor <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Reviewed-by: Dhinakaran Pandiyan <[email protected]> Acked-by: Daniel Vetter <[email protected]> Cc: Clint Taylor <[email protected]> Cc: Anusha Srivatsa <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28drm/i915: Take rpm wakelock around debugfs/i915_gpu_infoChris Wilson1-1/+4
Capturing GPU state requires the device to be awake in order to read registers. Normally, this is taken along the error handler, but for the direct debugfs access, we cannot make assumptions about the current device state and so either need to wake it up, or abort. Fixes: 5a4c6f1b1b2d ("drm/i915: The return of i915_gpu_info to debugfs") Testcase: igt/pm_rpm/debugfs-read Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-28drm/i915: WARN if the core runtime PM get helpers failImre Deak1-3/+9
We don't expect the core runtime PM get helpers to return any error, so add a WARN for this. Also print the return value for all the callsites to help debugging. v2: - Don't call pm_runtime_get_sync() as part of initing locals. (Chris) Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28drm/i915/perf: remove user triggerable warnMatthew Auld1-2/+6
Don't throw a warning if we are given an invalid property id. While here let's also bring back Robert' original idea of catching unhandled enumeration values at compile time. Fixes: eec688e1420d ("drm/i915: Add i915 perf infrastructure") Signed-off-by: Matthew Auld <[email protected]> Cc: Robert Bragg <[email protected]> Reviewed-by: Robert Bragg <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28drm/i915: update the firmware download URLJani Nikula1-1/+1
The old URL works but gives 301 Moved Permanently. Update. Reviewed-by: Michal Wajdeczko <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queuedDaniel Vetter379-2577/+3469
Backmerge drm-next to get at -rc4, which we need to land the 4.12 gvt patches. Signed-off-by: Daniel Vetter <[email protected]>
2017-03-28Backmerge tag 'v4.11-rc4' into drm-nextDave Airlie379-2577/+3469
Linux 4.11-rc4 The i915 GVT team need the rc4 code to base some more code on.
2017-03-28drm/i915/perf: destroy stream on sample_flags mismatchMatthew Auld1-1/+2
If we were to ever encounter a sample_flags mismatch we need to ensure we destroy the stream when we bail. Fixes: d79651522e89 ("drm/i915: Enable i915 perf stream for Haswell OA unit") Signed-off-by: Matthew Auld <[email protected]> Cc: Robert Bragg <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28drm/i915: allow HDMI 2.0 clock ratesShashank Sharma1-0/+2
Geminilake has a native HDMI 2.0 controller, which is capable of driving clocks upto 594Mhz. This patch updates the max tmds clock limit for the same. V2: rebase V3: rebase V4: added r-b from Ander V5: rebase V6: rebase V7: rebase V8: rebase V9: rebase V10: rebase Cc: Ander Conselvan De Oliveira <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Reviewed-by: Ander Conselvan De Oliveira <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-28drm/i915: enable scramblingShashank Sharma5-0/+106
Geminilake platform sports a native HDMI 2.0 controller, and is capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec mendates scrambling for these higher clocks, for reduced RF footprint. This patch checks if the monitor supports scrambling, and if required, enables it during the modeset. V2: Addressed review comments from Ville: - Do not track scrambling status in DRM layer, track somewhere in driver like in intel_crtc_state. - Don't talk to monitor at such a low layer, set monitor scrambling in intel_enable_ddi() before enabling the port. V3: Addressed review comments from Jani - In comments, function names, use "sink" instead of "monitor", so that the implementation could be close to the language of HDMI spec. V4: Addressed review comment from Maarten - scrambling -> hdmi_scrambling - high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio V5: Addressed review comments from Ville and Ander - Do not modifiy the crtc_state after compute_config. Move all scrambling and tmds_clock_ratio calcutations to compute_config. - While setting scrambling for source/sink, do not check the conditions again, just go by the crtc_state flags. This will simplyfy the condition checks. V6: Addressed review comments from Ville - Do not add IS_GLK check in disable/enable function, instead add it in compute_config, while setting state flags. - Remove unnecessary paranthesis. - Simplyfy handle_sink_scrambling function as suggested. - Add readout code for scrambling status in get_ddi_config and add a check for the same in pipe_config_compare. V7: Addressed review comments from Ander/Ville - No separate function for source scrambling, make it inline - Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK - Do not add platform check while setting source scrambling - Use pipe_config instead of crtc->config to set sink scrambling - To readout scrambling status, Compare with SCRAMBLING_MASK not any of its bits - Remove platform check in intel_pipe_config_compare while checking scrambling status V8: Fixed mege conflict, Addressed review comments from Ander - Remove the desciption/comment about scrambling fom the caller, move it to the function - Move the IS_GLK check into scrambling function - Fix alignment V9: Fixed review comments from Ville, Ander - Pass the scrambling state variables as bool input to the sink_scrambling function and let the disable call be unconditional. - Fix alignments in function calls and debug messages. - Add kernel doc for function intel_hdmi_handle_sink_scrambling V10: Rebase Signed-off-by: Shashank Sharma <[email protected]> Reviewed-by: Ander Conselvan de Oliveira <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-27drm/i915: kill intel_ddi_pll_select()Paulo Zanoni3-26/+11
All it does is pick the encoder and call intel_get_shared_dpll(). We can just do this in the caller. One less indirection level during code reading. As another plus, now the two callers of intel_get_shared_dpll() are {ironlake,haswell}_crtc_compute_clock(). Reported-by: Ville Syrjälä <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-27drm/i915: Mark manually wedged engines as guiltyChris Wilson1-5/+11
Use the incoming value from debugfs/i915_wedged to select which engines to marked as guilty in order to force us to reset those requests (required to quickly bypass simulated hangs). Testcase: igt/gem_exec_capture Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-27drm/i915: Refactor tests for validity of RING_TAILChris Wilson4-15/+19
Whilst I like having the assertions clearly visible in the code, they are quite repetitious! As we find new limits we want to incorporate into the set of assertions, it make sense to refactor them to a common routine. v2: Add a guc holdout. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-27drm/i915: Assert that the request->tail fits within the ringChris Wilson2-0/+7
In addition to being qword-aligned, the RING_TAIL offset must be within the ring! Signed-off-by: Chris Wilson <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-27drm/i915/execlists: Wrap tail pointer after reset tweakingChris Wilson2-3/+11
If the request->wa_tail is 0 (because it landed exactly on the end of the ringbuffer), when we reconstruct request->tail following a reset we fill in an illegal value (-8 or 0x001ffff8). As a result, RING_HEAD is never able to catch up with RING_TAIL and the GPU spins endlessly. If the ring contains a couple of breadcrumbs, even our hangcheck is unable to catch the busy-looping as the ACTHD and seqno continually advance. v2: Move the wrap into a common intel_ring_wrap(). Fixes: a3aabe86a340 ("drm/i915/execlists: Reinitialise context image after GPU hang") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: <[email protected]> # v4.10+ Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-27drm/i915: Use i9xx_check_plane_surface() for sprite planes as wellVille Syrjälä3-47/+27
All the pre-SKL sprite planes compute the x/y/tile offsets in a similar way. There are a couple of minor differences but the primary planes have those as well. Thus i9xx_check_plane_surface() already does what we need, so let's use it. Signed-off-by: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2017-03-27drm/i915: Eliminate ironlake_update_primary_plane()Ville Syrjälä1-49/+6
The effective difference between i9xx_update_primary_plane() and ironlake_update_primary_plane() is only the HSW/BDW DSPOFFSET special case. So bring that over into i9xx_update_primary_plane() and eliminate the duplicated code. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-27drm/i915: Introduce i9xx_check_plane_surface()Ville Syrjälä1-32/+50
Extract the primary plane surfae offset/x/y calculations for pre-SKL platforms into a common function, and call it during the atomic check phase to reduce the amount of stuff we have to do during the commit phase. SKL is already doing this. v2: Update the comment about the rotation adjustments to match the code better (Chris) Cc: Chris Wilson <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-27drm/i915: Pre-compute plane control register valueVille Syrjälä3-32/+36
Computing the plane control register value is branchy so moving it out from the plane commit hook seems prudent. Let's pre-compute it during the atomic check phase and store the result in the plane state. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-03-27drm/i915: Nuke ironlake_plane_ctl()Ville Syrjälä1-52/+6
Share the code to compute the primary plane control register value between the i9xx and ilk codepaths as the differences are minimal. Actually there are no differences between g4x and ilk, so the current split doesn't really make any sense. Cc: Chris Wilson <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2017-03-27drm/i915: Extract i9xx_plane_ctl() and ironlake_plane_ctl()Ville Syrjälä1-38/+66
Pull the code to calculate the pre-SKL primary plane control register value into separate functions. Allows us to pre-compute it in the future. v2: Split the pre-ilk vs. ilk+ unification to a separate patch (Chris) Cc: Chris Wilson <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2017-03-27drm/i915: Use BIT() for computing the engine's flagChris Wilson1-2/+2
Since the engine's flag is just the bit of its id, use BIT(). Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]>
2017-03-27drm/i915: Remove unused intel_flush_status_page()Chris Wilson1-8/+0
intel_flush_status_page() is defunct since commit f8dd2934c4ec ("drm/i915: Remove BXT incoherent seqno write workaround"), time to remove it. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]>
2017-03-27drm/i915: Fixup intel_write_status_page() for old CPUs without clflushChris Wilson1-7/+15
Not all of our target platforms have clflush. For those without, just assume the status page is sufficiently coherent that we do not need our paranoia. Reported-by: Ville Syrjälä <[email protected]> Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with a clflush") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Tested-by: Ville Syrjälä <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]>
2017-03-27drm/i915: Align "unfenced" tiled access on gen2, early gen3Chris Wilson3-1/+9
Old devices have quite severe restrictions for using fences, and unlike more recent device (anything from Pineview onwards) we need to enforce those restrictions even for unfenced tiled access from the render pipeline. Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma") Reported-by: Ville Syrjälä <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: <[email protected]> # v4.11-rc1+ Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Tested-by: Ville Syrjälä <[email protected]>
2017-03-27drm/i915: Limit number of reads to stabilize rc6 counter readsChris Wilson1-1/+2
We have only 8bits of precise timestamps in which to complete our upper/load reads, along with the switch between precision. This is not always enough time to read the upper counter twice within the same time slice, leading to hard lockups. Limit the number of times to prevent an inifite loop (my fault for assuming we would have no trouble doing the write + reads fast enough). Fixes: 47c21d9a1a7b ("drm/i915: Extend vlv/chv residency resolution") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100377 Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
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