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2023-12-21drm/xe/dg2: Remove one PCI IDShekhar Chauhan1-1/+0
The bspec was recently updated to remove PCI ID 0x5698; this ID is actually reserved for future use and should not be treated as DG2-G11. BSpec: 44477 Signed-off-by: Shekhar Chauhan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add new DG2 PCI IDsShekhar Chauhan1-1/+5
Add recently added PCI IDs for DG2 BSpec: 44477 Signed-off-by: Shekhar Chauhan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Set PTE_AE for smem allocations in integrated devicesJosé Roberto de Souza1-3/+6
Without this if a atomic operation is executed in Xe2 integrated GPUs it causes engine memory catastrophic error. This fixes at least 3 failures in piglit sanity and 2 failures in crucible for LNL. v3: - only add PTE_AE to smem in integrated Cc: Matt Roper <[email protected]> Cc: Lucas De Marchi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: refactor xe_mmio_probe_tiles to support MMIO extensionKoby Elbaz1-32/+38
In future ASICs, there will be an additional MMIO extension space for all tiles altogether, residing on top of MMIO address space. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: map MMIO BAR according to the num of tiles in device descKoby Elbaz1-7/+6
When MMIO BAR is initially mapped, the driver assumes a single tile device. However, former memory allocations take all tiles into account. First, a common standard for resource usage is needed here. Second, with the next (6th) patch in this series, the MMIO BAR remapping will be done only if a reduced-tile device is attached. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add MMIO extension support flagsKoby Elbaz3-0/+9
Besides the regular MMIO space that exists by default, MMIO extension support & MMIO extension tile size should both be defined per device, and updated from the device's descriptor. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add a flag to bypass multi-tile config from MTCFG regKoby Elbaz3-11/+17
Skip reading this register as it is not relevant in the new devices. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add read/write support for MMIO extension spaceKoby Elbaz1-4/+4
A distinction has to be made when addressing the MMIO space or the additional MMIO extension space. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add 28-bit address support in struct xe_regKoby Elbaz2-1/+28
Xe driver currently supports 22-bit addresses for MMIO access. Future platforms will have additional MMIO extension with larger address spaces, and to access them, the driver will have to support wider address representation. Please note that while the XE_REG macro is used for MMIO access, XE_REG_EXT macro will be used for MMIO-extension access. Signed-off-by: Koby Elbaz <[email protected]> Reviewed-by: Ofir Bitton <[email protected]> Reviewed-by: Moti Haimovski <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: directly use pat_index for pte_encodeMatthew Auld7-40/+43
In a future patch userspace will be able to directly set the pat_index as part of vm_bind. To support this we need to get away from using xe_cache_level in the low level routines and rather just use the pat_index directly. v2: Rebase v3: Some missed conversions, also prefer tile_to_xe() (Niranjana) v4: remove leftover const (Lucas) Signed-off-by: Matthew Auld <[email protected]> Cc: Niranjana Vishwanathapura <[email protected]> Cc: Pallavi Mishra <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: Pallavi Mishra <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pat: trim the xelp PAT tableMatthew Auld1-4/+0
We don't seem to use the 4-7 pat indexes, even though they are defined by the HW. In a future patch userspace will be able to directly set the pat_index as part of vm_bind and we don't want to allow setting 4-7. Simplest is to just ignore them here. Suggested-by: Matt Roper <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Cc: Pallavi Mishra <[email protected]> Cc: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add missing ADL entries to xe_test_waAnusha Srivatsa1-0/+1
With all ADl platforms and subplatforms added, also add support to xe_wa_test kunit tests for checking their WAs. Cc: Lucas De Marchi <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/rpls: Add Stepping info for RPLSAnusha Srivatsa1-0/+8
Add stepping-substepping info. Though it looks weird, the revision ID for the newer stepping is indeed backwards and is in accordance to the spec. v2: s/RPLS/RAPTORLAKE_S (Anusha) v3: rebase (Anusha) Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Matt Roper <[email protected]>(v1) Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/rpls: Add RPLS SupportAnusha Srivatsa3-0/+9
Add RPLS support that was missing apart from the PCI IDs. v2: Also add the support in xe_wa_test kunit v3: rebased. Cc: Dnyaneshwar Bhadane <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Matt Roper <[email protected]>(v1) Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/rplu: s/ADLP/ALDERLAKE_PAnusha Srivatsa3-3/+3
i915 now uses full names for platforms. So we now have ALDERLAKE instead of ADL. Extend this to xe driver as well. This will make it easier for macro magic usages. v2: Do not make changes to compat-i915-headers/i915_drv.h file with the rest of the changes (Jani) Cc: Jani Nikula <[email protected]> Cc: Dnyaneshwar Bhadane <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/rtp: Fix doc for XE_RTP_ACTIONSGustavo Sousa1-3/+2
Replace the paragraph that was meant for XE_RTP_RULES with one proper for XE_RTP_ACTIONS. Signed-off-by: Gustavo Sousa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/gt: Dump PAT table when failing to initializeLucas De Marchi1-0/+12
When failing on early initialization, one cause may be that the PAT configuration is not correct. Dump it for ease of debugging. Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pat: Add debugfs node to dump PATLucas De Marchi3-1/+211
This is useful to debug cache issues, to double check if the PAT indexes match what they were supposed to be set to from spec. v2: Add separate functions for XeHP, XeHPC and XeLPG so it correctly reads the index based on MCR/REG registers and also decodes the fields (Matt Roper) v3: Starting with XeHPC, do not translate values to human-readable formats as the main goal is to make it easy to compare the table with the spec. Also, share a single array for xelp/xehp str map (Matt Roper) Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add one more bit to encode PAT to ppgtt entriesLucas De Marchi2-0/+4
Xe2 adds one more bit to cover all the possible 32 entries. Although those entries are not used by internal kernel code paths, it's expected that userspace will make use of it. Bspec: 59510, 67095 Reviewed-by: Pallavi Mishra <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Program PAT tablesMatt Roper1-1/+91
The PAT tables become significantly more complicated on Xe2 platforms. They now control L3, L4, and coherency settings, as well as additional characteristics such as compression. Aside from the main PAT table, there's an additional register that also needs to be programmed with PAT settings for PCI Address Translation Services. Bspec: 71582 Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/tests/xe_migrate.c: Add vram to vram KUNIT testDavid Kershner1-37/+66
Add missing kunit test to migrate a bo from vram to vram Reviewed-by: Niranjana Vishwanathapura <[email protected]> Reviewed-by: "Michael J. Ruhl" <[email protected]> Signed-off-by: David Kershner <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe_migrate.c: Use DPA offset for page table entries.David Kershner1-10/+17
Device Physical Address (DPA) is the starting offset device memory. Update xe_migrate identity map base PTE entries to start at dpa_base instead of 0. The VM offset value should be 0 relative instead of DPA relative. Reviewed-by: Niranjana Vishwanathapura <[email protected]> Reviewed-by: "Michael J. Ruhl" <[email protected]> Signed-off-by: David Kershner <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Follow XeHPC for TLB invalidationLucas De Marchi1-1/+1
Register GUC_TLB_INV_CR is gone in xe2. When GuC submission is not yet enabled, make sure to follow the same path as XeHPC. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/vm: Prefer xe_assert() over XE_WARN_ON()Lucas De Marchi1-1/+2
When xelp_pte_encode_addr() was added in commit 23c8495efeed ("drm/xe/migrate: Do not hand-encode pte"), there was no xe pointer for using xe_assert(). This is not the case anymore, so prefer it over XE_WARN_ON(). Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add gt tuning for indirect stateMatt Atwood2-0/+6
Force indirect state sampler data to only be in the dynamic state pool, which is more convienent for the UMD. Behavior change mirrors similar change for i915 in commit 16fc9c08f0ec ("drm/i915: disable sampler indirect state in bindless heap") v2: split out per engine tuning into separate patch, commit message (Lucas) v3: rebase v4: Change to match render only, g.ver 1200 to 1271 (MattR) Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add infrastructure for per engine tuningMatt Atwood3-0/+15
Add the infrastructure for per engine tuning in preparation for disable indirect state. v3: Rebase v4: Fix rebasing issues Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/hwmon: fix uaf on unloadMatthew Auld1-1/+10
It doesn't look like you can mix and match devm_ and drmmm_ for a managed resource. For drmmm the resources are all tracked in drm with its own list, and there is only one devm_ resource for the entire list. If the driver itself also adds some of its own devm resources, then those will be released first. In the case of hwmon the devm_kzalloc will be freed before the drmmm_ action to destroy the mutex allocated within, leading to uaf. Since hwmon itself wants to use devm, rather use that for the mutex destroy. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/766 Signed-off-by: Matthew Auld <[email protected]> Cc: Badal Nilawar <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add missing mocs entryLucas De Marchi1-0/+2
Add index 4 so WB on both L3 and L4 can be used by userspace. Bspec: 71582 Link: https://lore.kernel.org/all/7oqovb356dx2hm5muop3xjqr4kv7m5fzjisch3vmsmxm33ygtv@eib4jielia35/ Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Remove devcoredump readout of IPEIRJosé Roberto de Souza3-6/+0
This register don't exist in gfx12+, so here dropping the readout and print in devcoredump. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix devcoredump readout of IPEHRJosé Roberto de Souza2-2/+1
It was reading (base) + 0x8c but that is not a valid register and instead it should read (base) + 0x68. So here reading the correct register and removing the wrong and duplicated. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix RING_MI_MODE label in devcoredumpJosé Roberto de Souza1-1/+1
Fix a typo in RING_MI_MODE label. Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: fix range printing for debug messagesPaulo Zanoni1-2/+2
We're already using the half-open interval notation "[A, B)", that "- 1" there makes it wrong. Also, getting rid of the "-1" makes it much easier to grep for the logs when you're looking for an address that's the end of a vma and the start of another. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/vm: use list_last_entry() to fetch last_opPaulo Zanoni1-2/+1
I would imagine that it's more efficient to fetch ops_list->prev than to walk the whole list forward. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/vm: print the correct 'keep' when printing gpuva opsPaulo Zanoni1-1/+1
Unions are cool, until they aren't. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/hwmon: Expose hwmon energy attributeBadal Nilawar4-1/+116
Expose hwmon energy attribute to show device level energy usage v2: - %s/hwm_/hwmon_/ - Convert enums to upper case v3: - %s/hwmon_/xe_hwmon - Remove gt specific hwmon attributes v4: - %s/REG_PKG_ENERGY_STATUS/REG_ENERGY_STATUS_ALL (Riana) - %s/hwmon_energy_info/xe_hwmon_energy_info (Riana) Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/hwmon: Expose input voltage attributeBadal Nilawar3-0/+67
Use Xe HWMON subsystem to display the input voltage. v2: - Rename hwm_get_vltg to hwm_get_voltage (Riana) - Use scale factor SF_VOLTAGE (Riana) v3: - %s/gt_perf_status/REG_GT_PERF_STATUS/ - Remove platform check from hwmon_get_voltage() v4: - Fix review comments (Andi) Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/hwmon: Expose card reactive critical powerBadal Nilawar4-1/+142
Expose the card reactive critical (I1) power. I1 is exposed as power1_crit in microwatts (typically for client products) or as curr1_crit in milliamperes (typically for server). v2: Move PCODE_MBOX macro to pcode file (Riana) v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2) v4: Fix review comments (Andi) Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/hwmon: Expose power attributesBadal Nilawar8-0/+445
Expose Card reactive sustained (pl1) power limit as power_max and card default power limit (tdp) as power_rated_max. v2: - Fix review comments (Riana) v3: - Use drmm_mutex_init (Matt Brost) - Print error value (Matt Brost) - Convert enums to uppercase (Matt Brost) - Avoid extra reg read in hwmon_is_visible function (Riana) - Use xe_device_assert_mem_access when applicable (Matt Brost) - Add [email protected] in Documentation (Matt Brost) v4: - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi) - %s/hwmon_reg/xe_hwmon_reg (Andi) - Fix review comments (Guenter/Andi) v5: - Fix review comments (Riana) v6: - Use drm_warn in default case (Rodrigo) - s/ENODEV/EOPNOTSUPP (Andi) Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix exec queue usage for unbindsMatthew Brost1-1/+2
Passing in a NULL exec queue to __xe_pt_unbind_vma results in the migrate exec queue being used. This is not the intent from the VM bind IOCTL, rather a NULL exec queue should use default VM exec queue. Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Leverage ComputeCS read L3 cachingBalasubramani Vivekanandan1-11/+14
On platforms that support read L3 caching, set the default mocs index in CCS RING_CMD_CTL to leverage the read caching in L3. Currently PVC and Xe2 platforms have the support. Bspec: 72161 Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Update MOCS fields in blitter instructionsHaridhar Kalvala2-17/+35
Xe2 changes or adds bits for mocs in a few BLT instructions: XY_CTRL_SURF_COPY_BLT, XY_FAST_COLOR_BLT, XY_FAST_COPY_BLT, and MEM_SET. Modify the code to deal with the new location. Unlike Xe1, the MOCS field in those instructions is only the MOCS index and not the Structure_MEMORY_OBJECT_CONTROL_STATE anymore. The pxp bit is now explicitly documented separately. Bspec: 57567,57566,57565,57562 Cc: Matt Roper <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Set tile y type in XY_FAST_COPY_BLT to Tile4Haridhar Kalvala2-1/+10
Set bits 30 and 31 of XY_FAST_COPY_BLT's dword1 for XeHP and above. Destination or source being Y-Major is selected on dword0 and there's nothing to set on dword1. According to the bspec for Xe2, "Behavior is undefined when programmed the value 0". Also for XeHP, the only value allowed in those bits is 0b11, not being possible to select "Legacy Tile-Y" anymore, only the newer Tile4. So, unconditionally set those bits for graphics IP 12.50 and above. v2: Reword commit message and extend it to graphics version >= 12.50 (Matt Roper) Bspec: 57567 Cc: Matt Roper <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Rename MEM_SET instructionHaridhar Kalvala2-5/+5
PVC_MS_* doesn't reflect the real name of the instruction. Rename it to follow the name used in the bspec. Cc: Matt Roper <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Adjust mocs field mask definitionsHaridhar Kalvala3-17/+5
Instead of using xe_mocs_index_to_value(), simply define the bitmask with the shift left applied. This will make it easier to adapt to new platforms that simply use the index. This also fixes PVC bug in emit_clear_link_copy() where the MOCS was getting shifted both by PVC_MS_MOCS_INDEX_MASK definition and by the xe_moc_index_to_value function. Bspec: 44509 Cc: Matt Roper <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Extend reserved stolen sizesLucas De Marchi2-5/+29
For xe2, besides the previous sizes, the reserved portion of stolen can also have 16MB and 32MB. Bspec: 53148 Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/tuning: Add missing engine class rules for LRC tuningMatt Roper1-4/+4
The LRC tuning settings we have today are modifying registers that are part of the RCS engine's context; they're not part of the general CSFE context that would apply to all engines. Add ENGINE_CLASS(RENDER) to the RTP rules to properly restrict these to the RCS. Bspec: 46255, 46261 Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: timeout needs to be a signed valueFei Yang1-18/+37
In xe_wait_user_fence_ioctl, the timeout is currently defined as unsigned long. That could potentially pass a negative value to the schedule_timeout() call because nsecs_to_jiffies() returns an unsigned long which gets used as signed long. [ 187.732238] schedule_timeout: wrong timeout value fffffffffffffc18 [ 187.733180] CPU: 0 PID: 792 Comm: test_thread_dim Tainted: G U 6.4.0-xe #1 [ 187.734251] Hardware name: Bochs Bochs, BIOS Bochs 01/01/2007 [ 187.735019] Call Trace: [ 187.735373] <TASK> [ 187.735687] dump_stack_lvl+0x92/0xb0 [ 187.736193] schedule_timeout+0x348/0x430 [ 187.736739] ? __might_fault+0x67/0xd0 [ 187.737255] ? check_chain_key+0x224/0x2d0 [ 187.737812] ? __pfx_schedule_timeout+0x10/0x10 [ 187.738429] ? __might_fault+0x6b/0xd0 [ 187.738946] ? __pfx_lock_release+0x10/0x10 [ 187.739512] ? __pfx_lock_release+0x10/0x10 [ 187.740080] wait_woken+0x86/0x100 [ 187.740556] xe_wait_user_fence_ioctl+0x34b/0xe00 [xe] [ 187.741281] ? __pfx_xe_wait_user_fence_ioctl+0x10/0x10 [xe] [ 187.742075] ? lock_acquire+0x169/0x3d0 [ 187.742601] ? check_chain_key+0x224/0x2d0 [ 187.743158] ? drm_dev_enter+0x9/0xe0 [drm] [ 187.743740] ? __pfx_woken_wake_function+0x10/0x10 [ 187.744388] ? drm_dev_exit+0x11/0x50 [drm] [ 187.744969] ? __pfx_lock_release+0x10/0x10 [ 187.745536] ? __might_fault+0x67/0xd0 [ 187.746052] ? check_chain_key+0x224/0x2d0 [ 187.746610] drm_ioctl_kernel+0x172/0x250 [drm] [ 187.747242] ? __pfx_xe_wait_user_fence_ioctl+0x10/0x10 [xe] [ 187.748037] ? __pfx_drm_ioctl_kernel+0x10/0x10 [drm] [ 187.748729] ? __pfx_xe_wait_user_fence_ioctl+0x10/0x10 [xe] [ 187.749524] ? __pfx_xe_wait_user_fence_ioctl+0x10/0x10 [xe] [ 187.750319] drm_ioctl+0x35e/0x620 [drm] [ 187.750871] ? __pfx_drm_ioctl+0x10/0x10 [drm] [ 187.751495] ? restore_fpregs_from_fpstate+0x99/0x140 [ 187.752172] ? __pfx_restore_fpregs_from_fpstate+0x10/0x10 [ 187.752901] ? mark_held_locks+0x24/0x90 [ 187.753438] __x64_sys_ioctl+0xb4/0xf0 [ 187.753954] do_syscall_64+0x3f/0x90 [ 187.754450] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 187.755127] RIP: 0033:0x7f4e6651aaff [ 187.755623] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 187.757995] RSP: 002b:00007fff05f37a50 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 187.758995] RAX: ffffffffffffffda RBX: 000055eca47c8130 RCX: 00007f4e6651aaff [ 187.759935] RDX: 00007fff05f37b60 RSI: 00000000c050644b RDI: 0000000000000004 [ 187.760874] RBP: 0000000000000017 R08: 0000000000000017 R09: 7fffffffffffffff [ 187.761814] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 [ 187.762753] R13: 0000000000000000 R14: 0000000000000000 R15: 00007f4e65d19ce0 [ 187.763694] </TASK> Fixes: 5572a0046857 ("drm/xe: Use nanoseconds instead of jiffies in uapi for user fence") Signed-off-by: Fei Yang <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Zbigniew Kempczyński <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: set PTE_AE for all platforms supporting itFei Yang1-1/+1
Atomic access is supported by PVC, and became a common feature for all platforms starting from Xe2. To enable that XE_VMA_ATOMIC_PTE_BIT needs to be set, then pte encode will eventually set PTE_AE for devmem. Signed-off-by: Fei Yang <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add a missing mutex_destroy to xe_ttm_vram_mgrBommithi Sakeena1-0/+2
Ensure that the mutex is destroyed at fini function. Cc: Maarten Lankhorst <[email protected]> Signed-off-by: Bommithi Sakeena <[email protected]> Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Ensure mutex are destroyedBommithi Sakeena4-2/+6
Add missing mutex_destroy calls to fini functions or convert to drmm_mutex_init where fini function is not available. Cc: Matthew Brost <[email protected]> Signed-off-by: Bommithi Sakeena <[email protected]> Reviewed-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
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