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2016-02-10drm/amd/powerplay: Use correct clock in cz_apply_state_adjust_rulesEric Yang1-2/+2
Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Eagle Yeh <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: get real display device num by cgs interfaceRex Zhu1-9/+16
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: Use engine clock limit calculated by dalVitaly Prosyak1-3/+3
Use min required system clock calculated by dal Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: Make declarations of functions exposed to DAL type-safe.David Rokhvarg2-14/+16
Signed-off-by: David Rokhvarg <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: implement functions in carrizo for DAL.Rex Zhu1-11/+115
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: export interface to DAL.Rex Zhu5-21/+251
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: change struct name.Rex Zhu6-8/+8
amd_pp_dal_clock_info to amd_pp_simple_clock_info. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd: Adding IVSRC register headersHarry Wentland1-0/+102
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: Move MMIO flip out of spinlocked regionVitaly Prosyak1-3/+3
Prior actual MMIO flip we need to acquire DAL mutex to guard our target state which get modified on reset mode. Assign page flip status before actual flip to handle the possible race condition with interrupt. Signed-off-by: Vitaly Prosyak <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: Don't crash system if we can't get crtcHarry Wentland1-0/+6
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-11drm/msm: add max-freq gpu param to uapiRob Clark2-0/+4
We need this in userspace for interpreting some of the perf ctrs. Note possibly not quite sufficient if we had some frequency mgmt approach other than race-to-idle. Not really sure what the best thing to do if we did. Although displaying results as a percentage of max frequence seems sensible(ish) if we did. Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2016-02-10drm/amdgpu: move sync into job objectChristian König13-38/+46
No need to keep that for every IB. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: send VCE IB tests directly to the ring againChristian König2-8/+22
We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: send UVD IB tests directly to the ring againChristian König5-15/+25
We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: rename amdgpu_sched.c to amdgpu_job.cChristian König2-5/+5
That's probably a better matching name. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup in kernel job submissionChristian König7-204/+111
Add a job_alloc_with_ib helper and proper job submission. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: send SDMA/GFX IB tests directly to the ring againChristian König5-18/+6
There is no point in sending them through the scheduler. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: directly return fence from ib_scheduleChristian König3-8/+12
Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: move ring from IBs into jobChristian König14-44/+45
We can't submit to multiple rings at the same time anyway. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: make pad_ib a ring function v3Christian König14-18/+41
The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup user fence handling in the CSChristian König2-17/+13
Don't keep that around twice. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: add proper job alloc/free functionsChristian König6-55/+69
And use them in the CS instead of allocating IBs and jobs separately. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: fix num_ibs checkChristian König1-11/+5
Specifying no IBs on command submission is invalid, stop crashing badly when somebody tries it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove AMDGPU_NUM_SYNCSChristian König2-4/+1
Just a leftover from semaphores. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove adev and fence from amdgpu_sync_freeChristian König3-8/+3
Just leftovers from the semaphores. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: check userptrs mm earlierChristian König7-15/+27
Instead of when we try to bind it check the usermm when we try to use it in the IOCTLs. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
2016-02-10drm/radeon: Avoid double gpu reset by adding a timeout on IB ring tests.Matthew Dawson9-23/+89
When the radeon driver resets a gpu, it attempts to test whether all the rings can successfully handle an IB. If these rings fail to respond, the process will wait forever. Another gpu reset can't happen at this point, as the current reset holds a lock required to do so. Instead, make all the IB tests run with a timeout, so the system can attempt to recover in this case. While this doesn't fix the underlying issue with card resets failing, it gives the system a higher chance of recovering. These timeouts have been confirmed to help both a Tathi and Hawaii card recover after a gpu reset. This also adds a new function, radeon_fence_wait_timeout, that behaves like fence_wait_timeout. It is used instead of fence_wait_timeout as it continues to work during a reset. radeon_fence_wait is changed to be implemented using this function. V2: - Changed the timeout to 1s, as the default 10s from radeon_wait_timeout was too long. A timeout of 100ms was tested and found to be too short. - Changed radeon_fence_wait_timeout to behave more like fence_wait_timeout. Reviewed-by: Christian König <[email protected]> Signed-off-by: Matthew Dawson <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu/gfx: minor code cleanupAlex Deucher2-28/+2
Drop needless function wrapper. Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: separate pushing CS to schedulerChristian König1-46/+50
Move that out of the main IOCTL function. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: add amdgpu_set_ib_value helper (v2)Christian König3-8/+15
And use it in UVD/VCE command patching. v2: squash in Christian's fix Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: fix size estimation for clear IBChristian König1-2/+2
We only need a few dw here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu/smu: skip SMC ucode loading on SR-IOV capable boards (v2)Alex Deucher3-0/+18
VBIOS does this for us in asic_init. v2: update iceland as well Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu/gmc8: skip MC ucode loading on SR-IOV capable boardsAlex Deucher1-0/+6
VBIOS does this for us in asic_init. Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: always repost cards that support SR-IOVAlex Deucher1-1/+2
Generally a good idea between VM sessions. We need a way to detect VM pass-through in general and always run asic_init in that case. Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: track whether the asic supports SR-IOVAlex Deucher2-0/+11
Required to make desicions about certain code pathes. Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: add check for atombios GPU virtualization tableAlex Deucher2-0/+15
This table is found on boards that support SR-IOV. This will be used to determine if the board supports SR-IOV and allow the driver to take specific action in certain cases. Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove unused functionAlex Deucher2-26/+0
amdgpu_boot_test_post_card() is not used anywhere. Probably a leftover from the original port from radeon. Reviewed-by: Christian König <[email protected]> Reviewed-by: Tom St Denis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd: add pm domain for ACP IP sub blocksMaruthi Srinivas Bayyavarapu3-1/+207
ACP IP have internal DMA controller, DW I2S controller and DSPs as separate power tiles. DMA and I2S devices are added to generic pm domain, so that entire IP can be powered off/on at appropriate times. Unused DSPs are made to be powered off though they are powered on during ACP pm domain power on sequence. Signed-off-by: Maruthi Bayyavarapu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd: add ACP driver supportMaruthi Bayyavarapu11-1/+480
This adds the ACP (Audio CoProcessor) IP driver and wires it up to the amdgpu driver. The ACP block provides the DMA engine for i2s based ALSA driver. This is required for audio on APUs that utilize an i2s codec. Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Maruthi Bayyavarapu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Murali Krishna Vemuri <[email protected]> Signed-off-by: Maruthi Bayyavarapu <[email protected]> Signed-off-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove power of two limit for vramlimitChristian König1-6/+0
That works with other values as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: optimize amdgpu_vm_update_ptes a bitChristian König1-20/+20
Don't calculate the end address multiple times. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup comments in VM codeChristian König1-21/+11
Neither the global nor the local mutex exists any more and amdgpu doesn't support cayman. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: optimize VM fencingChristian König1-28/+22
No need to fence every page table, just the page directory is enough. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: split VM mappings into smaller operations (v3)Christian König1-27/+77
If we can't copy entries from the GTT or fill them with one command split up the mapping operation into multiple ones. v2: agd: rebase on upstream v3: squash in Christian's fix Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: use BOs GART instance for mapping addresses v4Christian König1-46/+68
That allows the VM code to use GART BOs from other driver instances. v2: don't use copy optimization for foreign GARTs, that won't work. v3: some more comment cleanups v4: agd: rebase on upstream Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: move more logic into amdgpu_vm_map_gart v3Christian König5-42/+33
No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove nonsense IB size checksChristian König1-8/+0
Those are just leftovers from the time we wrote the VM updates directly to the ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: use WARN_ON_ONCE instead of BUG_ON in the SAChristian König1-2/+5
Crashing the system doesn't helps at all. Also properly return -EINVAL if size or alignment are outside valid ranges. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: drop a dummy wakeup schedulerMonk Liu1-1/+9
since the dependency job is also scheduled by the same scheduler with the job depended on it, no need to call wake up scheduler when the dep is scheduled. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd: add dce8 enum register headerAlex Deucher1-0/+1117
This adds the DCE8 enum header. Acked-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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