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2020-02-07Merge tag 'amd-drm-next-5.6-2020-02-05' of ↵Dave Airlie102-869/+4337
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.6-2020-02-05: amdgpu: - EDC fixes for Arcturus - GDDR6 memory training fixe - Fix for reading gfx clockgating registers while in GFXOFF state - i2c freq fixes - Misc display fixes - TLB invalidation fix when using semaphores - VCN 2.5 instancing fixes - Switch raven1 gfxoff to a blacklist - Coreboot workaround for KV/KB - Root cause dongle fixes for display and revert workaround - Enable GPU reset for renoir and navi - Navi overclocking fixes - Fix up confusing warnings in display clock validation on raven amdkfd: - SDMA fix radeon: - Misc LUT fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-07Merge branch 'linux-5.6' of git://github.com/skeggsb/linux into drm-nextDave Airlie5-10/+50
Just a couple of fixes to Volta/Turing modesetting on some systems. Signed-off-by: Dave Airlie <[email protected]> From: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv7=eP+Ai1ouoMyYyo1xMF0pTQki=owYjJkS=NpvKQd1fg@mail.gmail.com
2020-02-07Merge tag 'drm/tegra/for-5.6-rc1-fixes' of ↵Dave Airlie5-63/+123
git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Fixes for v5.6-rc1 These are a couple of quick fixes for regressions that were found during the first two weeks of the merge window. Signed-off-by: Dave Airlie <[email protected]> From: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-07drm/i915/selftests: drop igt_ppgtt_exhaust_hugeMatthew Auld1-102/+0
We already have tests that exhaustively exercise the most interesting page-size combinations, along with tests that offer randomisation, and so we should already be testing objects(local, system) with a varying mix of page-sizes, which leaves igt_ppgtt_exhaust_huge providing not much in terms of extra coverage. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-06drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing ↵José Roberto de Souza1-4/+7
DDI select TGL is suffering of timeouts and fifo underruns when disabling transcoder in MST mode, this is fixed by set TRANS_DDI_MODE_SELECT to 0(HDMI mode) when clearing DDI select. Although BSpec disable sequence don't require this step, it is a harmless change and it is also done by Windows driver. Anyhow HW team was notified about that but it can take some time to documentation to be updated. A case that always lead to those issues is: - do a modeset enabling pipe A and pipe B in the same MST stream leaving A as master - disable pipe A, promote B as master doing a full modeset in A - enable pipe A, changing the master transcoder back to A(doing a full modeset in B) - Pow: underruns and timeouts The transcoders involved will only work again when complete disabled and their power wells turned off causing a reset in their registers. v2: Setting TRANS_DDI_MODE_SELECT to default when clearing DDI select not anymore when disabling TRANS_DDI, both work but this one looks more safe. (Ville comment) Cc: Ville Syrjälä <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-06drm/i915/gt: Set the PP_DIR registers upon enabling ring submissionChris Wilson1-14/+26
Always prime the page table registers before starting the ring. Even though we will update these to the per-context page tables during dispatch, it is prudent to ensure that the registers always point to a valid PD. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-06gpu: host1x: Set DMA direction only for DMA-mapped buffer objectsThierry Reding1-1/+1
The DMA direction is only used by the DMA API, so there is no use in setting it when a buffer object isn't mapped with the DMA API. Signed-off-by: Thierry Reding <[email protected]> Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]>
2020-02-06drm/tegra: Reuse IOVA mapping where possibleThierry Reding3-23/+63
This partially reverts the DMA API support that was recently merged because it was causing performance regressions on older Tegra devices. Unfortunately, the cache maintenance performed by dma_map_sg() and dma_unmap_sg() causes performance to drop by a factor of 10. The right solution for this would be to cache mappings for buffers per consumer device, but that's a bit involved. Instead, we simply revert to the old behaviour of sharing IOVA mappings when we know that devices can do so (i.e. they share the same IOMMU domain). Cc: <[email protected]> # v5.5 Reported-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]>
2020-02-06drm/tegra: Relax IOMMU usage criteria on old TegraThierry Reding1-17/+32
Older Tegra devices only allow addressing 32 bits of memory, so whether or not the host1x is attached to an IOMMU doesn't matter. host1x IOMMU attachment is only needed on devices that can address memory beyond the 32-bit boundary and where the host1x doesn't support the wide GATHER opcode that allows it to access buffers at higher addresses. Cc: <[email protected]> # v5.5 Signed-off-by: Thierry Reding <[email protected]> Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]>
2020-02-05drm/i915: Flush execution tasklets before checking request statusChris Wilson1-1/+2
Rather than flushing the submission tasklets just before we sleep, flush before we check the request status. Ideally this gives us a moment to process the tasklets after sleeping just before we timeout. v2: Compromise by pushing the flush prior to the timeout, but after the check on completion so that we do not further delay the ready client. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Mark i915.reset as unsignedChris Wilson1-1/+1
We have been using '-1' to mean the maximum i915.reset level in the belief that it was unsigned... This turns out to have been a grave error, and instead of setting the default reset mechanism in igt, we have been disabling reset! Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Correctly map DBUF slices to pipesStanislav Lisovskiy1-19/+366
Added proper DBuf slice mapping to correspondent pipes, depending on pipe configuration as stated in BSpec. v2: - Remove unneeded braces - Stop using macro for DBuf assignments as it seems to reduce readability. v3: Start using enabled slices mask in dev_priv v4: Renamed "enabled_slices" used in dev_priv to "enabled_dbuf_slices_mask"(Matt Roper) v5: - Removed redundant parameters from intel_get_ddb_size function.(Matt Roper) - Made i915_possible_dbuf_slices static(Matt Roper) - Renamed total_width into total_width_in_range so that it now reflects that this is not a total pipe width but the one in current dbuf slice allowed range for pipe.(Matt Roper) - Removed 4th pipe for ICL in DBuf assignment table(Matt Roper) - Fixed wrong DBuf slice in DBuf table for TGL (Matt Roper) - Added comment regarding why we currently not using pipe ratio for DBuf assignment for ICL v6: - Changed u32 to unsigned int in icl_get_first_dbuf_slice_offset function signature (Ville Syrjälä) - Changed also u32 to u8 in dbuf slice mask structure (Ville Syrjälä) - Switched from DBUF_S1_BIT to enum + explicit BIT(DBUF_S1) access(Ville Syrjälä) - Switched to named initializers in DBuf assignment arrays(Ville Syrjälä) - DBuf assignment arrays now use autogeneration tool from https://patchwork.freedesktop.org/series/70493/ to avoid typos. - Renamed i915_find_pipe_conf to *_compute_dbuf_slices (Ville Syrjälä) - Changed platforms ordering in skl_compute_dbuf_slices to be from newest to oldest(Ville Syrjälä) v7: - Now ORing assigned DBuf slice config always with DBUF_S1 because slice 1 has to be constantly powered on. (Ville Syrjälä) v8: - Added pipe_name for neater printing(Ville Syrjälä) - Renamed width_before_pipe to width_before_pipe_in_range, to better reflect that now all the calculations are happening inside DBuf range allowed by current pipe configuration mask (Ville Syrjälä) - Shortened FIXME comment message, regarding constant ORing with DBUF_S1(Ville Syrjälä) - Added .dbuf_mask named initializer to pipe assignment array (Ville Syrjälä) - Edited pipe assignment array to use only single DBuf slice for gen11 single pipe configurations, until "pipe ratio" thing is finally sorted out(Ville Syrjälä) - Removed unused parameter crtc_state for now(Ville Syrjälä) from icl/tgl_compute_dbuf_slices function Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Manipulate DBuf slices properlyStanislav Lisovskiy8-118/+72
Start manipulating DBuf slices as a mask, but not as a total number, as current approach doesn't give us full control on all combinations of slices, which we might need(like enabling S2 only can't enabled by setting enabled_slices=1). Removed wrong code from intel_get_ddb_size as it doesn't match to BSpec. For now still just use DBuf slice until proper algorithm is implemented. Other minor code refactoring to get prepared for major DBuf assignment changes landed: - As now enabled slices contain a mask we still need some value which should reflect how much DBuf slices are supported by the platform, now device info contains num_supported_dbuf_slices. - Removed unneeded assertion as we are now manipulating slices in a more proper way. v2: Start using enabled_slices in dev_priv v3: "enabled_slices" is now "enabled_dbuf_slices_mask", as this now sits in dev_priv independently. v4: - Fixed debug print formatting to hex(Matt Roper) - Optimized dbuf slice updates to be used only if slice union is different from current conf(Matt Roper) - Fixed some functions to be static(Matt Roper) - Created a parameterized version for DBUF_CTL to simplify DBuf programming cycle(Matt Roper) - Removed unrequred field from GEN10_FEATURES(Matt Roper) v5: - Removed redundant programming dbuf slices helper(Ville Syrjälä) - Started to use parameterized loop for hw readout to get slices (Ville Syrjälä) - Added back assertion checking amount of DBUF slices enabled after DC states 5/6 transition, also added new assertion as starting from ICL DMC seems to restore the last DBuf power state set, rather than power up all dbuf slices as assertion was previously expecting(Ville Syrjälä) v6: - Now using enum for DBuf slices in this patch (Ville Syrjälä) - Removed gen11_assert_dbuf_enabled and put gen9_assert_dbuf_enabled back, as we really need to have a single unified assert here however currently enabling always slice 1 is enforced by BSpec, so we will have to OR enabled slices mask with 1 in order to be consistent with BSpec, that way we can unify that assertion and against the actual state from the driver, but not some hardcoded value.(concluded with Ville) - Remove parameterized DBUF_CTL version, to extract it to another patch.(Ville Syrjälä) v7: - Removed unneeded hardcoded return value for older gens from intel_enabled_dbuf_slices_mask - this now is handled in a unified manner since device info anyway returns max dbuf slices as 1 for older platforms(Matthew Roper) - Now using INTEL_INFO(dev_priv)->num_supported_dbuf_slices instead of intel_dbuf_max_slices function as it is trivial(Matthew Roper) v8: - Fixed icl_dbuf_disable to disable all dbufs still(Ville Syrjälä) v9: - Renamed _DBUF_CTL_S to DBUF_CTL_S(Ville Syrjälä) - Now using power_domain mutex to protect from race condition, which can occur because intel_dbuf_slices_update might be running in parallel to gen9_dc_off_power_well_enable being called from intel_dp_detect for instance, which causes assertion triggered by race condition, as gen9_assert_dbuf_enabled might preempt this when registers were already updated, while dev_priv was not. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Introduce parameterized DBUF_CTLStanislav Lisovskiy5-24/+31
Now start using parameterized DBUF_CTL instead of hardcoded, this would allow shorter access functions when reading or storing entire state. Tried to implement it in a MMIO_PIPE manner, however DBUF_CTL1 address is higher than DBUF_CTL2, which implies that we have to now subtract from base rather than add. v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR macros. Started to use _PICK construct as suggested by Matt Roper. v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice" in macro(Ville Syrjälä) - Introduced enum for enumerating DBUF slices(Ville Syrjälä) Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Update dbuf slices only with full modesetStanislav Lisovskiy1-2/+4
During full modeset, global state(i.e dev_priv) is protected by locking the crtcs in state, otherwise global state is not serialized. Also if it is not a full modeset, we anyway don't need to change DBuf slice configuration as Pipe configuration doesn't change. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Move dbuf slice update to proper placeStanislav Lisovskiy1-9/+28
Current DBuf slices update wasn't done in proper place, especially its "post" part, which should disable those only once vblank had passed and all other changes are committed. v2: Fix to use dev_priv and intel_atomic_state instead of skl_ddb_values (to be nuked in Villes patch) v3: Renamed "enabled_slices" to "enabled_dbuf_slices_num" (Matt Roper) v4: - Rebase against drm-tip. - Move post_update closer to optimize_watermarks, to prevent unneeded noise from underrun reporting (Ville Syrjälä) Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915: Remove skl_ddl_allocation structStanislav Lisovskiy6-51/+38
Current consensus that it is redundant as we already have skl_ddb_values struct out there, also this struct contains only single member which makes it unnecessary. v2: As dirty_pipes soon going to be nuked away from skl_ddb_values, evacuating enabled_slices to safer in dev_priv. v3: Changed "enabled_slices" to be "enabled_dbuf_slices_num" (Matt Roper) v4: - Wrapped the line getting number of dbuf slices(Matt Roper) - Removed indeed redundant skl_ddb_values declaration(Matt Roper) Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915/display: Be explicit in handling the preallocated vmaChris Wilson5-124/+101
As only the display codes tries to pin its preallocated framebuffer into an exact location in the GGTT, remove the convenience function and make the pin management explicit in the display code. Then throughout the display management, we track the framebuffer and its plane->vma; with less single purpose code and ready for first class i915_vma. In doing so, this should fix the BUG_ON(vma->pages) on fi-kbl-soraka. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915/display: Explicitly cleanup initial_plane_configChris Wilson1-4/+17
I am about to stuff more objects into the plane_config and would like to have it clean up after itself. Move the current framebuffer release into a common function so it can be extended with the new object with relative ease. Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-05drm/i915/hdcp: move update pipe code to hdcpJani Nikula3-33/+46
The DDI encoder code shouln't have to know about the guts of HDCP. Abstract the pipe update code to a new intel_hdcp_update_pipe() in intel_hdcp.c. No functional changes. Cc: Anshuman Gupta <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/amd/dm/mst: Ignore payload update failuresLyude Paul1-9/+4
Disabling a display on MST can potentially happen after the entire MST topology has been removed, which means that we can't communicate with the topology at all in this scenario. Likewise, this also means that we can't properly update payloads on the topology and as such, it's a good idea to ignore payload update failures when disabling displays. Currently, amdgpu makes the mistake of halting the payload update process when any payload update failures occur, resulting in leaving DC's local copies of the payload tables out of date. This ends up causing problems with hotplugging MST topologies, and causes modesets on the second hotplug to fail like so: [drm] Failed to updateMST allocation table forpipe idx:1 ------------[ cut here ]------------ WARNING: CPU: 5 PID: 1511 at drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2677 update_mst_stream_alloc_table+0x11e/0x130 [amdgpu] Modules linked in: cdc_ether usbnet fuse xt_conntrack nf_conntrack nf_defrag_ipv6 libcrc32c nf_defrag_ipv4 ipt_REJECT nf_reject_ipv4 nft_counter nft_compat nf_tables nfnetlink tun bridge stp llc sunrpc vfat fat wmi_bmof uvcvideo snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi videobuf2_vmalloc snd_hda_intel videobuf2_memops videobuf2_v4l2 snd_intel_dspcfg videobuf2_common crct10dif_pclmul snd_hda_codec videodev crc32_pclmul snd_hwdep snd_hda_core ghash_clmulni_intel snd_seq mc joydev pcspkr snd_seq_device snd_pcm sp5100_tco k10temp i2c_piix4 snd_timer thinkpad_acpi ledtrig_audio snd wmi soundcore video i2c_scmi acpi_cpufreq ip_tables amdgpu(O) rtsx_pci_sdmmc amd_iommu_v2 gpu_sched mmc_core i2c_algo_bit ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops cec drm crc32c_intel serio_raw hid_multitouch r8152 mii nvme r8169 nvme_core rtsx_pci pinctrl_amd CPU: 5 PID: 1511 Comm: gnome-shell Tainted: G O 5.5.0-rc7Lyude-Test+ #4 Hardware name: LENOVO FA495SIT26/FA495SIT26, BIOS R12ET22W(0.22 ) 01/31/2019 RIP: 0010:update_mst_stream_alloc_table+0x11e/0x130 [amdgpu] Code: 28 00 00 00 75 2b 48 8d 65 e0 5b 41 5c 41 5d 41 5e 5d c3 0f b6 06 49 89 1c 24 41 88 44 24 08 0f b6 46 01 41 88 44 24 09 eb 93 <0f> 0b e9 2f ff ff ff e8 a6 82 a3 c2 66 0f 1f 44 00 00 0f 1f 44 00 RSP: 0018:ffffac428127f5b0 EFLAGS: 00010202 RAX: 0000000000000002 RBX: ffff8d1e166eee80 RCX: 0000000000000000 RDX: ffffac428127f668 RSI: ffff8d1e166eee80 RDI: ffffac428127f610 RBP: ffffac428127f640 R08: ffffffffc03d94a8 R09: 0000000000000000 R10: ffff8d1e24b02000 R11: ffffac428127f5b0 R12: ffff8d1e1b83d000 R13: ffff8d1e1bea0b08 R14: 0000000000000002 R15: 0000000000000002 FS: 00007fab23ffcd80(0000) GS:ffff8d1e28b40000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f151f1711e8 CR3: 00000005997c0000 CR4: 00000000003406e0 Call Trace: ? mutex_lock+0xe/0x30 dc_link_allocate_mst_payload+0x9a/0x210 [amdgpu] ? dm_read_reg_func+0x39/0xb0 [amdgpu] ? core_link_enable_stream+0x656/0x730 [amdgpu] core_link_enable_stream+0x656/0x730 [amdgpu] dce110_apply_ctx_to_hw+0x58e/0x5d0 [amdgpu] ? dcn10_verify_allow_pstate_change_high+0x1d/0x280 [amdgpu] ? dcn10_wait_for_mpcc_disconnect+0x3c/0x130 [amdgpu] dc_commit_state+0x292/0x770 [amdgpu] ? add_timer+0x101/0x1f0 ? ttm_bo_put+0x1a1/0x2f0 [ttm] amdgpu_dm_atomic_commit_tail+0xb59/0x1ff0 [amdgpu] ? amdgpu_move_blit.constprop.0+0xb8/0x1f0 [amdgpu] ? amdgpu_bo_move+0x16d/0x2b0 [amdgpu] ? ttm_bo_handle_move_mem+0x118/0x570 [ttm] ? ttm_bo_validate+0x134/0x150 [ttm] ? dm_plane_helper_prepare_fb+0x1b9/0x2a0 [amdgpu] ? _cond_resched+0x15/0x30 ? wait_for_completion_timeout+0x38/0x160 ? _cond_resched+0x15/0x30 ? wait_for_completion_interruptible+0x33/0x190 commit_tail+0x94/0x130 [drm_kms_helper] drm_atomic_helper_commit+0x113/0x140 [drm_kms_helper] drm_atomic_helper_set_config+0x70/0xb0 [drm_kms_helper] drm_mode_setcrtc+0x194/0x6a0 [drm] ? _cond_resched+0x15/0x30 ? mutex_lock+0xe/0x30 ? drm_mode_getcrtc+0x180/0x180 [drm] drm_ioctl_kernel+0xaa/0xf0 [drm] drm_ioctl+0x208/0x390 [drm] ? drm_mode_getcrtc+0x180/0x180 [drm] amdgpu_drm_ioctl+0x49/0x80 [amdgpu] do_vfs_ioctl+0x458/0x6d0 ksys_ioctl+0x5e/0x90 __x64_sys_ioctl+0x16/0x20 do_syscall_64+0x55/0x1b0 entry_SYSCALL_64_after_hwframe+0x44/0xa9 RIP: 0033:0x7fab2121f87b Code: 0f 1e fa 48 8b 05 0d 96 2c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d dd 95 2c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffd045f9068 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00007ffd045f90a0 RCX: 00007fab2121f87b RDX: 00007ffd045f90a0 RSI: 00000000c06864a2 RDI: 000000000000000b RBP: 00007ffd045f90a0 R08: 0000000000000000 R09: 000055dbd2985d10 R10: 000055dbd2196280 R11: 0000000000000246 R12: 00000000c06864a2 R13: 000000000000000b R14: 0000000000000000 R15: 000055dbd2196280 ---[ end trace 6ea888c24d2059cd ]--- Note as well, I have only been able to reproduce this on setups with 2 MST displays. Changes since v1: * Don't return false when part 1 or part 2 of updating the payloads fails, we don't want to abort at any step of the process even if things fail Reviewed-by: Mikita Lipski <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Acked-by: Harry Wentland <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amdgpu: update default voltage for boot od table for navi1xAlex Deucher1-1/+8
It needed to be updated as well so it will show the proper values if you reset to the defaults. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/i915/gt: Fix rc6 on IvybridgeChris Wilson1-4/+1
The current rc6 threshold is larger than the evaluation interval on Ivybridge; it never enters rc6. Remove the special casing so it behaves like the other gen6/gen7, and we see rc6 residencies before we manually park the system. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1114 Testcase: igt/i915_pm_rc6_residency/rc6-idle #ivb Signed-off-by: Chris Wilson <[email protected]> Cc: Andi Shyti <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915: Sprinkle missing commasVille Syrjälä1-9/+9
Add the missing comma after the last initialized element of the hpd[] arrays. Best not give people bad ideas. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2020-02-04drm/i915/dvo: Mark TMDS DVO connectors as polledVille Syrjälä1-0/+2
All the TMDS DVO chips have a sensible looking .detect(). Let's poll them. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Jani Nikula <[email protected]>
2020-02-04drm/i915: Mark ns2501 as LVDS without a fixed modeVille Syrjälä1-5/+8
ns2501 has a builtin scaler so it doesn't need a fixed mode, but let's still mark it as LVDS instead of TMDS/DVI to make life less confusing. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2020-02-04drm/i915/crt: Configure connector->polled and encoder->hpd_pin consistentlyVille Syrjälä1-8/+2
Let's make sure encoder->hpd_pin and connector->polled are mirror images of each other (when we want to use polling). The other potentially polled connectors (sdvo and tv) already get this right. Also nuke the redundant force_hotplug_required initialization (the thing is kzalloc()ed). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2020-02-04drm/i915: Introduce intel_connector_hpd_pin()Ville Syrjälä1-22/+28
Simplify the hotplug code connector->encoder->hpd_pin handling by introducing a helper for exactly this purpose. In the helper we can neatly deal with the potential lack of an attached encoder on fresh MST connectors leaving the rest of the hpd code oblivious to such details. Cc: Lyude Paul <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2020-02-04drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_voltageAlex Deucher1-3/+5
Cull out 0 clocks to avoid a warning in DC. Bug: https://gitlab.freedesktop.org/drm/amd/issues/963 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latencyAlex Deucher1-6/+9
Only send non-0 clocks to DC for validation. This mirrors what the windows driver does. Bug: https://gitlab.freedesktop.org/drm/amd/issues/963 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c (v2)Alex Deucher1-11/+23
We might get different numbers of clocks from powerplay depending on what the OEM has populated. v2: add assert for at least one level Bug: https://gitlab.freedesktop.org/drm/amd/issues/963 Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amdgpu: fetch default VDDC curve voltages (v2)Alex Deucher1-1/+49
Ask the SMU for the default VDDC curve voltage values. This properly reports the VDDC values in the OD interface. v2: only update if the original values are 0 Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.5.x
2020-02-04drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables (v2)Matt Coffin4-20/+22
Previously, the syfs functionality for restoring the default powerplay table was sourcing it's information from the currently-staged powerplay table. This patch adds a step to cache the first overdrive table that we see on boot, so that it can be used later to "restore" the powerplay table v2: sqaush my original with Matt's fix Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Matt Coffin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.5.x
2020-02-04drm/amdgpu/navi10: add OD_RANGE for navi overclockingAlex Deucher1-0/+59
So users can see the range of valid values. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.5.x
2020-02-04drm/amdgpu/navi: fix index for OD MCLKAlex Deucher1-1/+1
You can only adjust the max mclk, not the min. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.5.x
2020-02-04drm/amd/display: Fix HW/SW state mismatchBhawanpreet Lakha1-0/+19
[Why] When we disable a connector we don't explicitly remove it from the module so the display is still cached(SW) in the hdcp_module. SST: no issues because we can only have 1 display per link MST: We have x displays per link, now if we disable 1 we don't remove it from the module so the module has x display cached(SW). If we try to enable HDCP, psp verification will fail because we are reporting x displays while the HW only has x-1 display enabled [How] Check the callback for when we disable stream and call remove display. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amd/display: Fix a typo when computing dsc configurationMikita Lipski1-1/+1
[why] Remove a backslash symbol accidentally left in increase bpp function when computing mst dsc configuration. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Zhan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amd/powerplay: fix navi10 system intermittent reboot issue V2Evan Quan6-1/+86
This workaround is needed only for Navi10 12 Gbps SKUs. V2: added SMU firmware version guard Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-02-04drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS modeYong Zhao1-4/+6
The sdma_queue_count increment should be done before execute_queues_cpsch(), which calls pm_calc_rlib_size() where sdma_queue_count is used to calculate whether over_subscription is triggered. With the previous code, when a SDMA queue is created, compute_queue_count in pm_calc_rlib_size() is one more than the actual compute queue number, because the queue_count has been incremented while sdma_queue_count has not. This patch fixes that. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/amd/display: Only enable cursor on pipes that need itNicholas Kazlauskas1-0/+30
[Why] In current code we're essentially drawing the cursor on every pipe that contains it. This only works when the planes have the same scaling for src to dest rect, otherwise we'll get "double cursor" where one cursor is incorrectly filtered and offset from the real position. [How] Without dedicated cursor planes on DCN we require at least one pipe that matches the scaling of the current timing. This is an optimization and workaround for the most common case where the top-most plane is not scaled but the bottom-most plane is scaled. Whenever a pipe has a parent pipe in the blending tree whose recout fully contains the current pipe we can disable the pipe. This only applies when the pipe is actually visible of course. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-04drm/i915: Wean off drm_pci_alloc/drm_pci_freeChris Wilson4-56/+55
drm_pci_alloc and drm_pci_free are just very thin wrappers around dma_alloc_coherent, with a note that we should be removing them. Furthermore since commit de09d31dd38a50fdce106c15abd68432eebbd014 Author: Kirill A. Shutemov <[email protected]> Date: Fri Jan 15 16:51:42 2016 -0800 page-flags: define PG_reserved behavior on compound pages As far as I can see there's no users of PG_reserved on compound pages. Let's use PF_NO_COMPOUND here. drm_pci_alloc has been declared broken since it mixes GFP_COMP and SetPageReserved. Avoid this conflict by weaning ourselves off using the abstraction and using the dma functions directly. Reported-by: Taketo Kabe Closes: https://gitlab.freedesktop.org/drm/intel/issues/1027 Fixes: de09d31dd38a ("page-flags: define PG_reserved behavior on compound pages") Signed-off-by: Chris Wilson <[email protected]> Cc: <[email protected]> # v4.5+ Reviewed-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/gt: Pull sseu context updates under gtChris Wilson4-85/+102
Lift the routines to emit a request to update the SSEU on the intel_context out of i915_gem_context. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/selftest: Ensure string fits within name[]Chris Wilson1-1/+1
Shrink the strncpy bounds to ensure the NUL-terminator can fit within the embedded array: In file included from drivers/gpu/drm/i915/gem/i915_gem_context.c:2475: drivers/gpu/drm/i915/gem/selftests/mock_context.c: In function ‘mock_context’: drivers/gpu/drm/i915/gem/selftests/mock_context.c:40:3: error: ‘strncpy’ specified bound 24 equals destination size [-Werror=stringop-truncation] 40 | strncpy(ctx->name, name, sizeof(ctx->name)); Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/selftests: Add a simple rollover test for the kernel contextChris Wilson1-0/+187
Exercise the seqno wrap paths on the kernel context to provide a small amount of sanity checking and ensure that they are visible to lockdep. Signed-off-by: Chris Wilson <[email protected]> Cc: Maarten Lankhorst <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/display: Defer application of initial chv_phy_controlChris Wilson1-4/+10
To write to the DISPLAY_PHY_CONTROL requires holding the powerwells, which during early resume we have not yet acquired until later in intel_display_power_init_hw(). So compute the initial chv_phy_control, but leave the HW unset until we first acquire the powerwell. <7> [120.055984] i915 0000:00:02.0: [drm:intel_power_domains_init_hw [i915]] rawclk rate: 200000 kHz <4> [120.056381] ------------[ cut here ]------------ <4> [120.056621] i915 0000:00:02.0: Unclaimed write to register 0x1e0100 <4> [120.056924] WARNING: CPU: 1 PID: 164 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.056935] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl btbcm btintel i915 bluetooth coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg snd_hda_codec ghash_clmulni_intel snd_hwdep ecdh_generic ecc snd_hda_core r8169 snd_pcm lpc_ich realtek pinctrl_cherryview i2c_designware_pci prime_numbers <4> [120.057027] CPU: 1 PID: 164 Comm: kworker/u4:3 Tainted: G U 5.5.0-CI-CI_DRM_7854+ #1 <4> [120.057038] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0055.2016.0812.1130 08/12/2016 <4> [120.057058] Workqueue: events_unbound async_run_entry_fn <4> [120.057275] RIP: 0010:__unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.057289] Code: 48 8b 78 18 48 8b 5f 50 48 85 db 74 2d e8 1f a0 3f e1 45 89 e8 48 89 e9 48 89 da 48 89 c6 48 c7 c7 00 8c 48 a0 e8 67 82 df e0 <0f> 0b 83 2d ce e2 2b 00 01 5b 5d 41 5c 41 5d c3 48 8b 1f eb ce 66 <4> [120.057301] RSP: 0018:ffffc90000bcfd08 EFLAGS: 00010082 <4> [120.057315] RAX: 0000000000000000 RBX: ffff888079919b60 RCX: 0000000000000003 <4> [120.057326] RDX: 0000000080000003 RSI: 0000000000000000 RDI: 00000000ffffffff <4> [120.057336] RBP: ffffffffa04c9f4e R08: 0000000000000000 R09: 0000000000000001 <4> [120.057348] R10: 0000000025c3d560 R11: 000000006815f798 R12: 0000000000000000 <4> [120.057359] R13: 00000000001e0100 R14: 0000000000000286 R15: ffffffff8234a76b <4> [120.057371] FS: 0000000000000000(0000) GS:ffff888074b00000(0000) knlGS:0000000000000000 <4> [120.057382] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [120.057393] CR2: 000055f4197df0d8 CR3: 000000006f326000 CR4: 00000000001006e0 <4> [120.057404] Call Trace: <4> [120.057635] fwtable_write32+0x114/0x1d0 [i915] <4> [120.057892] intel_power_domains_init_hw+0x4ff/0x650 [i915] <4> [120.058150] intel_power_domains_resume+0x3d/0x70 [i915] <4> [120.058363] i915_drm_resume_early+0x97/0xd0 [i915] <4> [120.058575] ? i915_resume_switcheroo+0x30/0x30 [i915] <4> [120.058594] dpm_run_callback+0x64/0x280 <4> [120.058626] device_resume_early+0xa7/0xe0 <4> [120.058652] async_resume_early+0x14/0x40 v2: Write our expected value of DISPLAY_PHY_CONTROL during sync_hw, so that it should always match the driver state after resume. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1089 Signed-off-by: Chris Wilson <[email protected]> Cc: Imre Deak <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/display: Fix NULL-crtc deref in calc_min_cdclk()Chris Wilson1-4/+5
[ 23.419442] BUG: KASAN: null-ptr-deref in intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.419527] Read of size 4 at addr 00000000000000f8 by task insmod/735 [ 23.419578] [ 23.419644] CPU: 2 PID: 735 Comm: insmod Not tainted 5.5.0+ #114 [ 23.419716] Hardware name: ��������������������������������� ���������������������������������/���������������������������������, BIOS RYBDWi35.86A.0246.2 [ 23.419793] Call Trace: [ 23.419864] dump_stack+0xef/0x16e [ 23.419927] __kasan_report.cold+0x60/0x90 [ 23.420157] ? intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.420397] intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.420630] intel_atomic_check+0x455f/0x65a0 [i915] [ 23.420708] ? mark_held_locks+0x90/0x90 [ 23.420929] ? intel_crtc_duplicate_state+0x2e/0x1b0 [i915] [ 23.421172] ? intel_plane_duplicate_state+0x2d/0xc0 [i915] [ 23.421239] ? __drm_dbg+0xa4/0x120 [ 23.421303] ? __kasan_kmalloc.constprop.0+0xc2/0xd0 [ 23.421355] ? __kmalloc_track_caller+0x23a/0x320 [ 23.421602] ? intel_calc_active_pipes+0x1c0/0x1c0 [i915] [ 23.421852] sanitize_watermarks+0x220/0x510 [i915] [ 23.422092] ? intel_atomic_check+0x65a0/0x65a0 [i915] [ 23.422164] ? drm_modeset_unlock_all+0x88/0x130 [ 23.422402] intel_modeset_init+0x1b76/0x3c90 [i915] [ 23.422647] ? intel_finish_reset+0x2d0/0x2d0 [i915] [ 23.422851] ? intel_irq_install+0x12c/0x210 [i915] [ 23.423076] i915_driver_probe+0x13e7/0x2930 [i915] v2: No crtc is implied by an invisible plane, so the extra !crtc check is redundant. Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/audio: Skip the cdclk modeset if no pipes attachedChris Wilson1-4/+8
If the display is not driving any pipes, we cannot change the bclk and doing so risks chasing NULL pointers: <6> [278.907105] snd_hda_intel 0000:00:0e.0: DSP detected with PCI class/subclass/prog-if info 0x040100 <6> [278.909936] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) <7> [278.910078] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2 <1> [278.910228] BUG: kernel NULL pointer dereference, address: 0000000000000080 <1> [278.910243] #PF: supervisor read access in kernel mode <1> [278.910251] #PF: error_code(0x0000) - not-present page <6> [278.910260] PGD 0 P4D 0 <4> [278.910267] Oops: 0000 [#1] PREEMPT SMP PTI <4> [278.910276] CPU: 0 PID: 5 Comm: kworker/0:0 Tainted: G U 5.5.0-CI-CI_DRM_7853+ #1 <4> [278.910289] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS GELKRVPA.X64.0062.B30.1708222146 08/22/2017 <4> [278.910312] Workqueue: events azx_probe_work [snd_hda_intel] <4> [278.910327] RIP: 0010:__ww_mutex_lock.constprop.15+0x5e/0x1090 <4> [278.910338] Code: 75 88 be a7 03 00 00 65 48 8b 04 25 28 00 00 00 48 89 45 c8 31 c0 4c 89 c3 e8 5e b3 6d ff 44 8b 3d 2f 24 37 02 45 85 ff 75 0a <4d> 3b 6d 58 0f 85 3f 07 00 00 48 85 db 74 22 49 8b 95 80 00 00 00 <4> [278.910362] RSP: 0018:ffffc9000008bc10 EFLAGS: 00010246 <4> [278.910371] RAX: 0000000000000246 RBX: ffffc9000008bd30 RCX: 0000000000000001 <4> [278.910382] RDX: 0000000000000000 RSI: ffffffff82647c60 RDI: ffff88817b27d848 <4> [278.910393] RBP: ffffc9000008bcc0 R08: 0000000000000000 R09: 0000000000000001 <4> [278.910404] R10: ffffc9000008bce0 R11: 0000000000000000 R12: ffffffff8168f0fc <4> [278.910414] R13: 0000000000000028 R14: ffffc9000008bd60 R15: 0000000000000000 <4> [278.910425] FS: 0000000000000000(0000) GS:ffff88817bc00000(0000) knlGS:0000000000000000 <4> [278.910437] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [278.910446] CR2: 0000000000000080 CR3: 00000001650da000 CR4: 0000000000340ef0 <4> [278.910456] Call Trace: <4> [278.910468] ? mark_held_locks+0x49/0x70 <4> [278.910479] ? ww_mutex_lock+0x39/0x70 <4> [278.910487] ww_mutex_lock+0x39/0x70 <4> [278.910497] drm_modeset_lock+0x6c/0x120 <4> [278.910575] glk_force_audio_cdclk+0x7d/0x140 [i915] <4> [278.910656] i915_audio_component_get_power+0xf2/0x110 [i915] <4> [278.910673] snd_hdac_display_power+0x7d/0x120 [snd_hda_core] <4> [278.910686] azx_probe_work+0x88/0x7e0 [snd_hda_intel] v2: Reorder glk_force_audio_cdclk() parameters to fit in with the norm. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1095 Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/pci: conversion to drm_device based logging macros.Wambui Karuga1-1/+2
Manual conversion of instances of printk based drm logging macros to the struct drm_device based logging macros in i915/i915_pci.c. Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/cmd_parser: conversion to struct drm_device logging macros.Wambui Karuga1-12/+17
Manually convert printk based drm logging macros to the struct drm_device based logging macros in i915/i915_cmd_parser.c. This also involves extracting the drm_i915_private device from various intel types for use in the macros. Instances of the DRM_DEBUG macro are not converted due to the lack of a similar struct drm_device based logging macro. References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-02-04drm/i915/debugfs: conversion to drm_device based logging macros.Wambui Karuga1-8/+13
Manual conversion of printk based logging macros to the struct drm_device based logging macros in i915/i915_debugfs.c. Also involves extracting the struct drm_i915_private device from various intel types to use in the macros. This does not convert various instances of the DRM_DEBUG macro due to the lack of an analogous struct drm_device based logging macro. References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html Signed-off-by: Wambui Karuga <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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