aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2013-01-28ARM: tegra: whistler: enable keyboard in DTLaxman Dewangan1-0/+12
Enable Tegra based keyboard controller and populate the key mapping for Whistler. With this patch, HOME, BACK, POWER and MENU keys will work. Still other keys which are in ROW3 and ROW4 will not work as it conflicts with KBC pins on SDIO2 pinmux. Signed-off-by: Laxman Dewangan <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: cardhu: register UARTCLaxman Dewangan1-0/+15
UARTC is used for the interfacing with bluetooth device. Register this UART channel as high speed serial channel so that it can use the APB DMA for data transfer. Signed-off-by: Laxman Dewangan <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: seaboard: enable keyboard in DTLaxman Dewangan1-0/+139
Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: Laxman Dewangan <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add DT entry for KBC controllerLaxman Dewangan2-0/+16
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <[email protected]> [swarren: added clocks property] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: swap cache-/interrupt-ctrlr nodes in DTStephen Warren2-18/+18
This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ASoC: tegra: add ac97 host controller to device treeLucas Stach1-0/+9
Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: DT: tegra: Add Tegra30 Beaver board supportBryan Wu3-0/+376
This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: Bryan Wu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: DT: tegra: Add board level compatible propertiesBryan Wu1-6/+23
The compatible properties of Tegra SoC based boards or machines need to be documented. This patch adds these board levle compatible properties into device tree binding document. Signed-off-by: Bryan Wu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: paz00: enable HDMI portStephen Warren1-4/+16
Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: ventana: enable HDMI portStephen Warren1-4/+16
Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: seaboard: enable HDMI portStephen Warren1-3/+15
Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: trimslice: add gpio-poweroff node to DTStephen Warren1-0/+10
... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: DT: tegra: Unify the description of Tegra20 boardsBryan Wu3-3/+3
Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: Bryan Wu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: dts: add aliases and DMA requestor for serial controllerLaxman Dewangan2-10/+51
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra30: tegra30 gpio is not compatible with tegra20 gpioLaxman Dewangan1-1/+1
tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <[email protected]> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: Add initial support for Tegra114 SoC.Hiroshi Doyu4-0/+60
Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: dt: tegra114: Add new board, PlutoHiroshi Doyu2-1/+23
Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: Hiroshi Doyu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: dt: tegra114: Add new board, DalmoreHiroshi Doyu2-1/+23
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: Hiroshi Doyu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: dt: tegra114: Add new SoC base, Tegra114 SoCHiroshi Doyu1-0/+114
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu1-0/+1
Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren12-68/+141
Conflicts: arch/arm/mach-tegra/platsmp.c
2013-01-28ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down modeJoseph Lo5-9/+192
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <[email protected]> Gary King <[email protected]> Signed-off-by: Joseph Lo <[email protected]> Acked-by: Colin Cross <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo2-5/+37
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_opsJoseph Lo1-0/+93
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra20: cpuidle: add powered-down state for secondary CPUJoseph Lo4-4/+259
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <[email protected]> Gary King <[email protected]> Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add pending SGI checking APIJoseph Lo2-0/+37
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28usb: host: tegra: don't touch EMC clockStephen Warren1-17/+0
Clock "emc" is for the External Memory Controller. The USB driver has no business touching this clock directly. Remove the code that does so. Acked-by: Greg Kroah-Hartman <[email protected]> Acked-by: Alan Stern <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28usb: add APIs to access host registers from Tegra PHYVenu Byravarasu3-43/+59
As Tegra PHY driver needs to access one of the host registers, added few APIs. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Alan Stern <[email protected]> [swarren: moved assignment of phy->is_ulpi_phy to previous patch.] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28USB: PHY: tegra: Get rid of instance number to differentiate PHY typeVenu Byravarasu2-14/+15
Tegra20 USB has 3 PHY instances: Instance 1 and 3 are UTMI. Instance 2 is ULPI. As instance number was used to differentiate ULPI from UTMI, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Felipe Balbi <[email protected]> [swarren: moved assignment of phy->is_ulpi_phy into this patch out of next patch.] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28USB: PHY: tegra: get rid of instance number to differentiate legacy controllerVenu Byravarasu2-17/+16
Tegra20 USB has 3 PHY instances. Instance 0 is based on legacy PHY interface and other two are standard interfaces. As instance number was used to differentiate legacy from standard interfaces, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add clocks properties to USB PHY nodesStephen Warren1-0/+6
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add DT nodes for Tegra USB PHYVenu Byravarasu3-0/+37
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28usb: phy: remove unused APIs from Tegra PHY.Venu Byravarasu2-17/+0
As tegra_usb_phy_clk_disable/enable() are not being used, removing them. Signed-off-by: Venu Byravarasu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28usb: host: tegra: Resetting PORT0 based on information received via DT.Venu Byravarasu1-1/+5
Tegra USB host driver is using port instance number, to handle some of the hardware issues on SOC e.g. reset PORT0 twice etc. As instance number based handling looks ugly, making use of information passed through DT for achieving this. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: Add new DT property to USB node.Venu Byravarasu2-0/+3
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Alan Stern <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28usb: phy: use kzalloc to allocate struct tegra_usb_phyVenu Byravarasu1-1/+1
Use kzalloc instead of kmalloc to allocate struct tegra_usb_phy. This ensures that all function pointers in member u_phy are initialized to NULL. Signed-off-by: Venu Byravarasu <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: remove USB address related macros from iomap.hVenu Byravarasu2-12/+3
USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad1-70/+0
With device tree support added for Tegra clocks look up is done from device tree, remove unused TEGRA_CLK_DUPLICATE()s. Signed-off-by: Prashant Gaikwad <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad1-17/+0
With device tree support added for Tegra clocks look up is done from device tree, remove unused TEGRA_CLK_DUPLICATE()s. Signed-off-by: Prashant Gaikwad <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra30: remove auxdataPrashant Gaikwad1-30/+1
Remove AUXDATA as clocks are initialized from device node. Signed-off-by: Prashant Gaikwad <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra20: remove auxdataPrashant Gaikwad1-24/+0
Remove AUXDATA as clock are initialized from device node. Signed-off-by: Prashant Gaikwad <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ASoC: tegra: remove auxdataPrashant Gaikwad1-12/+2
Configlink clock information is added to device tree. Get the clocks using device node. Remove AUXDATA. Signed-off-by: Prashant Gaikwad <[email protected]> Acked-by: Mark Brown <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28staging: nvec: remove use of clk_get_sysPrashant Gaikwad2-5/+1
As clock information is added to device tree clock can be looked up using clk_get. Remove use of clk_get_sys. Signed-off-by: Prashant Gaikwad <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Acked-by: Marc Dietrich <[email protected]> Acked-by: Julian Andres Klode <[email protected]> [swarren: updated TODO file to remove entry that requested this change] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: paz00: add clock information to DTPrashant Gaikwad1-0/+2
Add clock i2c clock information to device node. Signed-off-by: Prashant Gaikwad <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add clock properties to Tegra30 DTPrashant Gaikwad1-1/+55
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <[email protected]> [swarren: added second clock to 3d node] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: add clock properties to Tegra20 DTPrashant Gaikwad1-0/+44
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28spi: tegra: do not use clock name to get clockPrashant Gaikwad2-2/+2
Since Tegra spi devices do not have multiple clocks, no need to use clock name to get the clock. Signed-off-by: Prashant Gaikwad <[email protected]> Acked-by: Grant Likely <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: remove legacy clock codePrashant Gaikwad11-7141/+0
Remove all legacy clock code from mach-tegra. Signed-off-by: Prashant Gaikwad <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-01-28ARM: tegra: migrate to new clock codePrashant Gaikwad21-142/+73
Migrate Tegra clock support to drivers/clk/tegra, this involves moving: 1. definition of tegra_cpu_car_ops to clk.c 2. definition of reset functions to clk-peripheral.c 3. change parent of cpu clock. 4. Remove legacy clock initialization. 5. Initialize clocks using DT. 6. Remove all instance of mach/clk.h Signed-off-by: Prashant Gaikwad <[email protected]> [swarren: use to_clk_periph_gate().] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28clk: tegra: add clock support for Tegra30Prashant Gaikwad3-0/+2064
Add Tegra30 clock support based on common clock framework. Signed-off-by: Prashant Gaikwad <[email protected]> [swarren: ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.