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2022-07-05dt-bindings: usb: sunxi-musb: Add Allwinner D1 compatibleSamuel Holland1-0/+1
The MUSB controller in the Allwinner D1 has 10 endpoints, making it compatible with the A33 variant of the hardware. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: allwinner: a100: Update I2C controller fallbackSamuel Holland1-0/+6
The I2C controllers in the A100 SoC are newer-generation hardware which includes an offload engine. Signify that by including the allwinner,sun8i-v536-i2c fallback compatible, as V536 is the first SoC with this generation of I2C controller. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05dt-bindings: i2c: mv64xxx: Add variants with offload supportSamuel Holland1-1/+9
V536 and newer Allwinner SoCs contain an updated I2C controller which includes an offload engine for master mode. The controller retains the existing register interface, so the A31 compatible still applies. Add the V536 compatible and use it as a fallback for other SoCs with the updated hardware. This includes two SoCs that were already documented (H616 and A100) and two new SoCs (R329 and D1). Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: sun8i-r40: Add thermal trip points/cooling mapsqianfan Zhao1-0/+28
For the trip points, I used values from the BSP code. The critical trip point value is 30°C above the maximum recommended ambient temperature (85°C) for the SoC from the datasheet, so there's some headroom even at such a high ambient temperature. Signed-off-by: qianfan Zhao <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: sun8i-r40: add opp table for cpuqianfan Zhao6-0/+64
OPP table value is get from allwinner lichee linux-3.10 kernel driver Signed-off-by: qianfan Zhao <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based boardqianfan Zhao4-0/+16
The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node. Signed-off-by: qianfan Zhao <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanupKrzysztof Kozlowski15-123/+118
2022-07-05ARM: dts: aspeed: correct gpio-keys propertiesKrzysztof Kozlowski3-6/+0
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: aspeed: align gpio-key node names with dtschemaKrzysztof Kozlowski15-117/+118
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: exynosautov9: add usi device tree nodesChanho Park1-0/+1067
Universal Serial Interface (USI) supports three types of serial interface such as Universal Asynchronous Receiver and Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Each protocols can be working independently and configured as one of those using external configuration inputs. Exynos Auto v9 SoC support 12 USIs. When a USI uses two pins such as i2c and 3 wire uarts(RX/TX only), we can use remain two pins as i2c mode. So, we can define one USI node that includes serial/spi and hsi2c. usi_i2c nodes can be used only for i2c mode. We can have below combinations for one USI. 1) The usi node is used either 4 pin uart or 4 pin spi -> No usi_i2c can be used 2) The usi node is used 2 pin uart(RX/TX) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c 3) The usi node is used i2c(SDA/SCL) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c By default, all USIs are initially set to uart mode by below setting. samsung,mode = <USI_V2_UART>; You can change it either USI_V2_SPI or USI_V2_I2C. Signed-off-by: Chanho Park <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: exynosautov9: prepare usi0 changesChanho Park2-5/+7
Before adding whole USI nodes, this applies the changes of usi0 in advance. To be the usi0 and serian_0 nodes as SoC default, some properties should be moved to exynosautov9-sadk.dts. Signed-off-by: Chanho Park <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: exynosautov9: add pdma0 device tree nodeChanho Park1-0/+10
Add an ARM pl330 dma controller DT node as pdma0. Signed-off-by: Chanho Park <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05dt-bindings: soc: samsung: usi: add exynosautov9-usi compatibleChanho Park1-2/+6
Add samsung,exynosautov9-usi dedicated compatible for representing USI of Exynos Auto v9 SoC. Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Sam Protsenko <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: exynosautov9: correct spi11 pin namesChanho Park1-3/+3
They should be started with "gpp5-". Fixes: 31bbac5263aa ("arm64: dts: exynos: add initial support for exynosautov9 SoC") Signed-off-by: Chanho Park <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: stm32: Add ST MIPID02 bindings to AV96Marek Vasut1-0/+55
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for RCC pinMarek Vasut1-0/+15
Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for DCMI pinsMarek Vasut1-0/+37
Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut3-0/+353
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART5 pinsMarek Vasut1-0/+13
Add another mux option for UART5 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART4 pinsMarek Vasut1-0/+30
Add another mux option for UART4 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART3 pinsMarek Vasut1-0/+41
Add another mux option for UART3 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut1-0/+15
Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Add alternate pinmux for CAN1 pinsMarek Vasut1-0/+20
Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC ↵Marek Vasut1-1/+7
Compact Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact carrier board into YAML DT binding document. This system is a general purpose DIN Rail Controller design. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] To: [email protected] Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15Marek Vasut1-3/+3
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments. No functional change. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: lan966x: Add UDPHS supportHerve Codina1-0/+11
Add UDPHS (the USB High Speed Device Port controller) support. The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS IP. This IP is also the same as the one present in the SAMA5D3 SOC. Signed-off-by: Herve Codina <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05dt-bindings: usb: atmel: Add Microchip LAN9662 compatible stringHerve Codina1-0/+3
The USB device controller available in the Microchip LAN9662 SOC is the same IP as the one present in the SAMA5D3 SOC. Add the LAN9662 compatible string and set the SAMA5D3 compatible string as a fallback for the LAN9662. Signed-off-by: Herve Codina <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05ARM: dts: stm32: add optee reserved memory on stm32mp135f-dkGabriel Fernandez1-0/+11
Add the static OP-TEE reserved memory regions. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: add RCC on STM32MP13x SoC familyGabriel Fernandez4-79/+47
Enables Reset and Clocks Controller on STM32MP13 Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13Gabriel Fernandez1-0/+38
Enable optee and SCMI clocks support. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05dt-bindings: rcc: stm32: select the "secure" path for stm32mp13Alexandre Torgue1-0/+1
Like for stm32mp15, when stm32 RCC node is used to interact with a secure context (using clock SCMI protocol), a different path has to be used for yaml verification. Signed-off-by: Alexandre Torgue <[email protected]> Acked-by: Rob Herring <[email protected]>
2022-07-05ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32Leonard Göhrs1-7/+1
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to the VDD line and not to some single-purpose fixed regulator. Set the EEPROM supply according to the diagram to eliminate this parent-less regulator. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <[email protected]> Acked-by: Ahmad Fatoum <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1Leonard Göhrs1-0/+1
According to the OSD32MP1 Power System overview[1] ldo3's input is always internally connected to vdd_ddr. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <[email protected]> Reviewed-by: Ahmad Fatoum <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: adjust whitespace around '=' on MCU boardsKrzysztof Kozlowski5-18/+18
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSIMarek Vasut2-2/+7
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151Fabien Dessenne1-4/+3
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so remove the unsupported "wakeup" one. Note that the EXTI interrupt 61 has two roles : it is hierarchically linked to the GIC IPCC "rx" interrupt, and it acts as a wakeup source. Signed-off-by: Fabien Dessenne <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-05ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.Kavyasree Kotagiri1-14/+4
On pcb8291, Flexcom3 usart has only tx and rx pins. Cleaningup usart3 pinctrl settings. Signed-off-by: Kavyasree Kotagiri <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort orderGeert Uytterhoeven1-9/+9
The scif0 nodes were accidentally inserted after the scif3 nodes, breaking alphabetical sort order. Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be
2022-07-04arm64: dts: qcom: msm8996: Add interconnect supportYassine Oudjana1-0/+93
Add interconnect providers for the multiple NoCs available on the platform, and assign interconnects used by some blocks. Signed-off-by: Yassine Oudjana <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-05arm64: dts: Add SFP node for TA 3.0 devicesSean Anderson3-0/+24
This adds an SFP node for Trust Architecture 3.0 devices. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-05arm64: dts: layerscape: Add SFP node for TA 2.1 devicesSean Anderson3-0/+24
This adds an appropriate SFP node for Trust Architecture 2.1 devices. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-05ARM: dts: layerscape: Add SFP node for TA 2.1 devicesSean Anderson1-0/+7
This adds an appropriate SFP node for Trust Architecture 2.1 devices. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-05ARM: dts: ux500: Drop unused i2c power domain supplyLinus Walleij1-5/+0
This regulator supply is replaced by the proper power domain. Reported-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-04arm64: dts: allwinner: a64: orangepi-win: Fix LED node nameSamuel Holland1-1/+1
"status" does not match any pattern in the gpio-leds binding. Rename the node to the preferred pattern. This fixes a `make dtbs_check` error. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-04arm64: dts: rockchip: enable hdmi tx audio on rock-3aMichael Riesch1-0/+8
Enable the I2S0 controller and the hdmi-sound node on the Radxa ROCK3 Model A. Signed-off-by: Michael Riesch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-07-04arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10Michael Riesch1-0/+8
Enable the I2S0 controller and the hdmi-sound node on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-07-04Merge tag 'omap-for-v5.20/dt-signed' of ↵Arnd Bergmann1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes omaps for v5.20 merge window Just one devicetree change to add EEPROM regulator for BeagleBone Black. * tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-07-04ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15Fabrice Gasnier1-2/+2
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by: Fabrice Gasnier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-04ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMIGabriel Fernandez1-0/+6
Delete the node fixed clock managed by secure world with SCMI. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2022-07-04ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 boardGabriel Fernandez2-0/+8
LSE clock is provided by SCMI. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
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