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2021-01-08drm/i915/gt: Restore ce->signal flush before releasing virtual engineChris Wilson3-15/+47
Before we mark the virtual engine as no longer inflight, flush any ongoing signaling that may be using the ce->signal_link along the previous breadcrumbs. On switch to a new physical engine, that link will be inserted into the new set of breadcrumbs, causing confusion to an ongoing iterator. This patch undoes a last minute mistake introduced into commit bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer"), whereby instead of unconditionally applying the flush, it was only applied if the request itself was going to be reused. v2: Generalise and cancel all remaining ce->signals Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer") Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08drm/i915/selftests: Rearrange ktime_get to reduce latency against CSChris Wilson1-2/+2
In our tests where we measure the elapsed time on both the CPU and CS using a udelay, our CS results match the udelay much more accurately than the ktime (even when using ktime_get_fast_ns). With preemption disabled, we can go one step lower than ktime and use local_clock. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2919 Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08drm/i915/selftests: Skip unstable timing measurementsChris Wilson1-6/+14
If any of the perf tests run into 0 time, not only are we liable to divide by zero, but the result would be highly questionable. Nevertheless, let's not have a div-by-zero error. Signed-off-by: Chris Wilson <[email protected]> Cc: Andi Shyti <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08drm/i915/gt: Prevent use of engine->wa_ctx after errorChris Wilson1-0/+3
On error we unpin and free the wa_ctx.vma, but do not clear any of the derived flags. During lrc_init, we look at the flags and attempt to dereference the wa_ctx.vma if they are set. To protect the error path where we try to limp along without the wa_ctx, make sure we clear those flags! Reported-by: Matt Roper <[email protected]> Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb buffers if set") Signed-off-by: Chris Wilson <[email protected]> Cc: Matt Roper <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: <[email protected]> # v4.15+ Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08drm/i915: Disable RPM wakeref assertions during driver shutdownChris Wilson1-0/+4
As with the regular suspend paths, also disable the wakeref assertions as we disable the driver during shutdown. Reported-by: Hans de Goede <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899 Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot") Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Hans de Goede <[email protected]> Tested-by: Hans de Goede <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08drm/amdgpu: fix DRM_INFO flood if display core is not supported (bug 210921)Alexandre Demers1-1/+1
This fix bug 210921 where DRM_INFO floods log when hitting an unsupported ASIC in amdgpu_device_asic_has_dc_support(). This info should be only called once. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210921 Signed-off-by: Alexandre Demers <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-01-08drm/amdgpu/display: fix build with CONFIG_DRM_AMD_DC_DCN disabledAlex Deucher1-0/+2
dc_allow_idle_optimizations() needs to be protected by CONFIG_DRM_AMD_DC_DCN. Fixes: 71338cb4a7c2 ("drm/amd/display: enable idle optimizations for linux (MALL stutter)") Reviewed-by: Nicholas Kazlauskas <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du4-9/+51
This patch is to improve the fine grain tuning function for Renoir. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. And the flag "od_enabled" is used to control the overdrive function for dGPU, like navi10, navi14 and navi21. APU like Renior or Vangogh uses this "od_enabled" to configure the frequency range of gfx clock, but the max value of frequency range will not be higher than the safe limit, it is not "overdrive". So this patch adds two new flags -- "fine_grain_enabled" and "fine_grain_started" to avoid this confusion, the flag will make these two sysfs nodes work separately. The flag "fine_grain_enabled" is set as "enabled" by default, so the fine grain tuning function will be enabled by default. But the flag "fine_grain_started" is set as "false" by default, so the fine grain function will not take effect until it is set as "true". Only when power_dpm_force_perfomance_level is changed to "manual" mode, the flag "fine_grain_started" will be set as "true", and the fine grain tuning function will be started. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the flag "fine_grain_started" will be set as "false", and the od range of fine grain tuning function will be restored default value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amd/pm: add the parameters of power profiles for vangoghXiaojian Du2-26/+177
This pacth is to add the parameters of power profiles for vangogh, includeing "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk". Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amdgpu/psp: fix psp gfx ctrl cmdsVictor Zhao1-1/+1
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux, according to psp, linux cmds are not correct. v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD. Signed-off-by: Victor Zhao <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amdkfd: check more client ids in interrupt handlerTao Zhou1-2/+10
Add check for SExSH clients in kfd interrupt handler. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amdgpu: Correct the read sclk for navi10Emily.Deng1-1/+1
According to hw, after navi10,it runs in dfll mode, and should read sclk from AverageGfxclkFrequency. Signed-off-by: Emily.Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amdgpu: Add new mode 2560x1440Emily.Deng1-2/+3
Add one more 2k resolution which appears frequently in market. Signed-off-by: Emily.Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}Anshuman Gupta1-6/+2
We need a power_domain wakeref in pps_{lock,unlock} to prevent a race while resetting pps state in intel_power_sequencer_reset(). intel_power_sequencer_reset() need a pps_mutex to access pps_pipe but it can't grab pps_mutex due to deadlock with power_well functions are called while holding pps_mutex. intel_power_sequencer_reset() is called by power_well function associated with legacy platforms like vlv and chv therefore re-use the POWER_DOMAIN_DISPLAY_CORE power domain, which only used by vlv and chv display power domain. This will avoids the unnecessary noise of unrelated power wells in pps_{lock,unlock}. Cc: Jani Nikula <[email protected]> Cc: Imre Deak <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Acked-by: Imre Deak <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-08Merge drm/drm-next into drm-intel-nextRodrigo Vivi12165-230749/+832068
sync-up to not fall too much behind. Signed-off-by: Rodrigo Vivi <[email protected]>
2021-01-07drm/i915/gt: Remove timeslice suppressionChris Wilson2-108/+111
In the next^W future patch, we remove the strict priority system and continuously re-evaluate the relative priority of tasks. As such we need to enable the timeslice whenever there is more than one context in the pipeline. This simplifies the decision and removes some of the tweaks to suppress timeslicing, allowing us to lift the timeslice enabling to a common spot at the end of running the submission tasklet. One consequence of the suppression is that it was reducing fairness between virtual engines on an over saturated system; undermining the principle for timeslicing. v2: Commentary v3: Commentary for the right cancel_timer() v4: Add tracing for why we need a timeslice Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2802 Testcase: igt/gem_exec_balancer/fairslice Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07drm/i915: Wrap our timer_list.expires checkingChris Wilson2-2/+7
Refactor our timer_list.expires checking into its own timer_active() helper. Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07Merge tag 'drm-misc-next-2021-01-06' of ↵Daniel Vetter15-99/+174
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: Core Changes: - Lots of drm documentation updates by Simor Ser. - Require that each crtc has a unique primary plane. - Add fixme that fbdev_generic_setup is confusing. Driver Changes: - Update addresses for TI display drivers maintainers. - Make DRM_VIRTIO_GPU select VIRTIO. - Small fixes to qxl, virtio, hisilicon, tve200, panel/s6e63m0. Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07Merge tag 'du-next-20210105' of git://linuxtv.org/pinchartl/media into drm-nextDaniel Vetter35-226/+209
- Add default modes for connectors in unknown state - R-Car DU conversion to DRM-managed API - R-Car DU miscellaneous fixes - Miscellaneous bridge and bridge bindings fixes - Assorted misc driver cleanups - Constify drm_driver for PCI devices Signed-off-by: Daniel Vetter <[email protected]> From: Laurent Pinchart <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/X/[email protected]
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of ↵Daniel Vetter48-3039/+3183
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani) - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Signed-off-by: Daniel Vetter <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there is ↵Hans de Goede1-3/+13
no reset-deassert MIPI-sequence Commit 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode") added an intel_dsi_msleep() helper which skips sleeping if the MIPI-sequences have a version of 3 or newer and the panel is in vid-mode; and it moved a bunch of msleep-s over to this new helper. This was based on my reading of the big comment around line 730 which starts with "Panel enable/disable sequences from the VBT spec.", where the "v3 video mode seq" column does not have any wait t# entries. Given that this code has been used on a lot of different devices without issues until now, it seems that my interpretation of the spec here is mostly correct. But now I have encountered one device, an Acer Aspire Switch 10 E SW3-016, where the panel will not light up unless we do actually honor the panel_on_delay after exexuting the MIPI_SEQ_PANEL_ON sequence. What seems to set this model apart is that it is lacking a MIPI_SEQ_DEASSERT_RESET sequence, which is where the power-on delay usually happens. Fix the panel not lighting up on this model by using an unconditional msleep(panel_on_delay) instead of intel_dsi_msleep() when there is no MIPI_SEQ_DEASSERT_RESET sequence. Fixes: 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode") Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07Merge tag 'imx-drm-next-2021-01-04' of ↵Daniel Vetter18-424/+715
git://git.pengutronix.de/git/pza/linux into drm-next drm/imx: fixes and drm managed resources - Reduce stack usage in ipu-di. - Fix imx-ldb for compile tests. - Make drm encoder control functions optional. - Add drm managed variants drmm_encoder_alloc(), drmm_simple_encoder_alloc(), drmm_universal_plane_alloc(), and drmm_crtc_alloc_with_planes() for drm_encoder_init(), drm_simple_encoder_init(), drm_universal_plane_init(), and drm_crtc_init_with_planes(), respectively. - Update imx-drm to use the new functions for drm managed resource allocation, moving initialization from bind to probe where possible. - Fix imx-tve clock provider leak. Signed-off-by: Daniel Vetter <[email protected]> [danvet: Fix conflict between doc changes by both Philipp and Simon Ser, see 9999587b684f ("drm: rework description of primary and cursor planes")] From: Philipp Zabel <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07Merge tag 'topic/dp-hdmi-2.1-pcon-2020-12-23' of ↵Daniel Vetter11-19/+1650
git://anongit.freedesktop.org/drm/drm-intel into drm-next Add support for DP-HDMI2.1 PCON From the series cover letter: This patch series attempts to add support for a DP-HDMI2.1 Protocol Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata E5 to DisplayPort_v2.0: https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299 The details are mentioned in: VESA DP-to-HDMI PCON Specification Standalone Document https://groups.vesa.org/wg/DP/document/15651 This series starts with adding support for FRL (Fixed Rate Link) Training between the PCON and HDMI2.1 sink. As per HDMI2.1 specification, a new data-channel or lane is added in FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4 lanes). With these patches, the HDMI2.1 PCON can be configured to achieve FRL training based on the maximum FRL rate supported by the panel, source and the PCON. The approach is to add the support for FRL training between PCON and HDMI2.1 sink and gradually add other blocks for supporting higher resolutions and other HDMI2.1 features, that can be supported by pcon for the sources that do not natively support HDMI2.1. This is done before the DP Link training between the source and PCON is started. In case of FRL training is not achieved, the PCON will work in the regular TMDS mode, without HDMI2.1 feature support. Any interruption in FRL training between the PCON and HDMI2.1 sink is notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD registers are read and FRL training is re-attempted. Currently, we have tested the FRL training and are able to enable 4K display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting panel. Signed-off-by: Daniel Vetter <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-07Merge tag 'drm-misc-next-2020-12-17' of ↵Daniel Vetter239-5418/+5338
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: UAPI Changes: - Not necessarily one, but we document that userspace needs to force probe connectors. Cross-subsystem Changes: - Require FB_ATY_CT for aty on sparc64. - video: Fix documentation, and a few compiler warnings. - Add devicetree bindings for DP connectors. - dma-buf: Update kernel-doc, and add might_lock for resv objects in begin/end_cpu_access. Core Changes: - ttm: Warn when releasing a pinned bo. - ttm: Cleanup bo size handling. - cma-helper: Remove prime infix, and implement mmap as GEM CMA functions. - Split drm_prime_sg_to_page_addr_arrays into 2 functions. - Add a new api to install irq using devm. - Update panel kerneldoc to inline style. - Add DP support to drm/bridge. - Assorted small fixes to ttm, fb-helper, scheduler. - Add atomic_commit_setup function callback. - Automatically use the atomic gamma_set, instead of forcing drivers to declare the default atomic version. - Allow using degamma for legacy gamma if gamma is not available. - Clarify that primary/cursor planes are not tied to 1 crtc (depending on possible_crtcs). - ttm: Cleanup the lru handler. Driver Changes: - Add pm support to ingenic. - Assorted small fixes in radeon, via, rockchip, omap2fb, kmb, gma500, nouveau, virtio, hisilicon, ingenic, s6e63m0 panel, ast, udlfb. - Add BOE NV110WTM-N61, ys57pss36bh5gq, Khadas TS050 panels. - Stop using pages with drm_prime_sg_to_page_addr_arrays, and switch all callers to use ttm_sg_tt_init. - Cleanup compiler and docbook warnings in a lot of fbdev devices. - Use the drmm_vram_helper in hisilicon. - Add support for BCM2711 DSI1 in vc4. - Add support for 8-bit delta RGB panels to ingenic. - Add documentation on how to test vkms. - Convert vc4 to atomic helpers. - Use degamma instead of gamma table in omap, to add support for CTM and color encoding/range properties. - Rework omap DSI code, and merge all omapdrm modules now that the last omap panel is now a drm panel. - More refactoring of omap dsi code. - Enable 10/12 bpc outputs in vc4. Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-06drm/i915/rkl: Add DP vswing programming tablesMatt Roper1-3/+39
The bspec has been updated with new vswing programming for RKL DP. No data is provided for HDMI or eDP, so for now we'll continue to assume that those are the same as TGL. Bspec: 49291 Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Swathi Dhanavanthri <[email protected]>
2021-01-06Revert "drm/amd/display: Fix memory leaks in S3 resume"Alex Deucher1-2/+1
This reverts commit a135a1b4c4db1f3b8cbed9676a40ede39feb3362. This leads to blank screens on some boards after replugging a display. Revert until we understand the root cause and can fix both the leak and the blank screen after replug. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211033 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1427 Cc: Stylon Wang <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Andre Tomt <[email protected]> Cc: Oleksandr Natalenko <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-01-06drm/i915/selftests: Improve handling of iomem around stolenChris Wilson1-5/+5
Use memset_io() on the iomem, and silence sparse as we copy from the iomem to normal system pages. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-06drm/i915/selftests: Break out of the lrc layout test after register mismatchChris Wilson1-4/+6
AFter detecting a register mismatch between the protocontext and the image generated by HW, immediately break out of the double loop. Otherwise we end up with a second confusing error message. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-05drm/i915/rkl: new rkl ddc map for different PCHLee Shawn C2-0/+12
After boot into kernel. Driver configured ddc pin mapping based on predefined table in parse_ddi_port(). Now driver configure rkl ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will give incorrect gmbus port number to cause HDMI can't work. Refer to commit cd0a89527d06 ("drm/i915/rkl: Add DDC pin mapping"). Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can works properly on rkl. v2: update patch based on latest dinq branch. v3: update ddc table for RKL+TGP sku. RKL+CNP sku will load cnp_ddc_pin_map[] setting. v4: modify the if/else judgment to avoid nesting. v5: fix typo in v4. Cc: Matt Roper <[email protected]> Cc: Aditya Swarup <[email protected]> Cc: Anusha Srivatsa <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Cooper Chiou <[email protected]> Cc: Khaled Almahallawy <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577 Signed-off-by: Lee Shawn C <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-05Merge tag 'gvt-next-fixes-2020-12-25' of https://github.com/intel/gvt-linux ↵Rodrigo Vivi10-18/+42
into drm-intel-next gvt-next-fixes-2020-12-25 - Avoid one useless inline (Jani) - make gvt header self-contained, fix CONFIG_DRM_I915_WERROR (Jani) Signed-off-by: Rodrigo Vivi <[email protected]> From: Zhenyu Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-05drm/amdgpu: Add check to prevent IH overflowDefang Bo3-39/+71
Similar to commit <b82175750131>("drm/amdgpu: fix IH overflow on Vega10 v2"). When an ring buffer overflow happens the appropriate bit is set in the WPTR register which is also written back to memory. But clearing the bit in the WPTR doesn't trigger another memory writeback. So what can happen is that we end up processing the buffer overflow over and over again because the bit is never cleared. Resulting in a random system lockup because of an infinite loop in an interrupt handler. Reviewed-by: Christian König <[email protected]> Signed-off-by: Defang Bo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu/display: drop DCN support for aarch64Alex Deucher13-73/+1
From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <[email protected]> Reported-by: Ard Biesheuvel <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: enable ras eeprom support for sienna cichlidJohn Clements1-1/+7
added I2C address and asic support flag Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix no bad_pages issue after umc ue injectionDennis Li1-4/+4
old code wrongly used the bad page status as the function return value, which cause amdgpu_ras_badpages_read always return failed. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix potential memory leak during navi12 deinitializationJiawei Gu1-4/+14
Navi12 HDCP & DTM deinitialization needs continue to free bo if already created though initialized flag is not set. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Jiawei Gu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: Enable fp16 also on DCE-8/10/11.Mario Kleiner3-3/+3
The hw supports fp16, this is not only useful for HDR, but also for standard dynamic range displays, because it allows to get more precise color reproduction with about 11 - 12 bpc linear precision in the unorm range 0.0 - 1.0. Working fp16 scanout+display (and HDR over HDMI) was verified on a DCE-8 asic, so i assume that the more recent DCE-10/11 will work equally well, now that format-specific plane scaling constraints are properly enforced, e.g., the inability of fp16 to scale on older hw like DCE-8 to DCE-11. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: Check plane scaling against format specific hw plane caps.Mario Kleiner1-8/+73
This takes hw constraints specific to pixel formats into account, e.g., the inability of older hw to scale fp16 format framebuffers. It should now allow safely to enable fp16 formats also on DCE-8, DCE-10, DCE-11.0 Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: take runtime pm reference when we attach a bufferAlex Deucher1-2/+14
And drop it when we detach. If the shared buffer is in vram, we need to make sure we don't put the device into runtime suspend. Acked-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: Create and Destroy PSR resources for DCN302Joshua Aberback1-0/+13
We need these to support PSR on DCN302 Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: enable idle optimizations for linux (MALL stutter)Bhawanpreet Lakha2-1/+27
[Why] We can only use this feature when the display is idle. When active vblank irq count is 0 we know all the displays are idle. [How] -Add a active vblank irq counter -Update the counter when we enable/disable vblank irq -if vblank irq count is 0 we can consider mall stutter Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Nick Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: Update idle optimization handlingJoshua Aberback8-2/+31
[How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by: Joshua Aberback <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: Fix unused variable warningArnd Bergmann2-4/+2
Some of the newly added code is hidden inside of #ifdef blocks, but one variable is unused when debugfs is disabled: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8370:8: error: unused variable 'configure_crc' [-Werror,-Wunused-variable] Change the #ifdef to an if(IS_ENABLED()) check to fix the warning and avoid adding more #ifdefs. Fixes: c920888c604d ("drm/amd/display: Expose new CRC window property") Reviewed-by: Wayne Lin <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: fix comparison pointer to bool warning in dc.cTian Tao1-2/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc.c:1543:12-19: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:1496:14-42: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:971:15-48: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:976:15-44: WARNING: Comparison to bool Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: Fix macro name _AMDGPU_TRACE_H_ in preprocessor if conditionChenyang Li1-1/+1
Add an underscore in amdgpu_trace.h line 24 "_AMDGPU_TRACE_H". Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)") Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Paul Menzel <[email protected]> Signed-off-by: Chenyang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05gpu/drm/radeon: use DIV_ROUND_UP macro to do calculationZheng Yongjun1-2/+2
Don't open-code DIV_ROUND_UP() kernel macro. Signed-off-by: Zheng Yongjun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: remove useless else ifTian Tao1-2/+0
Fix the following coccinelle report: drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c:1357:6-8: WARNING: possible condition with no effect (if == else) Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/display: remove unused including <linux/version.h>Tian Tao3-3/+0
Remove including <linux/version.h> that don't need it. Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/pm: improve the fine grain tuning function for RV/RV2/PCOXiaojian Du2-1/+59
This patch is to improve the fine grain tuning function for RV/RV2/PCO. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. So this patch adds one flag to avoid this confusion, the flag will make these two sysfs nodes work separately. The flag is set as "disabled" by default, so the fine grain tuning function will be disabled by default. Only when power_dpm_force_perfomance_level is changed to "manual" mode, the flag will be set as "enabled", and the fine grain tuning function will be enabled. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the flag will be set as "disabled", and the od range of fine grain tuning function will be restored default value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amd/pm: enable dclk/vclk dpm function in "auto" power profile for vangoghXiaojian Du1-0/+2
This patch is to enable dclk/vclk dpm function in "auto" power profile for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: do optimization for psp command submitpengzhou1-2/+2
In the psp command submit logic, the function msleep(1) delayed too long, Changing it to usleep_range(10, 100) to have a better performance. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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