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2014-05-12ARM: imx6: clk: i.MX6 DualLite/Solo i2c4 clockIain Paton1-1/+5
Compared to i.MX6 Quad/Dual the CCM_CCGR1 register in the i.MX6 Solo/DualLite replaces the ecspi5 clock with the i2c4 clock. Handle this difference using cpu_is_imx6dl(). Signed-off-by: Iain Paton <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-05-12ARM: imx_v6_v7_defconfig: enable cpufreq and CMA supportShawn Guo1-1/+5
- Enable imx6 cpufreq support with ondemand governor - Enable CMA support so that device like 1080p HDMI can work - Run savedefconfig Signed-off-by: Shawn Guo <[email protected]>
2014-05-12ARM: shmobile: Remove unused r8a7791_init_early()Magnus Damm2-8/+0
Remove the now unused r8a7791_init_early() function. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-12ARM: shmobile: Use r8a7791 DT CPU Frequency for KoelschMagnus Damm2-2/+2
Convert the Koelsch board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-12ARM: shmobile: Use r8a7791 DT CPU Frequency in common caseMagnus Damm1-1/+1
Convert the common C-code-less r8a7791 DT board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-11ARM: shmobile: Remove unused r8a7740_init_delay()Magnus Damm2-6/+0
Remove the now unused r8a7740_init_delay() function. Signed-off-by: Magnus Damm <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-11ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT RefMagnus Damm1-1/+1
Convert the Armadillo r8a7740 DT reference board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-11ARM: shmobile: Use r8a7740 DT CPU Frequency in common caseMagnus Damm1-1/+1
Convert the common C-code-less r8a7740 DT board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-11ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTSMagnus Damm1-0/+1
Add 800 MHz to the r8a7740 DTS to describe the maximum CPU frequency. Signed-off-by: Magnus Damm <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-11ARM: shmobile: r8a7740: Correct name of DT Ethernet clockGeert Uytterhoeven1-1/+1
The preferred node name in DT for an Ethernet device is "ethernet". "sh-eth" was used in preliminary and incomplete bindings. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-05-08ARM: mvebu: Fix pmsu compilation when ARMv6 is selectedVincent Stehlé1-0/+1
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler flags are for ARMv6, and we will get: /tmp/ccwDEzd0.s: Assembler messages: /tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb ' /tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb ' /tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb ' /tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb ' make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1 Fix this in a similar manner than done previously in commit 72533b77d30c2be02672e26b5dde1263d7b4c2be, by specifying ARMv7 flags for pmsu.o. Signed-off-by: Vincent Stehlé <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Cc: Jason Cooper <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: Gregory Clement <[email protected]> Cc: Sebastian Hesselbarth <[email protected]> Cc: Russell King <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: conditionalize Armada 375 coherency workaroundThomas Petazzoni1-2/+8
The Armada 375 coherency workaround only needs to be applied to the Z1 revision of the SoC. The A0 and later revisions have been fixed, and no longer need this workaround. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1399302326-6917-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: conditionalize Armada 375 SMP workaroundThomas Petazzoni1-9/+11
The Armada 375 SMP workaround only needs to be applied to the Z1 revision of the SoC. The A0 and later revisions have been fixed, and no longer need this workaround. Note that the initialization of the SMP workaround is delayed from ->smp_prepare_cpus() to ->smp_boot_secondary() because when ->smp_prepare_cpus() is called, the early initcalls have not be called, so the mvebu-soc-id mechanism is not operational. Since the workaround is anyway not needed before the secondary CPU is started, we can delay its implementation until the ->smp_boot_secondary() call. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: add Armada 375 A0 revision definitionThomas Petazzoni1-0/+1
Now that we have access to Armada 375 A0 platforms, we can add the corresponding revision definition in mvebu-soc-id.h. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1399302326-6917-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: initialize mvebu-soc-id earlierThomas Petazzoni1-1/+1
Currently, the mvebu-soc-id logic is initialized through a core_initcall(). However, we will soon need to know the SoC revision before booting secondary CPUs, because a workaround affects Armada 375 Z1 steppings, but should not be applied on Armada 375 A0 steppings. Unfortunately, core_initcall() are called way too late compared to the SMP initialization. Therefore, the mvebu-soc-id initialization is move to an early_initcall(), which is called before the SMP initialization. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1399302326-6917-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: fix thermal quirk SoC revision checkThomas Petazzoni1-1/+1
In commit 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board'), a check on the Armada SoC revision was added to decide whether a quirk for the thermal device should be applied or not. However, the quirk implementation has a bug: it assumes mvebu_get_soc_id() returns true on success, but it returns 0. Therefore, the condition: if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV) is always false (as long as mvebu-soc-id is properly initialized). As a consequence, the quirk is always applied, even on A0 steppings, for which the quirk should not be applied. This was spotted by testing the thermal driver on Armada 375 A0, which Ezequiel could not do since he does not have access to the A0 revision of the SoC for the moment. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board') Acked-by: Ezequiel Garcia <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: Kirkwood: t5325: Remove platform device to instantiate audioAndrew Lunn5-43/+0
Remove platform device instantiating of the audio, which results in board-t5325.c being removed. A DT node will be added to take its place. Signed-off-by: Andrew Lunn <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: Kirkwood: Remove platform driver for codecAndrew Lunn1-15/+0
Remove the platform driver and platform data for the audio codec. A DT node will replace it. Signed-off-by: Andrew Lunn <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Add thermal quirk for the Armada 375 DB boardEzequiel Garcia2-0/+60
The initial release of the Armada 375 DB board has an Armada 375 Z1 stepping silicon. This commit introduces a quirk that allows to workaround a series of issues with the thermal sensor in this stepping, but updating the devicetree: * Updates the compatible string for the thermal, so the driver can perform a specific initialization of the sensor. * Moves the offset of the thermal control register. This quirk allows to specifiy the correct (A0 stepping) offset in the devicetree. Signed-off-by: Ezequiel Garcia <[email protected]> Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabledEzequiel Garcia1-2/+2
HAVE_ARM_TWD depends on SMP, so we should only select it if SMP is enabled, as the others platforms do. Signed-off-by: Ezequiel Garcia <[email protected]> Link: https://lkml.kernel.org/r/1398339276-5754-1-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_idGregory CLEMENT1-1/+1
The name of the two parameters of mvebu_get_soc_id were inverted. This patch fix it in order to have a more readable code. Reported-by: Ezequiel Garcia <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: remove unnecessary ifdef around l2x0_of_initGregory CLEMENT1-2/+0
l2x0_of_init function is always defined arch/arm/include/asm/hardware/cache-l2x0.h: in case of CONFIG_CACHE_L2X0 is not selected then a placeholder is defined. Then there is no need to have ifdef around l2x0_of_init. Signed-off-by: Gregory CLEMENT <[email protected]> Reviewed-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: register the cpuidle driver for the Armada XP SoCsGregory CLEMENT1-0/+37
The cpuidle is a platform driver so we register the device just after the initialization of the board in an arch_initcall. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-12-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoCGregory CLEMENT3-0/+99
Add the wfi, cpu idle and cpu deep idle power states support for the Armada XP SoCs. All the latencies and the power consumption values used at the "armada_370_xp_idle_driver" structure are preliminary and will be modified in the future after running some measurements and analysis. Based on the work of Nadav Haklai. Signed-off-by: Nadav Haklai <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Register notifier callback for the cpuidle transitionGregory CLEMENT1-0/+18
In order to have well encapsulated code, we use notifier callbacks for CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-10-git-send-email-gregory.clement@free-electrons.com Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: refine which files are build in mach-mvebuThomas Petazzoni1-5/+8
Following the integration into mach-mvebu of the Kirkwood ARMv5 support, we need to be more careful about which files get built. For example, the pmsu.c file now calls wfi(), which only exists on ARMv7 platforms. Therefore, this commit changes mach-mvebu/Makefile to build the Armada 370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is enabled. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1398709239-6126-1-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Gregory CLEMENT <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Add the PMSU related part of the cpu idle functionsGregory CLEMENT1-1/+131
The cpu idle support will need to access to Power Management Service Unit. This commit adds the architecture related functions that will be used in the idle path of the cpuidle driver. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-9-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Allow to power down L2 cache controller in idle modeGregory CLEMENT1-1/+19
This commit adds a function which adjusts the PMSU configuration to automatically power down the L2 and coherency fabric when we enter a certain idle state. This feature is part of the Power Management Service Unit of the Armada 370 and Armada XP SoCs. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-8-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Low level function to disable HW coherency supportGregory CLEMENT1-0/+20
When going to deep idle we need to disable the SoC snooping (aka hardware coherency support). Playing with the coherency fabric requires to use assembly code to be sure that the compiler doesn't reorder the instructions nor do wrong optimization. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Split low level functions to manipulate HW coherencyGregory CLEMENT3-35/+71
Actually enabling coherency and adding a CPU on a SMP group are two different operations which can be done separately. This patch splits this in two functions. Moreover as they use common pattern, this patch also creates local low level functions (ll_get_coherency_base and ll_get_cpuid) to be used by the exposed functions (ll_add_cpu_to_smp_group and ll_enable_coherency) Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: Remove the unused argument of set_cpu_coherent()Gregory CLEMENT3-4/+4
set_cpu_coherent() took the SMP group ID as parameter. But this parameter was never used, and the CPU always uses the SMP group 0. So we can remove this parameter. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: ll_set_cpu_coherent always uses the current CPUGregory CLEMENT5-18/+12
ll_set_cpu_coherent is always used on the current CPU, so instead of passing the CPU id as argument, ll_set_cpu_coherent() can find it by itself. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com Acked-by: Thomas Petazzoni <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: remove the address parameter for ll_set_cpu_coherentGregory CLEMENT3-14/+23
In order to be able to deal with the MMU enabled and the MMU disabled cases, the base address of the coherency registers was passed to the function. The address by itself was not interesting as it can't change for a given SoC, the only thing we need is to have a distinction between the physical or the virtual address. This patch add a check of the MMU bit to choose the accurate address, then the calling function doesn't have to pass this information. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: add Armada 38x compatible string to pmsuThomas Petazzoni2-3/+7
Since the Armada 38x PMSU registers are slightly different than the Armada 370/XP PMSU ones, we introduce a new compatible string "armada-380-pmsu" in the PMSU driver. These differences are not visible for the current usage of the PMSU, but they might become visible in the future. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: add workaround for SMP support for Armada 375 stepping Z1Gregory CLEMENT2-0/+44
Due to internal bootrom issue, CPU[1] initial jump code (four instructions) should be placed in SRAM memory of the SoC. In order to achieve this, we have to unmap the BootROM and at some specific location where the BootROM was place, create a specific MBus window for the SRAM. This SRAM is initialized with a few instructions of code that allows to jump into the real secondary CPU boot address. This workaround will most likely be disabled when newer steppings of the Armada 375 will be made available, in which case a dynamic test based on mvebu-soc-id will be added. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: add SMP support for Armada 375 and Armada 38xGregory CLEMENT5-1/+97
This commit adds the SMP support for Armada 375 and Armada 38x. It turns out that the SMP logic for both of these SOCs are fairly similar, the only differences being: * A different method to set the secondary CPU boot address * An Armada 375 specific workaround needed for the early Z1 stepping, added by the following patch. Other than that, the patch is fairly straightforward and adds the usual platsmp and headsmp code, defining the smp_operations structure that is referenced from the DT_MACHINE structures. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: add function to set the resume boot address for Armada 375Gregory CLEMENT2-1/+15
In order to boot the secondary CPUs on Armada 375, we need to set the boot address of these CPUs, through a register part of the System Controller (this deviates from the Armada XP design, where the boot address was defined using a register part of the PMSU unit). Therefore, this commit adds a new helper function in the System Controller driver to set the secondary CPU boot address. Moreover, it moves the System Controller initialization as an early_initcall(), since arch_initcall() is too late for an SMP-related initialization. Signed-off-by: Gregory CLEMENT <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08Merge branch 'mvebu/irqchip' into mvebu/socJason Cooper4-14/+24
2014-05-08ARM: mvebu: use CPU_METHOD_OF_DECLARE for SMP on Armada XPThomas Petazzoni2-0/+4
This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada XP SMP operations. Note that the .smp_ops field of Armada XP DT_MACHINE structure is kept, in order to ensure we remain compatible with older Device Trees that do not include the "enable-method" property for the CPUs. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08ARM: mvebu: move Armada XP specific SMP initialization to platsmp.cThomas Petazzoni3-26/+11
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets the boot address of a secondary CPUs and deasserts the reset. However, the Armada 375 needs a slightly different logic, so it makes more sense to move this code into the Armada XP specific platsmp.c. In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function is exported. It will be needed for both the Armada XP and Armada 38x SMP implementations. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08Merge branch 'mvebu/soc-pmsu' into mvebu/socJason Cooper6-28/+185
2014-05-08irqchip: orion: Reverse irq handling prioritySebastian Hesselbarth1-2/+2
Non-DT irq handlers were working through irq causes from most-significant to least-significant bit, while DT irqchip driver does it the other way round. This revealed some more HW issues on Kirkwood peripheral IP, where spurious sdio irqs can happen although irqs are masked. Also, the generated binaries show that original non-DT order compared to DT order save two instructions for each bit count check: irqchip DT order with ffs(): 60: e3a06001 mov r6, #1 64: e2643000 rsb r3, r4, #0 68: e0033004 and r3, r3, r4 6c: e16f3f13 clz r3, r3 70: e263301f rsb r3, r3, #31 74: e1c44316 bic r4, r4, r6, lsl r3 78: e5971004 ldr r1, [r7, #4] Original non-DT order with fls(): 60: e3a07001 mov r7, #1 64: e16f3f14 clz r3, r4 68: e263301f rsb r3, r3, #31 6c: e1c44317 bic r4, r4, r7, lsl r3 70: e5951004 ldr r1, [r5, #4] Therefore, reverse irq bit handling back to original order by replacing ffs() with fls(). Signed-off-by: Sebastian Hesselbarth <[email protected]> Link: https://lkml.kernel.org/r/1398719528-23607-1-git-send-email-sebastian.hesselbarth@gmail.com Acked-by: Jason Cooper <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2014-05-08irqchip: irq-armada-370-xp: Use cpu notifier to initialize secondary CPUsThomas Petazzoni3-8/+17
Some irqchip initialization must be done on secondary CPUs. On mvebu platforms, this is currently achieved by having the arch/arm/mach-mvebu/platsmp.c code directly call into a function exported by the irqchip driver, which isn't really nice. This commit changes this by using the same solution as the one used in the GIC driver: the irqchip driver registers a CPU notifier, which is used to do the secondary CPU IRQ initialization. This way, the irqchip driver is completely autonomous, and the function no longer needs to be exposed from the irqchip driver to the SoC code. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-08irqchip: irq-armada-370-xp: Do the set_smp_cross_call() in the driverThomas Petazzoni3-4/+5
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the set_smp_cross_call() to register the IPI-triggering function, it makes more sense to do exactly what the GIC driver is doing: let the irqchip driver do it. This way, it avoids having to expose the armada_mpic_send_doorbell() function between the irqchip driver and the SoC code. Signed-off-by: Thomas Petazzoni <[email protected]> Link: https://lkml.kernel.org/r/1397483648-26611-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
2014-05-07ARM: at91/dt: at91-cosino_mega2560 remove useless tsadcc nodeAlexandre Belloni1-5/+0
The tsadcc node is useless as it doesn't refer to anything and the touchscreen is handled by the adc0 node. Signed-off-by: Alexandre Belloni <[email protected]> Acked-by: Rodolfo Giometti <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-05-07ARM: at91: remove atmel_tsadcc platform_dataAlexandre Belloni2-10/+0
Signed-off-by: Alexandre Belloni <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-05-07Input: atmel_tsadcc: remove driverAlexandre Belloni4-377/+0
The atmel_tsadcc driver is not used anymore, it has been replaced by at91_adc so remove it. Signed-off-by: Alexandre Belloni <[email protected]> Acked-by: Dmitry Torokhov <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-05-07ARM: at91: remove atmel_tsadcc from sama5_defconfigAlexandre Belloni1-1/+0
atmel_tsadcc has been removed, stop selecting it. Signed-off-by: Alexandre Belloni <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-05-07ARM: at91: sam9rl: switch from atmel_tsadcc to at91_adcAlexandre Belloni3-63/+2
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc does. Completely switch to at91_adc and remove the tsadcc platform_data for at91sam9rl and at91sam9rl based boards. Signed-off-by: Alexandre Belloni <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-05-07ARM: at91: sam9g45: switch from atmel_tsadcc to at91_adcAlexandre Belloni3-66/+5
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc does. Completely switch to at91_adc and remove the tsadcc platform_data for at91sam9g45 and at91sam9g45 based boards. Signed-off-by: Alexandre Belloni <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
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