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2021-08-07drm/msm/dsi: stop calling set_encoder_mode callbackDmitry Baryshkov3-15/+0
None of the display drivers now implement set_encoder_mode callback. Stop calling it from the modeset init code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-7-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dp: stop calling set_encoder_mode callbackDmitry Baryshkov1-18/+0
None of the display drivers now implement set_encoder_mode callback. Stop calling it from the modeset init code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-6-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/mdp5: move mdp5_encoder_set_intf_mode after msm_dsi_modeset_initDmitry Baryshkov1-8/+3
Move a call to mdp5_encoder_set_intf_mode() after msm_dsi_modeset_init(), removing set_encoder_mode callback. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-5-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dpu: support setting up two independent DSI connectorsDmitry Baryshkov1-45/+57
Move setting up encoders from set_encoder_mode to _dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This allows us to support not only "single DSI" and "bonded DSI" but also "two independent DSI" configurations. In future this would also help adding support for multiple DP connectors. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-4-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: add three helper functionsDmitry Baryshkov3-10/+33
Add three helper functions to be used by display drivers for setting up encoders. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-3-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: rename dual DSI to bonded DSIDmitry Baryshkov8-80/+79
We are preparing to support two independent DSI hosts in the DSI/DPU code. To remove possible confusion (as both configurations can be referenced as dual DSI) let's rename old "dual DSI" (two DSI hosts driving single device, with clocks being locked) to "bonded DSI". Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-2-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [DB: add one extra hunk added by one previous patches] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: add support for dsi test pattern generatorAbhinav Kumar3-0/+77
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block. To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern. This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then. Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change. Changes in v2: - generate the new dsi.xml.h and update the bitfield names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/1626922232-29105-2-git-send-email-abhinavk@codeaurora.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: update dsi register header file for tpgAbhinav Kumar1-0/+73
Update the DSI controller header XML file to add registers and bitfields to support rectangular checkered pattern generator. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/1626922232-29105-1-git-send-email-abhinavk@codeaurora.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> [DB: removed headergen commit changes] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: Add DSI support for SC7280Rajeev Nandan2-0/+21
Add support for v2.5.0 DSI block in the SC7280 SoC. Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1624365748-24224-4-git-send-email-rajeevny@codeaurora.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: Add PHY configuration for SC7280Rajeev Nandan4-3/+32
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with different enable|disable regulator loads. Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1624365748-24224-3-git-send-email-rajeevny@codeaurora.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07dt-bindings: msm/dsi: Add sc7280 7nm dsi phyRajeev Nandan1-0/+1
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver. Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org> Link: https://lore.kernel.org/r/1624365748-24224-2-git-send-email-rajeevny@codeaurora.org Acked-by: Rob Herring <robh+dt@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: drop msm_dsi_phy_get_shared_timingsDmitry Baryshkov3-13/+8
Instead of fetching shared timing through an extra function call, get them directly from msm_dsi_phy_enable. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210709210729.953114-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: phy: use of_device_get_match_dataDmitry Baryshkov1-6/+4
Use of_device_get_match-data() instead of of_match_node(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210709210729.953114-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dpu: Add newlines to printksStephen Boyd1-7/+5
Add some missing newlines to the various DRM printks in this file. Noticed while looking at logs. While we're here unbreak quoted strings so grepping them is easier. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210708065619.999199-1-swboyd@chromium.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: mdp4: drop vblank get/put from prepare/complete_commitDavid Heidelberg1-13/+0
msm_atomic is doing vblank get/put's already, currently there no need to duplicate the effort in MDP4 Fix warning: ... WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194 drm_vblank_put+0x1cc/0x1d4 ... and multiple vblank time-outs: ... msm 5100000.mdp: vblank time out, crtc=1 ... Tested on Nexus 7 2013 (deb), LTS 5.10.50. Introduced by: 119ecb7fd3b5 ("drm/msm/mdp4: request vblank during modeset") Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210715060925.7880-1-david@ixit.cz Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/mdp4: move HW revision detection to earlier phaseDavid Heidelberg1-23/+22
Fixes if condition, which never worked inside mdp4_kms_init, since HW detection has been done later in mdp4_hw_init. Fixes: eb2b47bb9a03 ("drm/msm/mdp4: only use lut_clk on mdp4.2+") Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210705231641.315804-2-david@ixit.cz Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/mdp4: refactor HW revision detection into read_mdp_hw_revisionDavid Heidelberg1-9/+18
Inspired by MDP5 code. Also use DRM_DEV_INFO for MDP version as MDP5 does. Cosmetic change: uint32_t -> u32 - checkpatch suggestion. Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210705231641.315804-1-david@ixit.cz Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: Fix error return code in msm_drm_init()Wei Li1-0/+1
When it fail to create crtc_event kthread, it just jump to err_msm_uninit, while the 'ret' is not updated. So assign the return code before that. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Li <liwei391@huawei.com> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210705134302.315813-1-liwei391@huawei.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: drop gdsc regulator handlingDmitry Baryshkov2-27/+7
None of supported devies uses "gdsc" regulator for DSI. GDSC support is now implemented as a power domain. Drop old code and config handling gdsc regulator requesting and enabling. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210701000015.3347713-1-dmitry.baryshkov@linaro.org Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm/dsi: support CPHY mode for 7nm pll/phyJonathan Marek4-47/+184
Add the required changes to support 7nm pll/phy in CPHY mode. This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable the CPHY mode. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210617144349.28448-4-jonathan@marek.ca Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07dt-bindings: msm: dsi: document phy-type property for 7nm dsi phyJonathan Marek2-0/+7
Document a new phy-type property which will be used to determine whether the phy should operate in D-PHY or C-PHY mode. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.ca Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07dt-bindings: msm: dsi: add missing 7nm bindingsJonathan Marek1-0/+66
These got lost when going from .txt to .yaml bindings, add them back. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Fixes: 8fc939e72ff8 ("dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings") Link: https://lore.kernel.org/r/20210617144349.28448-2-jonathan@marek.ca Reviewed-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: Use list_move_tail instead of list_del/list_add_tail in msm_gem.cBaokun Li1-2/+1
Using list_move_tail() instead of list_del() + list_add_tail() in msm_gem.c. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Baokun Li <libaokun1@huawei.com> Link: https://lore.kernel.org/r/20210609072838.1369371-1-libaokun1@huawei.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: Use nvmem_cell_read_variable_le_u32() to read speed binDouglas Anderson1-3/+2
Let's use the newly-added nvmem_cell_read_variable_le_u32() to future proof ourselves a little bit. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210521134516.v2.1.Id496c6fea0cb92ff6ea8ef1faf5d468eb09465e3@changeid Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: Periodically update RPTR shadowRob Clark2-11/+45
On a5xx and a6xx devices that are using CP_WHERE_AM_I to update a ringbuffer read-ptr shadow value, periodically emit a CP_WHERE_AM_I every 32 commands, so that a later submit waiting for ringbuffer space to become available sees partial progress, rather than not seeing rptr advance at all until the GPU gets to the end of the submit that it is currently chewing on. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210428193654.1498482-3-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm/msm: Implement mmap as GEM object functionThomas Zimmermann6-62/+16
Moving the driver-specific mmap code into a GEM object function allows for using DRM helpers for various mmap callbacks. The respective msm functions are being removed. The file_operations structure fops is now being created by the helper macro DEFINE_DRM_GEM_FOPS(). v2: * rebase onto latest upstream * remove declaration of msm_gem_mmap_obj() from msm_fbdev.c Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20210706084753.8194-1-tzimmermann@suse.de [squash in missing VM_DONTEXPAND flag] Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm: msm: Add 680 gpu to the adreno gpu listBjorn Andersson5-8/+32
This patch adds a Adreno 680 entry to the gpulist. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210725032002.3961691-1-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-06drm/amdkfd: Allow querying SVM attributes that are clearFelix Kuehling2-13/+22
Currently the SVM get_attr call allows querying, which flags are set in the entire address range. Add the opposite query, which flags are clear in the entire address range. Both queries can be combined in a single get_attr call, which allows answering questions such as, "is this address range coherent, non-coherent, or a mix of both"? Proposed userspace for UAPI: https://github.com/RadeonOpenCompute/ROCR-Runtime/tree/memory_model_queries Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yand <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amd/display: Remove redundant initialization of variable eng_idColin Ian King1-1/+1
The variable eng_id is being initialized with a value that is never read, it is being re-assigned on the next statment. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amdgpu: check for allocation failure in amdgpu_vkms_sw_init()Dan Carpenter1-0/+2
Check whether the kcalloc() fails and return -ENOMEM if it does. Fixes: 84ec374bd58036 ("drm/amdgpu: create amdgpu_vkms (v4)") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amd/pm: bug fix for the runtime pm BACOKenneth Feng1-2/+1
In some systems only MACO is supported. This is to fix the problem that runtime pm is enabled but BACO is not supported. MACO will be handled seperately. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/i915/dg2: Add support for new DG2-G11 revid 0x5Matt Roper1-0/+1
The bspec has been updated with a new revision 0x5 that translates to B1 GT stepping and C0 display stepping. Bspec: 44477 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-2-matthew.d.roper@intel.com
2021-08-06drm/bridge: anx7625: Tune K value for IVO panelXin Ji2-4/+24
IVO panel require less input video clock variation than video clock variation in DP CTS spec. This patch decreases the K value of ANX7625 which will shrink eDP Tx video clock variation to meet IVO panel's requirement. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Xin Ji <xji@analogixsemi.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210806104407.2208538-1-xji@analogixsemi.com
2021-08-06drm: bridge: it66121: Check drm_bridge_attach retvalRobert Foss1-0/+2
The return value of drm_bridge_attach() is ignored during the it66121_bridge_attach() call, which is incorrect. Fixes: 988156dc2fc9 ("drm: bridge: add it66121 driver") Signed-off-by: Robert Foss <robert.foss@linaro.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210805185039.402178-1-robert.foss@linaro.org Link: https://patchwork.freedesktop.org/patch/msgid/20210805185039.402178-1-robert.foss@linaro.org
2021-08-05drm/amdgpu: Add preferred mode in modeset when freesync video mode's enabled.Solomon Chiu1-1/+6
[Why] With kernel module parameter "freesync_video" is enabled, if the mode is changed to preferred mode(the mode with highest rate), then Freesync fails because the preferred mode is treated as one of freesync video mode, and then be configurated as freesync video mode(fixed refresh rate). [How] Skip freesync fixed rate configurating when modeset to preferred mode. Signed-off-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amd/pm: Fix a memory leak in an error handling path in ↵Christophe JAILLET1-1/+1
'vangogh_tables_init()' 'watermarks_table' must be freed instead 'clocks_table', because 'clocks_table' is known to be NULL at this point and 'watermarks_table' is never freed if the last kzalloc fails. Fixes: c98ee89736b8 ("drm/amd/pm: add the fine grain tuning function for vangogh") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05DRM: gpu: radeon: Fixed coding style issuesSergio Miguéns Iglesias1-5/+2
Fixed braces, an unnecessary if statement and added a missing space. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Sergio Miguéns Iglesias <sergio@lony.xyz> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/radeon: Update pitch for page flipZhenneng Li4-3/+30
When primary bo is updated, crtc's pitch may have not been updated, this will lead to show disorder content when user changes display mode, we update crtc's pitch in page flip to avoid this bug. This refers to amdgpu's pageflip. v1->v2: Update all of the pitch in all of the page_flip functions in radeon rather than just the evergreen one. v2->v3: Update pitch set method for r100 according to radeon_legacy_crtc.c Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Zhenneng Li <lizhenneng@kylinos.cn> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdkfd: Expose GFXIP engine version to sysfsGraham Sider4-0/+34
Add u32 gfx_target_version field to kfd_node_properties and kfd_device_info. Populate <asic>_device_info structs accordingly and expose to sysfs. This allows eliminating device-ID-based lookup tables in user mode for future ASICs. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: drop redundant null-pointer checks in amdgpu_ttm_tt_populate() ↵Tuo Li1-2/+2
and amdgpu_ttm_tt_unpopulate() The varialbe gtt in the function amdgpu_ttm_tt_populate() and amdgpu_ttm_tt_unpopulate() is guaranteed to be not NULL in the context. Thus the null-pointer checks are redundant and can be dropped. Reported-by: TOTE Robot <oslab@tsinghua.edu.cn> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tuo Li <islituo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: don't enable baco on boco platforms in runpmAlex Deucher1-0/+2
If the platform uses BOCO, don't use BACO in runtime suspend. We could end up executing the BACO path if the platform supports both. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1669 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: Put MODE register in wave debug infoJoseph Greathouse5-0/+5
Add the MODE register into the per-wave debug information. This register holds state such as FP rounding and denorm modes, which exceptions are enabled, and active clamping modes. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: set RAS EEPROM address from VBIOSJohn Clements4-1/+59
update to latest atombios fw table Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amd/amdgpu: Recovery vcn instance iterate.Peng Ju Zhou1-13/+20
The previous logic is recording the amount of valid vcn instances to use them on SRIOV, it is a hard task due to the vcn accessment is based on the index of the vcn instance. Check if the vcn instance enabled before do instance init. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: added synchronization for psp cmd buf accessJohn Clements1-66/+139
resolved race condition accessing psp cmd submission memory Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: update PSP BL cmd IDsJohn Clements1-3/+3
resolved bug with incorrect PSP BL cmd IDs Signed-off-by: John Clements <john.clements@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amd/pm: update smu v13.0.1 firmware headerXiaomeng Hou1-1/+3
Update smu v13.0.1 firmware header for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: add DID for beige gobyChengming Gui1-0/+7
Add device ids. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debuggingTom St Denis2-0/+58
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu/display: fix DMUB firmware version infoShirish S1-1/+1
DMUB firmware info is printed before it gets initialized. Correct this order to ensure true value is conveyed. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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