aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-06-08drm/amd/display: Return last used DRR VTOTAL from DCJayendran Ramani12-6/+75
[How] Add call to get the last used VTOTAL from DC Signed-off-by: Jayendran Ramani <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Remove unused definition of DMUB SET_CONFIGMeenakshikumar Somasundaram1-4/+0
[Why & How] SET_CONFIG transactions with DMUB is not used and removed. Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Update scaling settings on modesetRoman Li1-1/+2
[Why] We update scaling settings when scaling mode has been changed. However when changing mode from native resolution the scaling mode previously set gets ignored. [How] Perform scaling settings update on modeset. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Support mappable encoders when transmitting training patterns.Jimmy Kizito1-1/+10
[Why & How] Add support for transmitting training pattern sequences for links whose encoders have been dynamically assigned. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Expand DP module equalization API.Jimmy Kizito2-11/+19
[Why & How] Add functionality useful for DP equalization phase of link training to public interface. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Revert "Fix clock table filling logic"Ilya Bakoulin2-72/+39
[Why] This change was found to break some high-refresh modes. Reverting to unblock mainline. Signed-off-by: Ilya Bakoulin <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: add visual confirm colors to differentiate layer_index > 0Evgenii Krasnikov1-0/+14
[WHY] Currently there is no way to visually identify if there is one or more layers presented fullscreen on the display [HOW] Add new visual confirm colors in get_surface_visual_confirm_color for planes with layer_index > 0 Signed-off-by: Evgenii Krasnikov <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Refactor visual confirmWyatt Wood18-179/+172
[Why + How] Visual confirm has no asic-specific logic, so we can refactor and unify these functions that are currently spread out across multiple dcn files. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. This will allow visual confirm to updated independently of MPCC blending updates. v2: squash in DCN3.1 fixes Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Control power gating by driver.JinZe.Xu1-22/+12
[Why] This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs. [How] Power gating is controlled by driver. Signed-off-by: JinZe.Xu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Fix DCN 3.01 DSCCLK validationNikola Cornij1-43/+21
[why] DSCCLK validation is not necessary because DSCCLK is derrived from DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too. Doing DSCLK validation in addition to DISPCLK leads to modes being wrongly rejected when DSCCLK was incorrectly set outside of DML. [how] Remove DSCCLK validation because it's implicitly validated under DISPCLK Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: delay 100ms before restart after failing to read CP_IRQWenjing Liu1-1/+1
[why] Some DPRX will issue CP_IRQ when user disconnects a display that has been authenticated. Since display is being disconnecting dpcd read will fail. This will cause us to attempt HDCP retry on disconnection. We are adding a 100ms delay before retry. So we will only start retry if within 100ms there is no disconnection call to HDCP module. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Enabling PSR support for multiple panelsMikita Lipski6-34/+153
[why] Updating PSR interfaces to allow PSR enablement per eDP panel. [how] - Copying PSR command structures to DC - Changing function interfaces to pass panel instance - Communicating with DMUB per link instead of assuming to use a single one -Iterating through all PSR capable panels when enabling/disabling all Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Trigger full update after DCC on/offJake Wang1-1/+6
[Why] During DCC on/off, stutter period is calculated before DCC has fully transitioned. This results in incorrect stutter period calculation. [How] Trigger a full update when DCC changes between on/off. Signed-off-by: Jake Wang <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: allocate psp fw private buffer from VRAM for sriov vfZhigang Luo1-5/+14
psp added new feature to check fw buffer address for sriov vf. the address range must be in vf fb. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: add psp ta microcode init for aldebaran sriov vfZhigang Luo1-0/+6
need to load xgmi ta for aldebaran sriov vf. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: remove sriov vf mmhub system aperture and fb location programmingZhigang Luo1-14/+3
host driver programmed mmhub system aperture and fb location for vf, no need to program in guest side. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: remove sriov vf gfxhub fb location programmingZhigang Luo1-12/+0
host driver programmed the gfxhub fb location for vf, no need to program in guest side. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: remove sriov vf checking from getting fb locationZhigang Luo1-4/+1
host driver programmed fb location registers for vf, no need to check anymore. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/pm: fix warning reported by kernel test robotXiaomeng Hou1-1/+1
Kernel test robot throws warning -> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2: warning: variable 'member_type' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47: note: uninitialized use occurs here return yellow_carp_get_smu_metrics_data(smu, member_type, value); ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2: note: variable 'member_type' is declared here MetricsMember_t member_type; ^ 1 warning generated. Fix this warning by return errno when the clk type is unsupported. Reported-by: kernel test robot <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amdgpu: fix shadow bo skip conditionNirmoy Das1-1/+1
Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: add kernel documentation for smu_get_power_limitDarren Powell2-0/+38
added doc tag "amdgpu_pp_power" with description added tags for enums pp_power_limit_level, pp_power_type added tag for function smu_get_power_limit Test: * Temporary insertion into Documentation/gpu/amdgpu.rst ------------START------------ Power Limit ----------- .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :doc: amdgpu_pp_power .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_limit_level .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_type .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c :identifiers: smu_get_power_limit -------------END------------- Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: handle return value for get_power_limitDarren Powell1-15/+24
Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: modify and add smu_get_power_limit to Powerplay APIDarren Powell3-17/+7
modify args of smu_get_power_limit to match Powerplay API .get_power_limit add smu_get_power_limit to Powerplay API swsmu_pm_funcs remove special handling of smu in amdgpu_hwmon_show_power_cap* * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power enumsDarren Powell3-24/+41
updated {amd_pm_funcs}->get_power_limit() signature rewrote pp_get_power_limit to use new enums pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit update calls to {amd_pm_funcs}->get_power_limit() * Test Notes * testing hardware was NAVI10 (tests SMU path) ** needs testing on VANGOGH ** needs testing on SMU < 11 ** ie, one of TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO, STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: clean up smu_get_power_limit function signatureDarren Powell4-12/+57
add two new powerplay enums (limit_level, type) add enums to smu_get_power_limit signature remove input bitfield stuffing of output variable limit update calls to smu_get_power_limit * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08amdgpu/pm: reorder definition of swsmu_pm_funcs for readabilityDarren Powell1-24/+24
Match the order of definition to the structure's declaration to help with locating included and missing functions of the API Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/bridge: ti-sn65dsi83: Fix syntax formatting issuesMarek Vasut1-18/+18
Fix checkpatch.pl --strict -f drivers/gpu/drm/bridge/ti-sn65dsi83.c CHECKs, no functional change. This is the same modification done to V7 of the original patch. Signed-off-by: Marek Vasut <[email protected]> Cc: Adam Ford <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Frieder Schrempf <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Loic Poulain <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Philippe Schenker <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Valentin Raevsky <[email protected]> To: [email protected] Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-08x86/gpu: add JasperLake to gen11 early quirksTejas Upadhyay1-0/+1
Let's reserve JSL stolen memory for graphics. JasperLake is a gen11 platform which is compatible with ICL/EHL changes. This was missed in commit 24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids") V2: - Added maintainer list in cc - Added patch ref in commit message V1: - Added Cc: [email protected] Fixes: 24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids") Cc: <[email protected]> # v5.11+ Cc: Thomas Gleixner <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: [email protected] Cc: José Roberto de Souza <[email protected]> Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20210608053411.394166-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-06-08drm/ttm: nuke VM_MIXEDMAP on BO mappings v3Christian König1-30/+12
We discussed if that is really the right approach for quite a while now, but digging deeper into a bug report on arm turned out that this is actually horrible broken right now. The reason for this is that vmf_insert_mixed_prot() always tries to grab a reference to the underlaying page on architectures without ARCH_HAS_PTE_SPECIAL and as far as I can see also enabled GUP. So nuke using VM_MIXEDMAP here and use VM_PFNMAP instead. Also make sure to reject mappings without VM_SHARED. v2: reject COW mappings, merge function with only caller v3: adjust comment as suggested by Thomas Signed-off-by: Christian König <[email protected]> Bugs: https://gitlab.freedesktop.org/drm/amd/-/issues/1606#note_936174 Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Thomas Hellström <[email protected]>
2021-06-08drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driverMarek Vasut3-0/+720
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add. The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed. Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Tested-by: Frieder Schrempf <[email protected]> Tested-by: Adam Ford <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Loic Poulain <[email protected]> Cc: Philippe Schenker <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Valentin Raevsky <[email protected]> To: [email protected] Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-08dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 bindingsMarek Vasut1-0/+159
Add DT binding document for TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge. Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Rob Herring <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-08drm/ttm: fix pipelined gutting v2Christian König1-8/+20
We need to make sure to allocate the sys_mem resource before the point of no return. v2: add missing return value checking, also handle idle case Signed-off-by: Christian König <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07drm/amd/display: Fix two spelling mistakes, clean wide linesColin Ian King1-4/+6
There are two spelling mistakes in dml_print messages, fix these and clear up checkpatch warning on overly wide line length. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Fix a a typo in a commentChristophe JAILLET1-1/+1
s/than/then/ Acked-by: Christian König <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amd/display: Fix duplicate included dce110_hw_sequencer.hJiapeng Chong1-1/+0
Clean up the following includecheck warning: ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: dce110_hw_sequencer.h is included more than once. No functional change. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amd/display: remove no need variableBernard Zhao1-3/+1
remove no need variable, just return the DC_OK Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Fix warning of Function parameter or member not describedEric Huang1-0/+1
Add the parameter table_freed description on function description. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdkfd: remove duplicate include of kfd_svm.hWan Jiabing1-1/+0
kfd_svm.h is included duplicately in commit 42de677f79999 ("drm/amdkfd: register svm range"). After checking possible related header files, remove the former one to make the code format more reasonable. Signed-off-by: Wan Jiabing <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: fix VM handling for GART allocationsChristian König1-2/+2
For GTT allocations with a GART address the res contains the VMID0 addresses and can't be used for VM handling. So ignore the res when the pages array is given or we fill the page tables with nonsense. Signed-off-by: Christian König <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10Peng Ju Zhou2-3/+4
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so NULL pointer must be checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Update psp fw attestation support listJohn Clements1-0/+3
Disable support on APU Reviewed-by: Changfeng <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdkfd: add sdma poison consumption handlingHawking Zhang2-1/+7
Follow the same apporach as GFX to handle SDMA poison consumption. Send SIGBUS to application when receives SDMA_ECC interrupt and issue gpu reset either mode 2 or mode 1 to get the engine back Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdkfd: pages_addr offset must be 0 for system rangePhilip Yang1-1/+1
prange->offset is for VRAM range mm_nodes, if multiple ranges share same mm_nodes, migrate range back to VRAM will reuse the VRAM at offset of the same mm_nodes. For system memory pages_addr array, the offset is always 0, otherwise, update GPU mapping will use incorrect system memory page, and cause system memory corruption. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macrosRohit Khaire1-35/+35
In SRIOV environment, KMD should access SDMA registers through RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when the flag is enabled. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/ttm: fix warning after moving resource to ghost objChristian König1-0/+1
After we moved the resource to the ghost the bo->resource pointer needs to be reset since the owner of the resource is now the ghost. Signed-off-by: Christian König <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07drm/i915/display: Drop FIXME about turn off infoframesJosé Roberto de Souza1-1/+0
intel_dp_set_infoframes() call in intel_ddi_post_disable_dp() will take care to disable all enabled infoframes. Cc: Ville Syrjälä <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with ↵José Roberto de Souza1-1/+16
PSR enabled When PSR is enabled it handles DP_SDP_VSC, changing revision and all the other fields as necessary. It can also enabled and disable this SDP as needed without a full modeset. So here masking DP_SDP_VSC bit when previous and future state PSR enabled, it will still be checked when comparing the asked state to what was programmed to hardware. Cc: Gwan-gyeong Mun <[email protected]> Cc: Radhakrishna Sripada <[email protected]> Reported-by: Ville Syrjälä <[email protected]> Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Gwan-gyeong Mun <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07drm/i915/display: Fix fastsets involving PSRJosé Roberto de Souza1-5/+5
Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") is not allowing fastsets to happen when PSR states changes but PSR is a feature that can be enabled and disabled during fastsets. So here moving the PSR pipe conf checks to a block that is only executed when checking if HW state matches with requested state, not during the phase where it checks if fastset is possible or not. There still a state mismatch not allowing fastsets between states turning off or on PSR because of crtc_state->infoframes.enable BIT(DP_SDP_VSC) but at least for now it will allow a fastset between PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not work with PSR2, but the remaning issue will be fixed in a future patch. Cc: Gwan-gyeong Mun <[email protected]> Cc: Radhakrishna Sripada <[email protected]> Reported-by: Ville Syrjälä <[email protected]> Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Gwan-gyeong Mun <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07drm/ttm: fix access to uninitialized variable.Christian König1-1/+1
The resource is not allocated yet, so no chance that this will work. Use the placement instead. Signed-off-by: Christian König <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-07MAINTAINERS: Add maintainer for hyperv video deviceDeepak Rawat1-0/+8
Maintainer for hyperv synthetic video device. Signed-off-by: Deepak Rawat <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.