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2021-06-04drm/amdgpu/pm: add smu v13.0.1 firmware header for yellow carp (V4)Aaron Liu1-0/+139
This patch is to add smu v13.0.1 firmware header for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/admgpu/pm: add smu v13 driver interface header for yellow carp (v3)Aaron Liu1-0/+222
This patch is to add smu v13 driver interface header for yellow carp. v2: squash in updates (Alex) v3: squash in v69.29.0 update (Alex) Signed-off-by: Aaron Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: support nbio_7_2_1 for yellow carpAaron Liu1-38/+104
This patch adds nbio_7_2_1 support yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdkfd: add yellow carp KFD supportAaron Liu6-0/+75
This patch is to add GFX10 based Yellow Carp KFD support. We will bypass IOMMU v2. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: set ip blocks for yellow carpAaron Liu1-0/+9
Enable ip blocks for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add sdma support for yellow carpAaron Liu1-0/+7
This patch adds the sdma v5.2 support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add gfx support for yellow carpAaron Liu1-0/+26
Add yellow carp checks to gfx10 code. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: support fw load type for yellow carpAaron Liu1-0/+1
This patch sets fw load type as direct with fw_load_type=0 for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add gmc v10 supports for yellow carpAaron Liu1-2/+7
Add gfx memory controller support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add yellow carp support for ih blockAaron Liu1-0/+1
This patch adds the support for yellow carp ih block. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add nv common ip block support for yellow carpAaron Liu1-0/+8
This patch adds common ip support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add yellow_carp_reg_base_init function for yellow carp (v2)Alex Deucher4-1/+1420
This patch adds yellow_carp_reg_base_init function to init the register base for yellow carp. v2: squash in updates (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add yellow carp support for gpu_info and ip block settingAaron Liu1-0/+7
This patch adds yellow carp support for gpu_info firmware and ip block setting. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add uapi to define yellow carp seriesAaron Liu1-0/+1
Add a flag to define yellow carp series. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add yellow carp asic_type enumAaron Liu2-0/+2
This patch adds yellow carp to amd_asic_type enum and amdgpu_asic_name[]. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add yellow carp asic header files (v3)Aaron Liu6-0/+192037
This patch is to add yellow carp asic header files. v2: squash in updates (Alex) v3: squash in DCN updates (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04radeon: use memcpy_to/fromio for UVD fw uploadChen Li1-2/+2
I met a gpu addr bug recently and the kernel log tells me the pc is memcpy/memset and link register is radeon_uvd_resume. As we know, in some architectures, optimized memcpy/memset may not work well on device memory. Trival memcpy_toio/memset_io can fix this problem. BTW, amdgpu has already done it in: commit ba0b2275a678 ("drm/amdgpu: use memcpy_to/fromio for UVD fw upload"), that's why it has no this issue on the same gpu and platform. Signed-off-by: Chen Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04radeon: fix coding issues reported from sparseChen Li1-11/+13
Also fix some coding issues reported from sparse. Signed-off-by: Chen Li <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm: amdgpu: Remove unneeded semicolon in amdgpu_vm.cWan Jiabing1-1/+1
Fix following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1726:2-3: Unneeded semicolon Reviewed-by: Christian König <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: Fix fall-through warning for ClangGustavo A. R. Silva1-0/+1
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Modify GC register access to use _SOC15 macrosRohit Khaire1-21/+21
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when flag is enabled. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Enable RLCG read/write interface for Sienna CichlidRohit Khaire1-1/+1
Enable this only for Sienna Cichild since only Navi12 and Sienna Cichlid support SRIOV Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Fix incorrect register offsets for Sienna CichlidRohit Khaire1-5/+21
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different offsets for Sienna Cichlid Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Don't flush/invalidate HDP for APUs and A+AEric Huang6-21/+42
Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: Use generic BACO function for smu11 ASICsLijo Lazar3-33/+3
Remove ASIC specific functions for BACO support check. Use generic smu11 function instead. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: Add VF check to BACO support checkLijo Lazar1-1/+1
For smuv11, check for VF also during BACO check. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: Read BIF STRAP also for BACO checkLijo Lazar3-20/+59
Avoid reading BIF STRAP each time for BACO capability. Read the STRAP value while checking BACO capability in PPTable. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: Remove BACO check for aldebaranLijo Lazar1-7/+0
BACO/MACO is not applicable for aldebaran. Remove the redundant check. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Keep linebuffer pixel depth at 30bpp for DCE-11.0.Mario Kleiner1-2/+9
Testing on AMD Carizzo with DCE-11.0 display engine showed that it doesn't like a 36 bpp linebuffer very much. The display just showed a solid green. Testing on RavenRidge DCN-1.0, Polaris11 with DCE-11.2 and Kabini with DCE-8.3 did not expose any problems, so for now only revert to 30 bpp linebuffer depth on asics with DCE-11.0 display engine. Fixes: a316db72096044 ("drm/amd/display: Increase linebuffer pixel depth to 36bpp.") Reported-by: Tom StDenis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm: fix doc warnings in drm_atomic.hYu Kuai1-0/+4
Add description for parameters for for_each_new_plane_in_state_reverse to fix warnings: include/drm/drm_atomic.h:908: warning: Function parameter or member '__state' not described in 'for_each_new_plane_in_state_reverse' include/drm/drm_atomic.h:908: warning: Function parameter or member 'plane' not described in 'for_each_new_plane_in_state_reverse' include/drm/drm_atomic.h:908: warning: Function parameter or member 'new_plane_state' not described in 'for_each_new_plane_in_state_reverse' include/drm/drm_atomic.h:908: warning: Function parameter or member '__i' not described in 'for_each_new_plane_in_state_reverse' Fixes: a6c3c37b661d ("drm/amd/display: fix gcc set but not used warning of variable 'old_plane_state'") Signed-off-by: Yu Kuai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: remove variable active_dispColin Ian King1-4/+1
The variable active_disp is being initialized with a value that is never read, it is being re-assigned immediately afterwards. Clean up the code by removing the need for variable active_disp. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: remove redundant assignment of variable kColin Ian King1-1/+1
The variable k is being assigned a value that is never read, the assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdkfd: Make TLB flush conditional on mappingEric Huang4-20/+27
It is to optimize memory mapping latency, and also aviod a page fault in a corner case of changing valid PDE into PTE. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Add table_freed parameter to amdgpu_vm_bo_updateEric Huang4-10/+10
It is to pass the flag to KFD, and optimize table_freed in amdgpu_vm_bo_update_mapping. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdkfd: Add heavy-weight TLB flush after unmappingEric Huang1-0/+1
It is a part of memory mapping optimization. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdkfd: Add flush-type parameter to kfd_flush_tlbEric Huang4-7/+7
It is to provide more tlb flush types option for different case scenario. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FBMichel Dänzer1-2/+2
drm_err meant broken user space could spam dmesg. Fixes: f258907fdd835e "drm/amdgpu: Verify bo size can fit framebuffer size on init." Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_createChangfeng1-2/+2
It will cause error when alloc memory larger than 128KB in amdgpu_bo_create->kzalloc. So it needs to switch kzalloc to kvzalloc. Call Trace: alloc_pages_current+0x6a/0xe0 kmalloc_order+0x32/0xb0 kmalloc_order_trace+0x1e/0x80 __kmalloc+0x249/0x2d0 amdgpu_bo_create+0x102/0x500 [amdgpu] ? xas_create+0x264/0x3e0 amdgpu_bo_create_vm+0x32/0x60 [amdgpu] amdgpu_vm_pt_create+0xf5/0x260 [amdgpu] amdgpu_vm_init+0x1fd/0x4d0 [amdgpu] Signed-off-by: Changfeng <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: soc15 register access through RLC should only apply to sriov runtimeshaoyunl1-2/+2
On SRIOV, driver should only access register through RLC in runtime Acked-by: Alex Deucher <[email protected]> Signed-off-by: shaoyunl <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: attr to control SS2.0 bias level (v2)Sathishkumar S4-0/+92
add sysfs attr to read/write smartshift bias level. document smartshift_bias sysfs attr. V2: add attr to amdgpu_device_attrs and use attr_update (Lijo) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: sysfs attrs to read ss powershare (v6)Sathishkumar S4-0/+129
add sysfs attrs to read smartshift APU and DGPU power share. document the sysfs device attributes. V2: change variable/macro name for stapm power limit (Lijo) V3: files to be exposed as sysfs device attributes (Alex) V4: check ret value of sysfs create and remove only if created. V5: add ss attrs in amdgpu_device_attrs and use attr_update (Lijo) V6: all checks for ss support to be in if else if statements. (Lijo) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Fix uninitialized field when expanding macro ↵Leslie Shi1-0/+1
MI_DCE12_MASK_SH_LIST Add back. Fixes: 0cadcf7c100161 ("drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK}") Signed-off-by: Leslie Shi <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/panfrost: Add AFBC_FEATURES parameterAlyssa Rosenzweig5-1/+7
The value of the AFBC_FEATURES register is required by userspace to determine AFBC support on Bifrost. A user on our IRC channel (#panfrost) reported a workload that raised a fault on one system's Mali G31 but worked flawlessly with another system's Mali G31. We determined the cause to be missing AFBC support on one vendor's Mali implementation -- it turns out AFBC is optional on Bifrost! Whether AFBC is supported or not is exposed in the AFBC_FEATURES register on Bifrost, which reads back as 0 on Midgard. A zero value indicates AFBC is fully supported, provided the architecture itself supports AFBC, allowing backwards-compatibility with Midgard. Bits 0 and 15 indicate that AFBC support is absent for texturing and rendering respectively. The user experiencing the fault reports that AFBC_FEATURES reads back 0x10001 on their system, confirming the architectural lack of AFBC. Userspace needs this parameter to know to disable AFBC on that chip, and perhaps others. v2: Fix typo from copy-paste fail. v3: Bump the UABI version. This commit was cherry-picked from another series so chalking this up to a rebase fail. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Steven Price <[email protected]> Cc: Rob Herring <[email protected]> Cc: Tomeu Vizoso <[email protected]> Signed-off-by: Steven Price <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/ttm: flip the switch for driver allocated resources v2Christian König16-189/+140
Instead of both driver and TTM allocating memory finalize embedding the ttm_resource object as base into the driver backends. v2: fix typo in vmwgfx grid mgr and double init in amdgpu_vram_mgr.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/vmwgfx: switch the TTM backends to self allocChristian König2-24/+31
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/nouveau: switch the TTM backends to self allocChristian König2-0/+5
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: switch the VRAM backend to self allocChristian König1-21/+30
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: switch the GTT backend to self allocChristian König1-14/+22
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdkfd: use resource cursor in svm_migrate_copy_to_vram v2Christian König1-58/+10
Access to the mm_node is now forbidden. So instead of hand wiring that use the cursor functionality. v2: fix handling as pointed out by Philip. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Reviewed-by and Tested-by: Philip Yang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: revert "drm/amdgpu: stop allocating dummy GTT nodes"Christian König1-29/+39
TTM is going to need this again since we are moving the resource allocation into the backend. Signed-off-by: Christian König <[email protected]> Acked-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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