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2016-03-14drm/nouveau/gr/gm200: switch over to using sw_method_init from firmwareBen Skeggs3-358/+1
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_bundle_init from firmwareBen Skeggs3-278/+1
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_ctx from firmwareBen Skeggs3-317/+1
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/bios/extdev: also parse v4.1 tableKarol Herbst1-1/+1
Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/hwmon: don't require therm to be valid to get any dataKarol Herbst1-20/+19
Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/hwmon: add power consumptionKarol Herbst2-0/+37
v2: expose only if the sensor reading is valid Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/iccsense: implement for ina209, ina219 and ina3221Karol Herbst8-1/+291
based on Martins initial work v3: fix ina2x9 calculations v4: don't kmalloc(0), fix the lsb/pga stuff v5: add a field to tell if the power reading may be invalid add nkvm_iccsense_read_all function check for the device on the i2c bus Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/nvbios/iccsense: add parsing of the SENSE tableMartin Peres3-0/+117
Karol Herbst: v4: don't kmalloc(0) v5: stricter validation Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres9-146/+216
Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Martin Peres <[email protected]>
2016-03-14drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot5-3/+242
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot6-7/+1674
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gm200: do not load firmware for secure falconsAlexandre Courbot1-6/+15
Secure falcons' firmware is managed by secboot. Do not load it in GR for them. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gf100: add support for securely-managed falconsAlexandre Courbot1-4/+24
Start securely-managed falcons using secboot functions since the process for them is different from just writing CPUCTL. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/core: add support for secure bootAlexandre Courbot9-0/+401
On GM200 and later GPUs, firmware for some essential falcons (notably GR ones) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to be able to access privileged registers, in a process known as Secure Boot. Secure Boot requires building a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to privileged mode. This patch adds infrastructure code to support this process on chips that require it. v2: - The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. - The falcon reset procedure expecting a falcon in an initialized state, which was accidentally provided by the PMU subdev. Make sure that secboot can manage the falcon on its own. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gm200: load external firmware and bundlesAlexandre Courbot5-29/+54
Load firmware and bundles in GM200's constructor. The previously called GF100 function did not care about the bundles. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gk20a: share external bundles loading functionsAlexandre Courbot2-3/+11
There functions are going to be used by other chips that rely on NVIDIA-provided firmware. Export them. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gk20a: simplify external bundle loading functionsAlexandre Courbot1-47/+73
Make these functions easier to use by handling memory management from within. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gf100: load firmware in outer functionAlexandre Courbot2-10/+22
The firmwares required by GR may vary from chip to chip, especially with the introduction of secure boot and NVIDIA-provided firmwares. Move the firmware loading outside of gf100_gr_ctor so other chips may still call it while managing their firmwares themselves. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gk20a: move firmware bundle release to gf100Alexandre Courbot4-19/+12
Some members of gf100_gr were freed by the gk20a driver. That's not where it should be done - free them in gf100 so other chips that use NVIDIA-provided firmware free these structures properly. This also removes the need for a GK20A-specific destructor. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/core: add gpuobj memcpy helper functionsAlexandre Courbot2-0/+24
Add memcpy functions to copy a buffer to a gpuobj and vice-versa. This will be used by the secure boot code. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gm200: enable graphics deviceBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gm200: s/gm204/gm200/Ben Skeggs10-128/+128
Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/bios/devinit: properly handle unknown generic conditionsBen Skeggs1-2/+3
Upon encountering an unknown condition code, the script interpreter is supposed to skip 'size' bytes and continue at the next devinit token. Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/bios/devinit: rename INIT_DP_CONDITION to INIT_GENERIC_CONDITIONBen Skeggs1-5/+5
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/ltc/gm107: fix slice intr offsetBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/devinit/gf100-: detect if BIOS invoked devinitAlexandre Courbot4-3/+16
It is not advisable to perform devinit if it has already been done. VBIOS will very likely have invoked devinit if the GPU is the primary graphics device, but there is no accurate way to detect this fact yet. This patch adds such a method for gf100 and later chips, by means of the NV_PTOP_SCRATCH1_DEVINIT_COMPLETED bit. This bit is set to 1 by devinit, and reset to 0 when the GPU is powered. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/devinit/nv50: remove unneeded variableAlexandre Courbot1-7/+6
We never use any nv50-specific member in this nv50_devinit_preinit(). Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau: s/gm204/gm200/ in a number of placesBen Skeggs39-150/+150
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau: recognise GM200 chipsetBen Skeggs1-0/+31
Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/device/tegra: fix uninitialized IRQ numberAlexandre Courbot1-1/+0
nvkm_device_tegra_new initializes the irq member of the Tegra device to -1 in order to signal that it is uninitialized. However, nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has been allocated or not. This leads to free_irq being called on -1 during device initialization. Fix this by using 0 as the uninitialized value everywhere. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/device: call nvkm_device_fini if nvkm_device_init failsAlexandre Courbot1-0/+2
nvkm_device_fini is never called if a failure occurs in nvkm_device_init, even when unloading the module. This can lead to a resources leak (one example is the Tegra interrupt which would never be freed in that case). Fix this by calling nvkm_device_fini in nvkm_device_init's failure path. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/gr/gf100: use the nvkm_firmware functionsAlexandre Courbot1-15/+3
Use the nvkm_firmware_* functions when loading external firmware to avoid duplicate code. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/core: add firmware handling functionsAlexandre Courbot3-0/+73
Add two functions nvkm_firmware_get() and nvkm_firmware_put() to load a firmware file and free its resources, respectively. Since firmware files are becoming a necessity for new GPUs, and their location has been standardized to nvidia/chip/, this will prevent duplicate and error-prone name-generation code. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-14drm/nouveau/ltc/gm107: wait on relevant bit in gm107_ltc_cbc_waitAlexandre Courbot1-4/+2
Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit of the CTRL1 register instead of writing it entirely in gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also be modified to wait on that single bit only, otherwise a timeout may occur if some other bit of that register is set. This happened at least on GM206 when running glmark2-drm. While we are at it, use the more compact nvkm_wait_msec() to wait for the bit to clear. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2016-03-13drm/vc4: Return -EFAULT on copy_from_user() failureDan Carpenter1-3/+4
The copy_from_user() function returns the number of bytes not copied but we want to return a negative error code. Fixes: 463873d57014 ('drm/vc4: Add an API for creating GPU shaders in GEM BOs.') Cc: [email protected] Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2016-03-13drm/vc4: Respect GPIO_ACTIVE_LOW on HDMI HPD if set in the devicetree.Eric Anholt1-2/+10
The original Raspberry Pi had the GPIO active high, but the later models are active low. The DT GPIO bindings allow specifying the active flag, except that it doesn't get propagated to the gpiodesc, so you have to handle it yourself. Signed-off-by: Eric Anholt <[email protected]> Tested-by: Daniel Stone <[email protected]>
2016-03-13drm/vc4: Let gpiolib know that we're OK with sleeping for HPD.Eric Anholt1-1/+1
Fixes an error thrown every few seconds when we poll HPD when it's on a I2C to GPIO expander. Signed-off-by: Eric Anholt <[email protected]> Tested-by: Daniel Stone <[email protected]>
2016-03-13drm/vc4: improve throughput by pipelining binning and rendering jobsVarad Gautam3-52/+166
The hardware provides us with separate threads for binning and rendering, and the existing model waits for them both to complete before submitting the next job. Splitting the binning and rendering submissions reduces idle time and gives us approx 20-30% speedup with some x11perf tests such as -line10 and -tilerect1. Improves openarena performance by 1.01897% +/- 0.247857% (n=16). Thanks to anholt for suggesting this. v2: Rebase on the spurious resets fix (change by anholt). Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2016-03-14Merge tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux into drm-nextDave Airlie3-3/+64
This pull request fixes the major VC4 HDMI modesetting bugs found when the first wave of users showed up in Raspbian. * tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux: drm/vc4: Initialize scaler DISPBKGND on modeset. drm/vc4: Fix setting of vertical timings in the CRTC. drm/vc4: Fix the name of the VSYNCD_EVEN register. drm/vc4: Add another reg to HDMI debug dumping. drm/vc4: Bring HDMI up from power off if necessary. drm/vc4: Fix a framebuffer reference leak on async flip interrupt.
2016-03-14Merge branch 'exynos-drm-next' of ↵Dave Airlie4-1/+31
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next * 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: drm/exynos: add DRM_EXYNOS_GEM_MAP ioctl
2016-03-14Merge drm-fixes into drm-next.Dave Airlie1064-8100/+12833
Nouveau wanted this to avoid some worse conflicts when I merge that.
2016-03-13drm: atomic helper: do not unreference error pointerLionel Landwerlin1-0/+1
562c5b4d8986 didn't quite fix the issue of dealing with an error pointer. We can't free/unref an error pointer so reset it to NULL. Many thanks to Dan Carpenter for pointing this out again. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: Dan Carpenter <[email protected]> Cc: Daniel Stone <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Matt Roper <[email protected]> Cc: [email protected] Fixes: 562c5b4d8986 ("drm: fix blob pointer check") Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-03-13drm/edid: Extract SADs properly from multiple audio data blocksVille Syrjälä1-6/+11
SADs may span multiple CEA audio data blocks in the EDID. CEA-861-E says: "The order of the Data Blocks is not constrained. It is also possible to have more than one of a specific type of data block if necessary to include all of the descriptors needed to describe the sink’s capabilities." Each audio data block can carry up to 10 SADs, whereas the ELD SAD limit is 15 according to HDA 1.0a spec. So we should support at least two data blocks. And apparently some devices take a more liberal interpretation and stuff only one SAD per data block even when they would fit into one. So let's try to extract all the SADs we can fit into the ELD even when they span multiple data blocks. While at it, toss in a comment to explain the 13 byte monitor name string limit which confused me at first. Cc: Arturo Pérez <[email protected]> Tested-by: Arturo Pérez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94197 Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-03-13drm/exynos: add DRM_EXYNOS_GEM_MAP ioctlJoonyoung Shim4-1/+31
The commit d931589c01a2 ("drm/exynos: remove DRM_EXYNOS_GEM_MAP_OFFSET ioctl") removed it same with the ioctl that this patch adds. The reason that removed DRM_EXYNOS_GEM_MAP_OFFSET was we could use DRM_IOCTL_MODE_MAP_DUMB. Both did exactly same thing. Now we again will revive it as DRM_EXYNOS_GEM_MAP because of render node. DRM_IOCTL_MODE_MAP_DUMB isn't permitted in render node. Signed-off-by: Joonyoung Shim <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2016-03-12Merge tag 'drm-intel-fixes-2016-03-11' of ↵Dave Airlie5-4/+9
git://anongit.freedesktop.org/drm-intel into drm-next Two i915 regression fixes. * tag 'drm-intel-fixes-2016-03-11' of git://anongit.freedesktop.org/drm-intel: drm/i915: Actually retry with bit-banging after GMBUS timeout drm/i915: Fix bogus dig_port_map[] assignment for pre-HSW
2016-03-11Merge tag 'armsoc-fixes' of ↵Linus Torvalds13-20/+41
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Two more fixes for 4.5: - One is a fix for OMAP that is urgently needed to avoid DRA7xx chips from premature aging, by always keeping the Ethernet clock enabled. - The other solves a I/O memory layout issue on Armada, where SROM and PCI memory windows were conflicting in some configurations" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory window ARM: dts: dra7: do not gate cpsw clock due to errata i877 ARM: OMAP2+: hwmod: Introduce ti,no-idle dt property
2016-03-11Merge tag 'media/v4.5-5' of ↵Linus Torvalds2-1/+28
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media fix from Mauro Carvalho Chehab: "One last time fix: It adds a code that prevents some media tools like media-ctl to hide some entities that have their IDs out of the range expected by those apps" * tag 'media/v4.5-5' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: [media] media-device: map new functions into old types for legacy API
2016-03-11ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory windowThomas Petazzoni9-19/+19
When the Crypto SRAM mappings were added to the Device Tree files describing the Armada XP boards in commit c466d997bb16 ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards"), the fact that those mappings were overlaping with the PCIe memory aperture was overlooked. Due to this, we currently have for all Armada XP platforms a situation that looks like this: Memory mapping on Armada XP boards with internal registers at 0xf1000000: - 0x00000000 -> 0xf0000000 3.75G RAM - 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB) - 0xf1000000 -> 0xf1100000 1M internal registers - 0xf8000000 -> 0xffe0000 126M PCIe memory aperture - 0xf8100000 -> 0xf8110000 64KB Crypto SRAM #0 => OVERLAPS WITH PCIE ! - 0xf8110000 -> 0xf8120000 64KB Crypto SRAM #1 => OVERLAPS WITH PCIE ! - 0xffe00000 -> 0xfff00000 1M PCIe I/O aperture - 0xfff0000 -> 0xffffffff 1M BootROM The overlap means that when PCIe devices are added, depending on their memory window needs, they might or might not be mapped into the physical address space. Indeed, they will not be mapped if the area allocated in the PCIe memory aperture by the PCI core overlaps with one of the Crypto SRAM. Typically, a Intel IGB PCIe NIC that needs 8MB of PCIe memory will see its PCIe memory window allocated from 0xf80000000 for 8MB, which overlaps with the Crypto SRAM windows. Due to this, the PCIe window is not created, and any attempt to access the PCIe window makes the kernel explode: [ 3.302213] igb: Copyright (c) 2007-2014 Intel Corporation. [ 3.307841] pci 0000:00:09.0: enabling device (0140 -> 0143) [ 3.313539] mvebu_mbus: cannot add window '4:f8', conflicts with another window [ 3.320870] mvebu-pcie soc:pcie-controller: Could not create MBus window at [mem 0xf8000000-0xf87fffff]: -22 [ 3.330811] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf08c0018 This problem does not occur on Armada 370 boards, because we use the following memory mapping (for boards that have internal registers at 0xf1000000): - 0x00000000 -> 0xf0000000 3.75G RAM - 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB) - 0xf1000000 -> 0xf1100000 1M internal registers - 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 => OK ! - 0xf8000000 -> 0xffe0000 126M PCIe memory - 0xffe00000 -> 0xfff00000 1M PCIe I/O - 0xfff0000 -> 0xffffffff 1M BootROM Obviously, the solution is to align the location of the Crypto SRAM mappings of Armada XP to be similar with the ones on Armada 370, i.e have them between the "internal registers" area and the beginning of the PCIe aperture. However, we have a special case with the OpenBlocks AX3-4 platform, which has a 128 MB NOR flash. Currently, this NOR flash is mapped from 0xf0000000 to 0xf8000000. This is possible because on OpenBlocks AX3-4, the internal registers are not at 0xf1000000. And this explains why the Crypto SRAM mappings were not configured at the same place on Armada XP. Hence, the solution is two-fold: (1) Move the NOR flash mapping on Armada XP OpenBlocks AX3-4 from 0xe8000000 to 0xf0000000. This frees the 0xf0000000 -> 0xf80000000 space. (2) Move the Crypto SRAM mappings on Armada XP to be similar to Armada 370 (except of course that Armada XP has two Crypto SRAM and not one). After this patch, the memory mapping on Armada XP boards with registers at 0xf1 is: - 0x00000000 -> 0xf0000000 3.75G RAM - 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB) - 0xf1000000 -> 0xf1100000 1M internal registers - 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 - 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1 - 0xf8000000 -> 0xffe0000 126M PCIe memory - 0xffe00000 -> 0xfff00000 1M PCIe I/O - 0xfff0000 -> 0xffffffff 1M BootROM And the memory mapping for the special case of the OpenBlocks AX3-4 (internal registers at 0xd0000000, NOR of 128 MB): - 0x00000000 -> 0xc0000000 3G RAM - 0xd0000000 -> 0xd1000000 1M internal registers - 0xe800000 -> 0xf0000000 128M NOR flash - 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 - 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1 - 0xf8000000 -> 0xffe0000 126M PCIe memory - 0xffe00000 -> 0xfff00000 1M PCIe I/O - 0xfff0000 -> 0xffffffff 1M BootROM Fixes: c466d997bb16 ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards") Reported-by: Phil Sutter <[email protected]> Cc: Phil Sutter <[email protected]> Cc: <[email protected]> Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Gregory CLEMENT <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2016-03-11Merge tag 'dmaengine-fix-4.5' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2-3/+41
Pull dmaengine fixes from Vinod Koul: "Two fixes showed up in last few days, and they should be included in 4.5. Summary: Two more late fixes to drivers, nothing major here: - A memory leak fix in fsdma unmap the dma descriptors on freeup - A fix in xdmac driver for residue calculation of dma descriptor" * tag 'dmaengine-fix-4.5' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: at_xdmac: fix residue computation dmaengine: fsldma: fix memory leak
2016-03-11Merge tag 'pm+acpi-4.5-final' of ↵Linus Torvalds2-9/+8
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management and ACPI fixes from Rafael Wysocki: "Two more fixes for issues introduced recently, one in the generic device properties framework and one in ACPICA. Specifics: - Revert a recent ACPICA commit that has been reverted upstream, because it caused problems to happen on user systems and the problem it attempted to address will not be relevant any more after upcoming ACPI specification changes (Bob Moore). - Fix crash in the generic device properties framework introduced by a recent change that forgot to check pointers against error values in addition to checking them against NULL (Heikki Krogerus)" * tag 'pm+acpi-4.5-final' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: device property: fwnode->secondary may contain ERR_PTR(-ENODEV) ACPICA: Revert "Parser: Fix for SuperName method invocation"
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