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2013-05-09ARC: [mm] Aliasing VIPT dcache support 3/4Vineet Gupta2-2/+4
Fix the one zillion warnings Signed-off-by: Vineet Gupta <[email protected]>
2013-05-09ARC: [mm] Aliasing VIPT dcache support 2/4Vineet Gupta6-22/+223
This is the meat of the series which prevents any dcache alias creation by always keeping the U and K mapping of a page congruent. If a mapping already exists, and other tries to access the page, prev one is flushed to physical page (wback+inv) Essentially flush_dcache_page()/copy_user_highpage() create K-mapping of a page, but try to defer flushing, unless U-mapping exist. When page is actually mapped to userspace, update_mmu_cache() flushes the K-mapping (in certain cases this can be optimised out) Additonally flush_cache_mm(), flush_cache_range(), flush_cache_page() handle the puring of stale userspace mappings on exit/munmap... flush_anon_page() handles the existing U-mapping for anon page before kernel reads it via the GUP path. Note that while not complete, this is enough to boot a simple dynamically linked Busybox based rootfs Signed-off-by: Vineet Gupta <[email protected]>
2013-05-09ARC: [mm] Aliasing VIPT dcache support 1/4Vineet Gupta3-18/+34
This preps the low level dcache flush helpers to take vaddr argument in addition to the existing paddr to properly flush the VIPT dcache Signed-off-by: Vineet Gupta <[email protected]>
2013-05-09ARM: dts: don't assume boards are using twl4030 for omap3Jason Cooper4-1/+3
If a board isn't using twl4030, then dtc will complain about the missing phandle (which is in twl4030.dtsi). Move the phy declaration to the dts files. Signed-off-by: Jason Cooper <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2013-05-09ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.cTony Lindgren1-3/+2
Commit 6770b211 (ARM: OMAP2+: Export SoC information to userspace) had some broken return value handling as noted by Russell King: + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR_OR_NULL(soc_dev)) { + kfree(soc_dev_attr); + return; + } + + parent = soc_device_to_device(soc_dev); + if (!IS_ERR_OR_NULL(parent)) + device_create_file(parent, &omap_soc_attr); This is nonsense. For the first, IS_ERR() is sufficient. For the second, tell me what error checking is required in the return value of this function: struct device *soc_device_to_device(struct soc_device *soc_dev) { return &soc_dev->dev; } when you've already determined that the passed soc_dev is a valid pointer. If you read the comments against the prototype: /** * soc_device_to_device - helper function to fetch struct device * @soc: Previously registered SoC device container */ struct device *soc_device_to_device(struct soc_device *soc); if "soc" is valid, it means the "previously registered SoC device container" must have succeeded and that can only happen if the struct device has been registered. Ergo, there will always be a valid struct device pointer for any registered SoC device container. Therefore, if soc_device_register() succeeds, then the return value from soc_device_to_device() will always be valid and no error checking of it is required. Simples. The rule as ever applies here: get to know the APIs your using and don't fumble around in the dark hoping that you'll get this stuff right. Fix it as noted by Russell. Reported-by: Russell King <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2013-05-09Merge branch 'mti-next' of ↵Ralf Baechle90-1416/+5835
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2013-05-09Merge branch 'next/kvm' into mips-for-linux-nextRalf Baechle42-18/+7412
2013-05-09MIPS: Add new GIC clockevent driver.Raghu Gandham8-2/+163
Add new clockevent driver that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Raghu Gandham <[email protected]> Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: Formatting clean-ups for clocksources.Steven J. Hill3-10/+2
Various whitespace and #ifdef removals for GIC and R4K clocksources. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: Refactor GIC clocksource code.Steven J. Hill6-25/+48
Reorganize some of the GIC clocksource driver code. Below is a list of the various changes. * No longer select CSRC_GIC by default for Malta platform. * Limit choice for either the GIC or R4K clocksource, not both. * Change location in Makefile. * Created new 'gic_read_count' function in common 'irq-gic.c' file. * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function. * Surround GIC specific code in Malta platform code with #ifdef's. * Only initialize the GIC clocksource if it was selected. Original code called it unconditionally if a GIC was found. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: Move 'gic_frequency' to common location.Steven J. Hill3-1/+2
Move the global variable 'gic_frequency' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: Move 'gic_present' to common location.Steven J. Hill5-5/+3
Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: MIPS16e: Add unaligned access support.Steven J. Hill1-0/+255
Add logic needed to handle unaligned accesses in MIPS16e mode. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]>
2013-05-09MIPS: MIPS16e: Support handling of delay slots.Steven J. Hill3-5/+119
Add logic needed to properly calculate exceptions for delay slots when in MIPS16e mode. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: MIPS16e: Add instruction formats.Steven J. Hill1-0/+110
Add structures for all the MIPS16e instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Optimise 'strnlen' core library function.Steven J. Hill1-1/+1
Optimise 'strnlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Optimise 'strlen' core library function.Steven J. Hill1-4/+5
Optimise 'strlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Optimise 'strncpy' core library function.Steven J. Hill1-15/+17
Optimise 'strncpy' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Optimise 'memset' core library function.Steven J. Hill2-30/+56
Optimise 'memset' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Add configuration option for microMIPS kernel.Steven J. Hill5-3/+134
This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Disable LL/SC and fix linker bug.Steven J. Hill2-2/+16
Partially revert commit e0c14a260d66ba35935600d6435940a566fe806b and turn off LL/SC when building a pure microMIPS kernel. This is a temporary fix until the cmpxchg assembly macro functions are re-written to not use the HI/LO registers in address calculations. Also add .insn in selected user access functions which would otherwise produce ISA mode jump incompatibilities. This is also a temporary fix. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Add vdso support.Douglas Leung1-0/+9
Support vdso in microMIPS mode. Signed-off-by: Douglas Leung <[email protected]> Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Add unaligned access support.Leonid Yegoshin2-201/+1112
Add logic needed to handle unaligned accesses in microMIPS mode. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]>
2013-05-09MIPS: microMIPS: Support handling of delay slots.Leonid Yegoshin2-5/+102
Add logic needed to properly calculate exceptions for delay slots when in microMIPS mode. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Add support for exception handling.Steven J. Hill9-107/+353
All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Floating point support.Leonid Yegoshin7-100/+893
Add logic needed to do floating point emulation in microMIPS mode. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Steven J. Hill <Steven. [email protected]>
2013-05-09MIPS: microMIPS: Fix macro naming in micro-assembler.Steven J. Hill2-2/+25
The macros did not properly take into account the ISA that the kernel was being compiled with. A classic MIPS kernel will have the standard 'uasm_i_##op' macro functions with 'MM_uasm_i_##op' macro functions for the microMIPS version. A pure microMIPS kernel will have the standard macros with 'CL_uasm_i_##op' macro functions for the classic version. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09MIPS: microMIPS: Fix incorrect mask for jump immediate.Steven J. Hill1-1/+2
Jump or branch target addresses have the first bit set. The original mask did not take this into account and will cause a field overflow warning for the target address when a jump immediate instruction is built. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-09KVM/MIPS32: Binary patching of select privileged instructions.Sanjay Lal3-0/+209
Currently, the following instructions are translated: - CACHE (indexed) - CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations, but still much faster than a trap. - mfc0/mtc0: the virtual COP0 registers for the guest are implemented as 2-D array. [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0. mfc0/mtc0 operations are transformed to load/stores. Signed-off-by: Sanjay Lal <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Ralf Baechle <[email protected]>
2013-05-09KVM/MIPS32: Do not call vcpu_load when injecting interrupts.Sanjay Lal1-1/+1
Signed-off-by: Sanjay Lal <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Ralf Baechle <[email protected]>
2013-05-09EDAC: Don't give write permission to read-only filesSrivatsa S. Bhat1-6/+6
I get the following warning on boot: ------------[ cut here ]------------ WARNING: at drivers/base/core.c:575 device_create_file+0x9a/0xa0() Hardware name: -[8737R2A]- Write permission without 'store' ... </snip> Drilling down, this is related to dynamic channel ce_count attribute files sporting a S_IWUSR mode without a ->store() function. Looking around, it appears that they aren't supposed to have a ->store() function. So remove the bogus write permission to get rid of the warning. Signed-off-by: Srivatsa S. Bhat <[email protected]> Cc: Mauro Carvalho Chehab <[email protected]> Cc: <[email protected]> # 3.[89] [ shorten commit message ] Signed-off-by: Borislav Petkov <[email protected]>
2013-05-09bfin cache: dcplb map: add 16M dcplb map for BF60xSteven Miao4-9/+45
use 16M data cplb map on BF60x to avoid too much dcplb miss overhead cleanup cplb info Signed-off-by: Steven Miao <[email protected]>
2013-05-09ARC: [mm] refactor the core (i|d)cache line ops loopsVineet Gupta1-29/+24
Nothing semantical * simplify the alignement code by using & operation only * rename variables clearly as paddr Signed-off-by: Vineet Gupta <[email protected]>
2013-05-09microblaze: Enable IRQ in arch_cpu_idleMichal Simek1-0/+5
Microblaze requires to enable IRQ in cpu_idle loop. It should be the part of this patch: "microblaze: Use generic idle loop" (sha1: e962bb9e9cf73b8c8893c95903e791dd5ec19fb4) Signed-off-by: Michal Simek <[email protected]>
2013-05-09ARC: [mm] serious bug in vaddr based icache flushVineet Gupta1-1/+1
vaddr used to index the cache was clipped from the wrong end, and thus would potentially fail to flush the correct lines. The problem was dorment for so long because up until the recent optimizations it was only used for ptrace break-point only flushes. Signed-off-by: Vineet Gupta <[email protected]>
2013-05-09xtensa: Switch to asm-generic/linkage.hGeert Uytterhoeven2-16/+1
Signed-off-by: Geert Uytterhoeven <[email protected]>
2013-05-09xtensa: fix redboot load addressChris Zankel1-1/+1
With the patch to support MMUv3, the base address for the loaded binary image has changed, and a fix was applied to the U-Boot image. This fixes the RedBoot image. Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: ISS: fix timer_lock usage in rs_openMax Filippov1-2/+2
This fixes the following lockdep splat: [ 66.460000] ================================= [ 66.460000] [ INFO: inconsistent lock state ] [ 66.460000] 3.9.0-rc5-00161-ga48dd49 #4 Not tainted [ 66.460000] --------------------------------- [ 66.460000] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage. [ 66.460000] swapper/1 [HC0[0]:SC1[1]:HE1:SE0] takes: [ 66.460000] (timer_lock){+.?...}, at: [<d0006cde>] rs_poll+0x12/0xdc [ 66.460000] {SOFTIRQ-ON-W} state was registered at: [ 66.460000] [<d00421f0>] lock_acquire+0xec/0x13c [ 66.460000] [<d01ea036>] _raw_spin_lock+0x3a/0x84 [ 66.460000] [<d0006c8c>] rs_open+0x18/0x58 [ 66.460000] [<d0139ea2>] tty_open+0x262/0x3cc [ 66.460000] [<d00942e0>] chrdev_open+0x8c/0xe0 [ 66.460000] [<d00907b2>] do_dentry_open$isra$16+0x10e/0x190 [ 66.460000] [<d0091141>] finish_open+0x39/0x48 [ 66.460000] [<d009a0b4>] do_last$isra$34+0x6c4/0x824 [ 66.460000] [<d009a27a>] path_openat+0x66/0x310 [ 66.460000] [<d009a53a>] do_filp_open+0x16/0x44 [ 66.460000] [<d0091445>] do_sys_open+0xd5/0x13c [ 66.460000] [<d00914be>] sys_open+0x12/0x18 [ 66.460000] [<d0413ffc>] kernel_init_freeable+0xe4/0x12c [ 66.460000] [<d01e2a9c>] kernel_init+0xc/0x9c [ 66.460000] [<d00044fc>] ret_from_kernel_thread+0x8/0xc [ 66.460000] irq event stamp: 132542 [ 66.460000] hardirqs last enabled at (132542): [<d01ea2ec>] _raw_spin_unlock_irq+0x30/0x44 [ 66.460000] hardirqs last disabled at (132541): [<d01ea11e>] _raw_spin_lock_irq+0xe/0x8c [ 66.460000] softirqs last enabled at (132234): [<d0017d32>] __do_softirq+0x216/0x2a4 [ 66.460000] softirqs last disabled at (132539): [<d0018024>] irq_exit+0x38/0x40 [ 66.460000] [ 66.460000] other info that might help us debug this: [ 66.460000] Possible unsafe locking scenario: [ 66.460000] [ 66.460000] CPU0 [ 66.460000] ---- [ 66.460000] lock(timer_lock); [ 66.460000] <Interrupt> [ 66.460000] lock(timer_lock); [ 66.460000] [ 66.460000] *** DEADLOCK *** [ 66.460000] [ 66.460000] 1 lock held by swapper/1: [ 66.460000] #0: (((&serial_timer))){+.-...}, at: [<d001c65c>] call_timer_fn+0x0/0x1f0 [ 66.460000] Stack: d7c2fac0 00000018 00000004 00000001 d7c2faa0 00000004 00000006 d7c2fa90 9003e87c d7c2fae0 d7c30000 d025a87c 00000001 0000000f 00000000 d7c2fac0 9004005d d7c2fb10 d7c30000 d7c30338 00000001 00000001 00000000 d7c30338 [ 66.460000] Call Trace: [ 66.460000] [<d01e4f93>] print_usage_bug$part$26+0x1c3/0x1c8 [ 66.460000] [<d003e87c>] mark_lock+0x2b4/0x440 [ 66.460000] [<d004005d>] __lock_acquire+0x54d/0x16c4 [ 66.460000] [<d00421f0>] lock_acquire+0xec/0x13c [ 66.460000] [<d01ea036>] _raw_spin_lock+0x3a/0x84 [ 66.460000] [<d0006cde>] rs_poll+0x12/0xdc [ 66.460000] [<d001c71a>] call_timer_fn+0xbe/0x1f0 [ 66.460000] [<d001cd90>] run_timer_softirq+0x198/0x1f4 [ 66.460000] [<d0017c30>] __do_softirq+0x114/0x2a4 [ 66.460000] [<d0018024>] irq_exit+0x38/0x40 [ 66.460000] [<d00046c0>] do_IRQ+0x44/0x48 [ 66.460000] [<d0005c58>] do_interrupt+0x4c/0x54 [ 66.460000] [<d0003c80>] common_exception_return+0x0/0x5c [ 66.460000] [<d006682c>] free_pcppages_bulk+0x254/0x308 [ 66.460000] Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: disable IRQs while IRQ handler is runningMax Filippov3-55/+28
IRQ handlers are expected to run with IRQs disabled. See e.g. http://lwn.net/Articles/380931/ for a longer story. This was overlooked in the commit 2d1c645 xtensa: dispatch medium-priority interrupts Revert to old behavior and simplify interrupt entry and exit code. Interrupt handler still honours IRQ priority. do_notify_resume/schedule must be called with interrupts enabled, enable interrupts if we return from user exception. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: enable lockdep supportMax Filippov1-3/+4
Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: fix arch_irqs_disabled_flags implementationMax Filippov1-1/+4
IRQs are disabled when PS.EXCM is set or PS.INTLEVEL is equal to or higher than LOCKLEVEL. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: add irq flags trace supportMax Filippov2-0/+35
Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: provide custom CALLER_ADDR* implementationsMax Filippov2-1/+66
Definition of CALLER_ADDR* through __builtin_return_address makes compiler insert calls to __xtensa_libgcc_window_spill, which in turn makes fast_syscall_spill_registers syscall that clobbers registers when called from the kernel mode, leading to invalid opcode exceptions on return to userspace. Provide definition for CALLER_ADDR0 as MAKE_PC_FROM_RA(a0, a1) and in case CONFIG_FRAME_POINTER is enabled extract CALLER_ADDR{1-3} from stack. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: add stacktrace supportMax Filippov5-41/+140
Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: clean up stpill_registersMax Filippov1-3/+2
- remove unused asm parameters; - fix EXCM bit setting in the PS SR during _spill_registers call. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: don't use a7 in simcallsMax Filippov3-18/+18
To support FRAME_POINTER avoid using a7 in __simc (none of the existing simcalls needs it). Replace calls to __simc with more specific simc_read, simc_write and simc_lseek calls. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: don't attempt to use unconfigured timersMax Filippov1-3/+6
Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: provide default platform_pcibios_init implementationMax Filippov2-6/+1
This fixes the following build error: arch/xtensa/kernel/built-in.o:(.init.literal+0xe8): undefined reference to `platform_pcibios_init' arch/xtensa/kernel/built-in.o: In function `setup_arch': (.init.text+0x20e): undefined reference to `platform_pcibios_init' and allows platform to omit definition of platform_pcibios_init if it's empty. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: remove KCORE_ELF againPaul Bolle1-15/+0
The Kconfig symbol KCORE_ELF was removed in v2.6.0, but reappeared in two architectures. It is useless. Remove it again. Signed-off-by: Paul Bolle <[email protected]> Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
2013-05-09xtensa: document MMUv3 setup sequenceMax Filippov1-0/+46
Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Chris Zankel <[email protected]>
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