aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-07-08arm64: tegra: Enable native timers on Tegra186Kartik1-1/+1
Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs. Signed-off-by: Kartik <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Add node for CBB 2.0 on Tegra234Sumit Gupta1-0/+42
Tegra234 uses the Control Backbone (CBB) version 2.0. Add the nodes that enable error handling from the various CBB 2.0 fabrics found on Tegra234. Signed-off-by: Sumit Gupta <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Add node for CBB 1.0 on Tegra194Sumit Gupta1-1/+61
Add device tree nodes to enable error handling on the Control Backbone (CBB). Tegra194 uses CBB version 1.0. Signed-off-by: Sumit Gupta <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Align gpio-keys node names with dtschemaKrzysztof Kozlowski10-26/+26
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Mark BPMP channels as no-memory-wcMikko Perttunen3-0/+3
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues. Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map. Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed. As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory. Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <[email protected]> Reviewed-by: Yousaf Kaukab <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Add Tegra234 GPCDMA device tree nodeAkhil R1-0/+42
Add device tree nodes for Tegra234 GPCDMA Signed-off-by: Akhil R <[email protected]> Reviewed-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Adjust whitespace around '='Krzysztof Kozlowski1-1/+1
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Enable OPE on various platformsSameer Pujar6-0/+340
Enable OPE module usage on various Jetson platforms. This can be plugged into an audio path using ALSA mixer controls. Add audio-graph-port binding to use OPE device with generic audio-graph based sound card. Signed-off-by: Sameer Pujar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: tegra: Add OPE device on Tegra210 and laterSameer Pujar4-0/+109
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08Merge branch 'for-5.20/dt-bindings' into for-5.20/arm64/dtThierry Reding9-1/+463
2022-07-08dt-bindings: tegra-ccplex-cluster: Remove status from required propertiesThierry Reding1-1/+0
The "status" property is implied to be "okay" if it isn't present, so do not mark it as required. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: Add headers for Host1x and VIC on Tegra234Mikko Perttunen4-0/+11
Add clock, memory controller, powergate and reset dt-binding headers for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: timer: Add Tegra186 & Tegra234 TimerKartik1-0/+109
The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08Merge tag 'renesas-dt-bindings-for-v5.20-tag2' of ↵Arnd Bergmann2-1/+4
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.20 (take two) - Miscellaneous fixes and improvements. * tag 'renesas-dt-bindings-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: hwinfo: renesas,prr: move from soc directory MAINTAINERS: Add Renesas SoC DT bindings to Renesas Architecture sections Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-07-08Merge tag 'renesas-arm-dt-for-v5.20-tag2' of ↵Arnd Bergmann20-57/+555
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.20 (take two) - Ethernet MAC and switch support for the RZ/N1 SoC on the RZN1D-DB development board, - AA1024XD12 panel overlay support for the Draak, Ebisu, and Salvator-X(S) development boards, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Add panel overlay for Draak and Ebisu boards arm64: dts: renesas: Add panel overlay for Salvator-X(S) boards arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay support arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order ARM: dts: r9a06g032-rzn1d400-db: Add switch description dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter ARM: dts: r9a06g032: Describe switch ARM: dts: r9a06g032: Describe GMAC2 ARM: dts: r9a06g032: Describe MII converter arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in comment ARM: dts: renesas: Fix DA9063 watchdog subnode names arm64: dts: renesas: r8a779m8: Drop operating points above 1.5 GHz Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-07-08arm64: dts: freescale: imx8qxp: Fix the keys node nameAbel Vesa1-1/+1
The proper name is 'keys', not 'scu-keys'. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08arm64: dts: freescale: imx8: Fix the system-controller node nameViorel Suman2-2/+2
The proper name is 'system-controller', not 'scu'. Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08arm64: dts: freescale: imx8qxp: Fix the ocotp node nameViorel Suman1-1/+1
The proper name is 'ocotp', not 'imx8qx-ocotp'. Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controllerAbel Vesa1-1/+1
Both i.MX8QM and i.MX8DXL use the fallback fsl,scu-clk compatible. They rely on the same driver generic part as the i.MX8QXP, so lets add it to i.MX8QXP too, for consitency. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08arm64: dts: freescale: imx8: Fix power controller nameAbel Vesa2-2/+2
The proper name is power-controller, not imx8qx-pd. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entriesViorel Suman1-2/+0
XTAL clocks are not exposed by SCU to OS via OS<->SCU communication protocol, so remove unnecessary entries. Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: firmware: Add fsl,scu yaml fileAbel Vesa2-96/+210
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch adds the fsl,scu.yaml in the firmware bindings folder. This one is only for the main SCU node. The old txt file will be removed only after all the child nodes have been properly switch to yaml. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: watchdog: Add fsl,scu-wdt yaml fileAbel Vesa2-15/+34
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'watchdog' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Guenter Roeck <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: thermal: Add fsl,scu-thermal yaml fileAbel Vesa2-16/+38
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'thermal' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: rtc: Add fsl,scu-rtc yaml fileAbel Vesa2-10/+31
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'rtc' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: power: Add fsl,scu-pd yaml fileAbel Vesa2-25/+41
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'power controller' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: nvmem: Add fsl,scu-ocotp yaml fileAbel Vesa2-24/+56
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'ocotp' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: input: Add fsl,scu-key yaml fileAbel Vesa2-14/+40
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'keys' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml fileAbel Vesa2-40/+74
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'iomux/pinctrl' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: clk: imx: Add fsl,scu-clk yaml fileAbel Vesa2-31/+43
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'clock' child node of the SCU main node. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Acked-by: Stephen Boyd <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB 2.0 bindingSumit Gupta1-0/+74
Add device-tree binding documentation to represent the Control Backbone (CBB) version 2.0 used on Tegra234 SoCs. Signed-off-by: Sumit Gupta <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra194 AXI2APB bindingSumit Gupta1-0/+40
Add device-tree binding documentation to represent the AXI2APB bridges used by Control Backbone (CBB) 1.0 on Tegra194 SoCs. All errors for APB slaves are reported as slave error because APB bas single bit to report error. So, CBB driver needs to further check error status registers of all the AXI2APB bridges to find error type. Signed-off-by: Sumit Gupta <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB 1.0 bindingSumit Gupta1-0/+97
Add device-tree binding documentation to represent the Control Backbone (CBB) version 1.0 used on Tegra194 SoCs. Signed-off-by: Sumit Gupta <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: memory: Add Tegra234 MGBE memory clientsThierry Reding1-0/+20
Add the memory client and stream ID definitions for the MGBE hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Bhadram Varka <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: Add Tegra234 MGBE clocks and resetsThierry Reding2-0/+109
Add the clocks and resets used by the MGBE Ethernet hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Bhadram Varka <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08dt-bindings: power: Add Tegra234 MGBE power domainsThierry Reding1-0/+1
Add power domain IDs for the four MGBE power partitions found on Tegra234. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Bhadram Varka <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-07-08arm64: dts: imx8mp: add NoC nodePeng Fan1-0/+20
Add i.MX8MP NoC node to make the interconnect i.MX8MP driver could work. Currently dynamic frequency scaling of the i.MX8MP NoC has not been supported, only NoC initial settings are configured by interconnect driver. Signed-off-by: Peng Fan <[email protected]> Acked-by: Georgi Djakov <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2022-07-08Merge tag 'zynqmp-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann8-7/+94
arm/dt arm64: dts: ZynqMP DT changes for v5.20 - Extend gpio-zynq DT binding (compatible, power-domains, gpio-line-names) - Fix sm-k26 gpio comment - Wire AMS device - Align gpio-keys node names with dtschema * tag 'zynqmp-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: arm64: dts: xilinx: align gpio-key node names with dtschema arm64: dts: zynqmp: add AMS driver to device tree dt-bindings: gpio: zynq: Describe gpio-line-names arm64: zynqmp: Fix comment about number of gpio line names dt-bindings: gpio: zynq: Add power-domains dt-bindings: gpio: zynq: Add missing compatible strings Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-07-08Merge tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann2-3/+3
arm/dt ARM: Zynq DT changes for v5.20 - Align gpio-keys node names with dtschema * tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: ARM: dts: xilinx: align gpio-key node names with dtschema Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-07-07arm64: dts: mt8183: Add panel rotationHsin-Yi Wang1-0/+1
krane, kakadu, and kodama boards have a default panel rotation. Signed-off-by: Hsin-Yi Wang <[email protected]> Reviewed-by: Enric Balletbo i Serra <[email protected]> Tested-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mt7622: fix BPI-R64 WPS buttonNick Hainke1-1/+1
The bananapi R64 (BPI-R64) experiences wrong WPS button signals. In OpenWrt pushing the WPS button while powering on the device will set it to recovery mode. Currently, this also happens without any user interaction. In particular, the wrong signals appear while booting the device or restarting it, e.g. after doing a system upgrade. If the device is in recovery mode the user needs to manually power cycle or restart it. The official BPI-R64 sources set the WPS button to GPIO_ACTIVE_LOW in the device tree. This setting seems to suppress the unwanted WPS button press signals. So this commit changes the button from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW. The official BPI-R64 sources can be found on https://github.com/BPI-SINOVOIP/BPI-R64-openwrt Fixes: 0b6286dd96c0 ("arm64: dts: mt7622: add bananapi BPI-R64 board") Suggested-by: INAGAKI Hiroshi <[email protected]> Signed-off-by: Nick Hainke <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mt8173: Fix nor_flash nodeXiangsheng Hou1-2/+5
Add axi clock since the driver change to DMA mode which need to enable axi clock. And change spi clock to 26MHz as default. Signed-off-by: Xiangsheng Hou <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4AngeloGioacchino Del Regno4-0/+40
This platform carries a HID compatible I2C touchscreen on the i2c4 bus, but it may be at a different address, depending on the board model. Add the node for a touchscreen at 0x10, but enable it only in the final board dts. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Enable support for the SPI NOR flashAngeloGioacchino Del Regno1-0/+31
This platform has a SPI NOR: enable support for it, completing the storage compartment enablement for the entire platform. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7AngeloGioacchino Del Regno1-0/+20
All devices of the Cherry platform have a MT6360 sub-pmic, providing two LDOs. Add the required node to enable the PMIC but without regulators yet, as these will be added in a later commit. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllersAngeloGioacchino Del Regno1-0/+55
Add USB functionality by enabling the required PHYs and the XHCI controllers. This enables all of the supported USB ports on the Cherry boards. Please note that u3phy1 also enables u3port1, which is configured to be a PCI-Express PHY for the second PCIe controller that is found on the MT8195 SoC, which will be enabled in a later commit. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Enable I2C and SPI controllersAngeloGioacchino Del Regno1-0/+148
This platform uses eight I2C controllers and one SPI controller: in preparation for enabling devices attached to these controllers, add basic configuration to enable the busses. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Document gpios and add default pin configAngeloGioacchino Del Regno3-0/+239
Add gpio-line-names to document GPIO names and add the default basic pin configuration to allow lower power operation by setting appropriate state on the unused pins. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Add support for internal eMMC storageAngeloGioacchino Del Regno1-0/+87
Add mtk-sd controller and pin configuration to enable the internal eMMC storage: now it is possible to mount a rootfs located at the internal storage. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2022-07-07arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMICAngeloGioacchino Del Regno1-0/+4
To allow MT6359 peripherals to trigger interrupts and the driver to safely handle them, assign the right interrupt line for the Cherry platform to the MT6359 PMIC node. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.