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2018-07-05drm/amd/display: fix dcn1 watermark range reportingDmytro Laktyushkin1-84/+18
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Moving powerplay functions to a separate classMikita Lipski3-493/+526
Moving powerplay functions to a new amdgpu_dm_pp_smu class and cleaning dm_services class from unused headers. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: move dml defaults to respective dcn resource filesDmytro Laktyushkin2-61/+64
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Convert 10kHz clks from PPLib into kHzMikita Lipski1-6/+9
The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Add dmpp clks types for conversionMikita Lipski1-23/+18
Add more cases for dm_pp clks translator into pp clks so we can pass the right structures to the powerplay. Use clks translator instead of massive switch statement. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Enable PPLib calls from DC on linuxMikita Lipski1-1/+1
Set the powerplay debug flag to false for both Windows and Linux to allow the calls to pplib. So we can retrieve the clock values from powerplay instead of using default hardcoded values. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: fix potential infinite loop in fbc pathRoman Li1-2/+2
- Fixing integer overflow bug in wait_for_fbc_state_changed() - Correct the max value of retries for the corresponding warning Signed-off-by: Roman Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: dal 3.1.51Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: clean rq/dlg/ttu reg structs before calculationsDmytro Laktyushkin3-4/+10
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: dal 3.1.50Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Add front end for dp debugfs filesDavid Francis4-1/+215
As part of hardware certification, read-write access to the link rate, lane count, voltage swing, pre-emphasis, and PHY test pattern of DP connectors is required. This commit adds debugfs files that will correspond to these values. The file operations are not yet implemented: currently writing or reading them does nothing. Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: dal 3.1.49Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: fix use of uninitialized memoryWesley Chalmers1-0/+2
DML does not calculate chroma values for RQ when surface is not YUV, but DC will unconditionally use the uninitialized values for HW programming. This does not cause visual corruption since HW will ignore garbage chroma values when surface is not YUV, but causes presubmission tests to fail golden value comparison. Signed-off-by: Wesley Chalmers <[email protected]> Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: support ACrYCb2101010Zheng, XueLai(Eric)2-1/+2
Signed-off-by: XueLai(Eric), Zheng <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: add safe_to_lower support to dcn wm programmingDmytro Laktyushkin3-138/+214
This will prevent watermarks from lowering when unsafe to do so. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: change dentist DID enum values to uppercaseDmytro Laktyushkin1-25/+25
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: add CHG_DONE mash/sh defines for dentistDmytro Laktyushkin1-2/+6
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: fix pplib voltage requestDmytro Laktyushkin1-27/+32
This fixes incorrect clock caching and by extension fixes the clock reporting. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: fix dccg dcn1 ifdefDmytro Laktyushkin2-4/+8
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Define dp_alt_modeCharlene Liu3-29/+24
Also cleanup command_table2.c. No need for a lot of forward declarations. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Temporarily remove Chroma logsWesley Chalmers1-6/+2
To ensure tests continue to pass Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Shahin Khayyer <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: remove unnecessary pplib volage requests that are assertingDmytro Laktyushkin1-8/+0
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: clean up set_bandwidth usageDmytro Laktyushkin3-18/+3
This removes redundant set_bandwidth calls as well as fixes a bug in post_set_address_update where dcn1 would never get to lower clocks. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: rename dce_disp_clk to dccgDmytro Laktyushkin7-95/+88
No functional change. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: clean up dccg divider calc and dcn constructorDmytro Laktyushkin2-155/+68
No functional change. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: move dcn1 dispclk programming to dccgDmytro Laktyushkin4-115/+90
No functional change. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: get rid of cur_clks from dcn_bw_outputDmytro Laktyushkin6-74/+72
Cleans up dcn_bw_output to only contain calculated info, actual programmed values will now be stored in respective blocks. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Add clock types to applying clk for voltageMikita Lipski1-0/+8
Add DCF and FCLK clock case statements for changing raven's clocks for voltage request. Also maintain DCEF clock for DCE120 calls. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Use local structs instead of struct pointersMikita Lipski1-11/+11
Change struct pointers to creating structs on a stack. Thats fixing a mistake in a previous patch introducing dm_pplib functions Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Use tg count for opp init.Yongqiang Sun1-1/+1
In case of tg count not equal to FE pipe count, if use pipe count to iterate the tgs, it will cause BSOD. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: remove invalid assert when no max_pixel_clk is foundDmytro Laktyushkin1-3/+0
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Introduce pp-smu raven functionsMikita Lipski3-6/+92
DM powerplay calls for DCN10 allowing to bypass PPLib and call directly to the SMU functions. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: dal 3.1.48Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Adding Get static clocks for dm_pp interfaceMikita Lipski1-2/+16
Adding a call to powerplay to get system clocks and translate to dm structure Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Apply clock for voltage requestMikita Lipski1-2/+29
Translate dm_pp tructure to pp type Call PP lib to apply clock voltage request for display Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Adding dm-pp clocks getting by voltageMikita Lipski1-2/+41
Function to get clock levels by voltage from PPLib Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: move clock programming from set_bandwidth to dccgDmytro Laktyushkin3-70/+51
This change moves dcn clock programming(with exception of dispclk) into dccg. This should have no functional effect. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: rename display clock block to dccgDmytro Laktyushkin14-100/+100
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: redesign dce/dcn clock voltage update requestDmytro Laktyushkin10-322/+250
The goal of this change is to move clock programming and voltage requests to a single function. As of this change only dce is affected. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: replace clocks_value struct with dc_clocksDmytro Laktyushkin7-86/+49
This will avoid structs with duplicate information. Also removes pixel clock voltage request. This has no effect since pixel clock does not affect dcn voltage and this function only matters for dcn. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05Revert "drm/amdgpu: avoid sleep while executing atombios table (V2)"Alex Deucher1-1/+1
This reverts commit 8f4805a265fd710a2827b2c0e10c08ef2b526870. This change was mistakenly committed and should have been dropped with the rest of the series. Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v3.Andrey Grodzovsky2-13/+76
Access to SQ_EDC_INFO requires selecting register instance and hence mutex lock when accessing GRBM_GFX_INDEX for which a work is schedueled from IH. But SQ interrupt can be raised on many instances at once which means queuing work will usually succeed for the first one but fail for the rest since the work takes time to process. To avoid losing info about other interrupt instances call the parsing function directly from high IRQ when current work hasn't finished and avoid accessing SQ_EDC_INFO in that case. v2: Simplify high IRQ and BH handlers synchronization using work_pending. Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit compiler barriers. v3: Remove exlicit memory barriers as scedule_work has r/w barriers. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: Polish SQ IH.Andrey Grodzovsky1-16/+20
Switch to using reg fields defines istead of magic values. Add SH_ID and PRIV fields reading for instr. and err cases. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v3)Tom St Denis2-0/+45
This adds what should be a stable interface to read GPU load from userspace. (v2): Fix comments and name of file per recommendations. (v3): Add chapter to amdgpu.rst as well. Signed-off-by: Tom St Denis <[email protected]> Acked-by: Slava Abramov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: band aid validating VM PTsChristian König1-1/+1
Always validating the VM PTs takes to much time. Only always validate the per VM BOs for now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-06Merge tag 'omapdrm-4.19' of ↵Dave Airlie19-176/+237
git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next omapdrm changes for 4.19 * Workaround for DRA7 errata i932 * Fix mm_list locking * Cleanups Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-05drm/arm/malidp: Added the late system pm functionsAyan Kumar Halder1-0/+17
malidp_pm_suspend_late checks if the runtime status is not suspended and if so, invokes malidp_runtime_pm_suspend which disables the display engine/core interrupts and the clocks. It sets the runtime status as suspended. The difference between suspend() and suspend_late() is as follows:- 1. suspend() makes the device quiescent. In our case, we invoke the DRM helper which disables the CRTC. This would have invoked runtime pm suspend but the system suspend process disables runtime pm. 2. suspend_late() It continues the suspend operations of the drm device which was started by suspend(). In our case, it performs the same functionality as runtime_suspend(). The complimentary functions are resume() and resume_early(). In the case of resume_early(), we invoke malidp_runtime_pm_resume() which enables the clocks and the interrupts. It sets the runtime status as active. If the device was in runtime suspend mode before system suspend was called, pm_runtime_work() will put the device back in runtime suspended mode( after the complete system has been resumed). Signed-off-by: Ayan Kumar Halder <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Liviu Dudau <[email protected]>
2018-07-05drm/arm/malidp: Set the output_depth register in modesetAyan Kumar Halder3-0/+6
One needs to store the value of the OUTPUT_DEPTH that one has parsed from device tree, so that it can be restored on system resume. This value is set in the modeset function as this gets reset when the system suspends. Signed-off-by: Ayan Kumar Halder <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Liviu Dudau <[email protected]>
2018-07-05drm/arm/malidp: Enable/disable interrupts in runtime pmAyan Kumar Halder1-0/+4
Display and scaling engine interrupts need to be disabled when the runtime pm invokes malidp_runtime_pm_suspend(). Conversely, they need to be enabled in malidp_runtime_pm_resume(). This patch depends on: https://lkml.org/lkml/2017/5/15/695 Reported-by: Alexandru-Cosmin Gheorghe <[email protected]> Signed-off-by: Alexandru-Cosmin Gheorghe <[email protected]> Signed-off-by: Ayan Kumar Halder <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Liviu Dudau <[email protected]>
2018-07-05drm/arm/malidp: Split malidp interrupt initialization functions.Ayan Kumar Halder2-9/+31
Malidp uses two interrupts ie 1. se_irq - used for memory writeback. and 2. de_irq - used for display output. Extract the hardware initialization part from malidp interrupt registration ie (malidp_de_irq_init()/ malidp_se_irq_init()) into a separate function (ie malidp_de_irq_hw_init()/malidp_se_irq_hw_init()) which will be later invoked from runtime_pm_resume function when it needs to re-enable the interrupts. Signed-off-by: Ayan Kumar Halder <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Liviu Dudau <[email protected]>
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