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2023-09-21drm/i915/gt: Update RC6 mask for mtl_drpcBadal Nilawar2-2/+1
It has been observed sometimes RC6 status register's unused bits are being set by h/w, without affecting RC6 functionality therefore updating the mask with used bits accordingly. As mtl_drpc is debugfs function, removing MISSING_CASE from default case as it doesn't make sense to panic (panic_on_warn=1) the CI system if register is reporting unsupported state. Cc: Anshuman Gupta <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-21i915: Limit the length of an sg list to the requested lengthMatthew Wilcox (Oracle)1-4/+7
The folio conversion changed the behaviour of shmem_sg_alloc_table() to put the entire length of the last folio into the sg list, even if the sg list should have been shorter. gen8_ggtt_insert_entries() relied on the list being the right length and would overrun the end of the page tables. Other functions may also have been affected. Clamp the length of the last entry in the sg list to be the expected length. Signed-off-by: Matthew Wilcox (Oracle) <[email protected]> Fixes: 0b62af28f249 ("i915: convert shmem_sg_free_table() to use a folio_batch") Cc: [email protected] # 6.5.x Link: https://gitlab.freedesktop.org/drm/intel/-/issues/9256 Link: https://lore.kernel.org/lkml/[email protected]/ Reported-by: Oleksandr Natalenko <[email protected]> Tested-by: Oleksandr Natalenko <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-21drm/i915: add a note about fec_enable with 128b/132bJani Nikula1-1/+6
Add a note that fec_enable actually means FEC is to be enabled explicitly. 128b/132b always has FEC enabled, the driver doesn't need to enable it separately, and fec_enable will be false. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/i915: refactor deprecated strncpyJustin Stitt1-1/+1
`strncpy` is deprecated for use on NUL-terminated destination strings [1]. We should prefer more robust and less ambiguous string interfaces. A suitable replacement is `strscpy` [2] due to the fact that it guarantees NUL-termination on the destination buffer without unnecessarily NUL-padding. `ctx` is zero allocated and as such strncpy's NUL-padding behavior was strictly a performance hit which is now resolved. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1] Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2] Link: https://github.com/KSPP/linux/issues/90 Cc: [email protected] Signed-off-by: Justin Stitt <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-09-20drm/i915: Implement transcoder LRR for TGL+Ville Syrjälä6-11/+70
Implement low refresh rate (LRR) where we change the vblank length by hand as requested, but otherwise keep the timing generator running in non-VRR mode (ie. fixed refresh rate). The panel itself must support VRR for this to work, and only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that we need to make the switch properly. The double buffer latching happens at the start of transcoders undelayed vblank. The other thing that we change is TRANS_VBLANK.VBLANK_END but the hardware entirely ignores that in DP mode. But I decided to keep writing it anyway just to avoid more special cases in readout/state check. v2: Document that TRANS_VBLANK.VBLANK_END is ignored by the hardware v3: Reconcile with VRR fastset Adjust update_lrr flag behaviour Make sure timings stay within VRR range v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi) Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi) TODO: Hook LRR into the automatic DRRS downclocking stuff? Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Assert that VRR is off during vblank evasion if necessaryVille Syrjälä1-0/+4
Whenever we change the actual transcoder timings (clock via seamless M/N, full modeset, (or soon) vtotal via LRR) we want the timing generator to be in non-VRR during the commit. Warn if we forgot to turn VRR off prior to vblank evasion. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Update VRR parameters in fastsetVille Syrjälä1-8/+26
We should be able to change any of the VRR parameters during fastsets as long as we toggle VRR off at the start and then back on at the end. The transcoder will be running in non-VRR mode during the transition. Co-developed-by: Manasi Navare <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Sean Paul <[email protected]>
2023-09-20drm/i915: Disable VRR during seamless M/N changesVille Syrjälä1-2/+4
Make life less confusing by making sure VRR is disabled whenever we do any drastic changes to the display timings, such as seamless M/N changes. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Validate that the timings are within the VRR rangeVille Syrjälä1-2/+2
Let's assume there are some crazy displays where the high end of the VRR range ends up being lower than the refresh rate as determined by the actual timings. In that case when we toggle VRR on/off we would step outside the VRR range when toggling VRR on/off. Let's just make sure that never happens by not using VRR in such cases. If the user really wants VRR they should then select the timings to land within the VRR range. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Relocate is_in_vrr_range()Ville Syrjälä3-13/+14
Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and rename it accordingly. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Optimize out redundant M/N updatesVille Syrjälä1-1/+3
Don't perform a seamless M/N update if the values aren't actually changing. This avoids doing extra shenanigans during vblank evasion needlessly. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Adjust seamless_m_n flag behaviourVille Syrjälä5-12/+17
Make the seamless_m_n flag more like the update_pipe fastset flag, ie. the flag will only be set if we need to do the seamless M/N update, and in all other cases the flag is cleared. Also rename the flag to update_m_n to make it more clear it's similar to update_pipe. I believe special casing seamless_m_n like this makes sense as it also affects eg. vblank evasion. We can potentially avoid some vblank evasion tricks, simplify some checks, and hopefully will help with the VRR vs. M/N mess. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Enable VRR later during fastsetsVille Syrjälä2-20/+36
In order to reconcile seamless M/N updates with VRR we'll need to defer the fastset VRR enable to happen after the seamless M/N update (which happens during the vblank evade critical section). So just push the VRR enable to be the last thing during the update. This will also affect the vblank evasion as the transcoder will now still be running with the old VRR state during the vblank evasion. So just grab the timings always from the old crtc state during any non-modeset commit, and also grab the current state of VRR from the active timings (as we disable VRR before vblank evasion during fastsets). This also fixes vblank evasion for seamless M/N updates as we now properly account for the fact that the M/N update happens after vblank evasion. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Extract intel_crtc_vblank_evade_scanlines()Ville Syrjälä1-22/+31
Pull the vblank evasion scanline calculations into their own helper to declutter intel_pipe_update_start() a bit. Reviewed-by: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Change intel_pipe_update_{start,end}() calling conventionVille Syrjälä3-10/+18
We'll need to also look at the old crtc state in intel_pipe_update_start() so change the calling convention to just plumb in the full atomic state instead. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Move psr unlock out from the pipe update critical sectionVille Syrjälä1-4/+5
Do the PSR unlock after the vblank evade critcal section is fully over, not before. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915/dsi: let HW maintain CLK_POSTWilliam Tseng1-12/+1
This change is to adjust TCLK-POST timing so DSI signaling can meet CTS specification. For clock lane, the TCLK-POST timing may be changed from 133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI) and is conformed to the CTS standard. The computed UI is around 1.47 ns. v2: remove the change of HS-TRAIL. Cc: Ville Syrjala <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Vandita Kulkarni <[email protected]> Cc: Suraj Kandpal <[email protected]> Cc: Lee Shawn C <[email protected]> Signed-off-by: William Tseng <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: panel: Fix device link for DRM_BRIDGE_ATTACH_NO_CONNECTORAngeloGioacchino Del Regno1-8/+9
When external bridges are attached with DRM_BRIDGE_ATTACH_NO_CONNECTOR, the panel bridge may also get the same flag, but in the .attach() callback for the panel bridge a device link is added only when this flag is not present; To make things worse, the .detach() callback tries to delete the device link unconditionally and without checking if it was created in the first place, crashing the kernel with a NULL pointer kernel panic upon calling panel_bridge_detach(). Fix that by moving the device_link_add() call before checking if the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is present. Fixes: 199cf07ebd2b ("drm/bridge: panel: Add a device link between drm device and panel device") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Liu Ying <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm: Update file owner during useTvrtko Ursulin8-15/+71
With the typical model where the display server opens the file descriptor and then hands it over to the client(*), we were showing stale data in debugfs. Fix it by updating the drm_file->pid on ioctl access from a different process. The field is also made RCU protected to allow for lockless readers. Update side is protected with dev->filelist_mutex. Before: $ cat /sys/kernel/debug/dri/0/clients command pid dev master a uid magic Xorg 2344 0 y y 0 0 Xorg 2344 0 n y 0 2 Xorg 2344 0 n y 0 3 Xorg 2344 0 n y 0 4 After: $ cat /sys/kernel/debug/dri/0/clients command tgid dev master a uid magic Xorg 830 0 y y 0 0 xfce4-session 880 0 n y 0 1 xfwm4 943 0 n y 0 2 neverball 1095 0 n y 0 3 *) More detailed and historically accurate description of various handover implementation kindly provided by Emil Velikov: """ The traditional model, the server was the orchestrator managing the primary device node. From the fd, to the master status and authentication. But looking at the fd alone, this has varied across the years. IIRC in the DRI1 days, Xorg (libdrm really) would have a list of open fd(s) and reuse those whenever needed, DRI2 the client was responsible for open() themselves and with DRI3 the fd was passed to the client. Around the inception of DRI3 and systemd-logind, the latter became another possible orchestrator. Whereby Xorg and Wayland compositors could ask it for the fd. For various reasons (hysterical and genuine ones) Xorg has a fallback path going the open(), whereas Wayland compositors are moving to solely relying on logind... some never had fallback even. Over the past few years, more projects have emerged which provide functionality similar (be that on API level, Dbus, or otherwise) to systemd-logind. """ v2: * Fixed typo in commit text and added a fine historical explanation from Emil. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: "Christian König" <[email protected]> Cc: Daniel Vetter <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]> Tested-by: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Christian König <[email protected]>
2023-09-20drm/bridge: tc358768: Attempt to fix DSI horizontal timingsTomi Valkeinen1-28/+185
The DSI horizontal timing calculations done by the driver seem to often lead to underflows or overflows, depending on the videomode. There are two main things the current driver doesn't seem to get right: DSI HSW and HFP, and VSDly. However, even following Toshiba's documentation it seems we don't always get a working display. This patch attempts to fix the horizontal timings for DSI event mode, and on a system with a DSI->HDMI encoder, a lot of standard HDMI modes now seem to work. The work relies on Toshiba's documentation, but also quite a bit on empirical testing. This also adds timing related debug prints to make it easier to improve on this later. The DSI pulse mode has only been tested with a fixed-resolution panel, which limits the testing of different modes on DSI pulse mode. However, as the VSDly calculation also affects pulse mode, so this might cause a regression. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Fix tc358768_ns_to_cnt()Tomi Valkeinen1-1/+1
The tc358768_ns_to_cnt() is, most likely, supposed to do a div-round-up operation, but it misses subtracting one from the dividend. Fix this by just using DIV_ROUND_UP(). Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Clean up clock period codeTomi Valkeinen1-31/+29
The driver defines TC358768_PRECISION as 1000, and uses "nsk" to refer to clock periods. The original author does not remember where all this came from. Effectively the driver is using picoseconds as the unit for clock periods, yet referring to them by "nsk". Clean this up by just saying the periods are in picoseconds. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Rename dsibclk to hsbyteclkTomi Valkeinen1-24/+24
The Toshiba documentation talks about HSByteClk when referring to the DSI HS byte clock, whereas the driver uses 'dsibclk' name. Also, in a few places the driver calculates the byte clock from the DSI clock, even if the byte clock is already available in a variable. To align the driver with the documentation, change the 'dsibclk' variable to 'hsbyteclk'. This also make it easier to visually separate 'dsibclk' and 'dsiclk' variables. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Use dev for dbg prints, not priv->devTomi Valkeinen1-20/+21
Simplify the code by capturing the priv->dev value to dev variable, and use it. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Print logical values, not raw register valuesTomi Valkeinen1-9/+12
The driver debug prints DSI related timings as raw register values in hex. It is much more useful to see the "logical" value of the timing, not the register value. Change the prints to print the values separately, in case a single register contains multiple values, and use %u to have it in a more human consumable form. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Use struct videomodeTomi Valkeinen1-21/+24
The TC358768 documentation uses HFP, HBP, etc. values to deal with the video mode, while the driver currently uses the DRM display mode (htotal, hsync_start, etc). Change the driver to convert the DRM display mode to struct videomode, which then allows us to use the same units the documentation uses. This makes it much easier to work on the code when using the TC358768 documentation as a reference. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Cleanup PLL calculationsTomi Valkeinen1-7/+7
As is quite common, some of TC358768's PLL register fields are to be programmed with (value - 1). Specifically, the FBD and PRD, multiplier and divider, are such fields. However, what the driver currently does is that it considers that the formula used for PLL rate calculation is: RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] where FBD and PRD are values directly from the registers, while a more sensible way to look at it is: RefClk * FBD / PRD * (1 / (2^FRS)) and when the FBD and PRD values are written to the registers, they will be subtracted by one. Change the driver accordingly, as it simplifies the PLL code. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Fix bit updatesTomi Valkeinen1-6/+7
The driver has a few places where it does: if (thing_is_enabled_in_config) update_thing_bit_in_hw() This means that if the thing is _not_ enabled, the bit never gets cleared. This affects the h/vsyncs and continuous DSI clock bits. Fix the driver to always update the bit. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Default to positive h/v syncsTomi Valkeinen1-0/+18
As the TC358768 is a DPI to DSI bridge, the DSI side does not need to define h/v sync polarities. This means that sometimes we have a mode without defined sync polarities, which does not work on the DPI side. Add a mode_fixup hook to default to positive sync polarities. Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge: tc358768: Fix use of uninitialized variableTomi Valkeinen1-0/+4
smatch reports: drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error: uninitialized symbol 'orig'. Fix this by bailing out from tc358768_update_bits() if the tc358768_read() produces an error. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/tegra: rgb: Parameterize V- and H-sync polaritiesThierry Reding1-3/+13
The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding <[email protected]> Cc: Thierry Reding <[email protected]> [[email protected]: default to positive sync] Reviewed-by: Peter Ujfalusi <[email protected]> Tested-by: Maxim Schwalm <[email protected]> # Asus TF700T Tested-by: Marcel Ziswiler <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-20drm/bridge/analogix/anx78xx: Add missing definitionAlicja Michalska1-0/+2
Analogix ANX78XX driver is missing definitions for anx7816. It uses the same I2C register set as anx7818. Signed-off-by: Alicja Michalska <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ZPvagaXnQ/TlNEkJ@tora
2023-09-20dt-bindings: display: anx7814: Add definition for anx7816Alicja Michalska1-0/+1
As requested by Robert Foss <[email protected]>, this patch adds definition for anx7816. It supplements the patch submitted to dri-devel. Signed-off-by: Alicja Michalska <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ZQjFabKW7QvrvsnG@tora
2023-09-19drm/nouveau/kms/nv50-: disable dcb parsingBen Skeggs3-8/+10
- nvkm should provide all this info now - preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: create outputs based on nvkm infoBen Skeggs9-50/+223
- preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: create connectors based on nvkm infoBen Skeggs8-72/+139
- preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: name aux channels after their connectorBen Skeggs1-16/+9
- removes use of VBIOS data for naming - preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: create heads after outps/connsBen Skeggs1-32/+32
- output info will be used later to determine MST support Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: create heads based on nvkm head maskBen Skeggs1-15/+3
No need to go poking HW directly, and probably shouldn't on GSP-RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp/nv50-: skip DCB_OUTPUT_TVBen Skeggs1-1/+1
We've never supported it. Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: move outp init/fini paths to chipset codeBen Skeggs6-56/+22
- pre-nv5x doesn't use any of this - preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: move outp/conn construction to chipset codeBen Skeggs2-118/+121
- pre-nv5x doesn't use any of this, has its own version DRM-side - preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: add dp mst id get/put methodsBen Skeggs9-4/+137
- preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: add dp sst config methodBen Skeggs5-0/+54
This is presently unused on HW, we read a bunch of regs and calculate the watermark during the second supervisor interrupt. I don't want to change this yet as I need to re-remember how older HW works exactly, but RM wants this info via RPC. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: move link training out of supervisorBen Skeggs9-146/+218
- preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: add dp train methodBen Skeggs9-176/+143
- passes DPCD information from DRM to NVKM - removes NVKM's own sink caps handling - link still trained from supervisor, more patches to come Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: fixup sink D3 before tearing down linkBen Skeggs3-10/+19
- fixes bug preventing this on SST - implement for MST Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: flush mst disables togetherBen Skeggs2-11/+1
- fixes some issues tearing down modes on tiled displays Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/kms/nv50-: split DP disable+enable into two modesetsBen Skeggs1-1/+2
Link training can finally be moved out of the supervisor sequence, but first we need to split DP modesets into separate disable and enable sequences to be able to perform link training between them instead. - preparation for GSP-RM Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-19drm/nouveau/disp: add dp rates methodBen Skeggs8-99/+189
- moves building of link rates table from NVKM to DRM - preparing to move link training out of supervisor Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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