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2013-11-06pinctrl: imx50: add pinctrl support code for the IMX50 SoCGreg Ungerer3-0/+435
Add code to support the specific pin arrangements of the Freescale IMX50 SoC. Signed-off-by: Greg Ungerer <[email protected]> Acked-by: Shawn Guo <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2013-11-06microblaze: Remove unused NO_MMU Kconfig parameterMichael Opdenacker2-7/+2
This removes the NO_MMU Kconfig parameter, which was no longer used anywhere in the source code and Makefiles. This also updates a comment refering to this parameter. Signed-off-by: Michael Opdenacker <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2013-11-06ALSA: pxa2xx: Replace BUG() with snd_BUG()Takashi Iwai1-2/+2
BUG() used in the driver is just to spit the stack trace on buggy points, not really needed to stop the whole operation. For that purpose, it'd be more convenient to use snd_BUG() instead. Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06ALSA: mips/ad1843: Use WARN_ON() instead of BUG_ON()Takashi Iwai1-1/+1
BUG_ON() is rather useless for debugging as it leads to panic(). Use WARN_ON() and handle the error cases accordingly. Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06ALSA: sparc/cs4231: Use WARN_ON() instead of BUG_ON()Takashi Iwai1-2/+4
BUG_ON() is rather useless for debugging as it leads to panic(). Use WARN_ON() and handle the error cases accordingly. Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06ALSA: ps3: Use WARN_ON() instead of BUG_ON()Takashi Iwai1-2/+4
BUG_ON() is rather useless for debugging as it leads to panic(). Use WARN_ON() and handle the error cases accordingly. Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06ALSA: ctxfi: Use WARN_ON() instead of BUG_ON()Takashi Iwai1-2/+4
BUG_ON() is rather useless for debugging as it leads to panic(). Use WARN_ON() and handle the error cases accordingly. Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06x86/cpu: Increase max CPU count to 8192Josh Boyer1-2/+2
The MAXSMP option is intended to enable silly large numbers of CPUs for testing purposes. The current value of 4096 isn't very silly any longer as there are actual SGI machines that approach 6096 CPUs when taking HT into account. Increase the value to a nice round 8192 to account for this and allow for short term future increases. Signed-off-by: Josh Boyer <[email protected]> Cc: [email protected] Cc: Russ Anderson <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ Tweaked it so that MAXSMP simply sets the maximum of the normal range. ] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06x86/cpu: Allow higher NR_CPUS valuesJosh Boyer1-2/+4
The current range for SMP configs is 2 - 512 CPUs, or a full 4096 in the case of MAXSMP. There are machines that have 1024 CPUs in them today and configuring a kernel for that means you are forced to set MAXSMP. This adds additional unnecessary overhead. While that overhead might be considered tiny for large machines, it isn't necessarily so if you are building a kernel that runs across a wide variety of machines. To cover the range of more common machines today, we allow NR_CPUS to be up to 4096 when CPUMASK_OFFSTACK is enabled. Signed-off-by: Josh Boyer <[email protected]> Cc: [email protected] Cc: Russ Anderson <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06ALSA: intel8x0: Fix chmap applicationTakashi Iwai1-9/+8
The playback chmap for multi-channel stream hasn't been properly added to intel8x0 devices due to the wrong condition. Reported-by: Raymond Yau <[email protected]> Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06x86/cpu: Always print SMP information in /proc/cpuinfoHATAYAMA Daisuke1-9/+6
Currently show_cpuinfo_core() displays cpu core information only if the number of threads per a whole cores is 2 or larger. However, this condition doesn't care about the number of sockets. For example, this condition doesn't hold on systems with two logical cpus consisting of two sockets and a single core on each socket - yet the topology information would be interesting to see in that case as well. I don't know whether or not there are processors in real world by which such configurations are possible, but at least on vitual machine environments, such configuration can occur, typically when no explicit SMP information is provided in advance. For example, on qemu/KVM, SMP information is specified via -smp command-line option, more specifically, its syntax is: -smp n[,cores=cores][,threads=threads][,sockets=sockets][,maxcpus=maxcpus] If this is not specified, qemu tells configuration with n-sockets, 1-core and 1-thread to the guest machine, on which guest, MP information is not displayed in /proc/cpuinfo. I saw this situation on VMWare guest environment, too. To fix this issue, this patch simply removes the condition because this information is useful even if there's only 1 thread. Signed-off-by: HATAYAMA Daisuke <[email protected]> Cc: Vivek Goyal <[email protected]> Cc: H. Peter Anvin <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06ALSA: hda - Apply GPIO setup for MacBooks with CS4208Takashi Iwai1-0/+1
Apply the existing GPIO0 fixup as default for MacBooks with CS4208 codec. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=64401 Cc: <[email protected]> [v3.12+] Signed-off-by: Takashi Iwai <[email protected]>
2013-11-06sched: Move completion code from core.c to completion.cPeter Zijlstra4-286/+301
Completions already have their own header file: linux/completion.h Move the implementation out of kernel/sched/core.c and into its own file: kernel/sched/completion.c. Signed-off-by: Peter Zijlstra <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06sched: Move wait code from core.c to wait.cPeter Zijlstra2-105/+105
For some reason only the wait part of the wait api lives in kernel/sched/wait.c and the wake part still lives in kernel/sched/core.c; ammend this. Signed-off-by: Peter Zijlstra <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06sched: Move wait.c into kernel/sched/Peter Zijlstra3-1/+2
Suggested-by: Ingo Molnar <[email protected]> Signed-off-by: Peter Zijlstra <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Andrew Morton <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06Merge tag 'v3.12' into x86/cpu, to refresh the branch before queueing up ↵Ingo Molnar120-864/+1142
more changes Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06Merge tag 'perf-core-for-mingo' of ↵Ingo Molnar45-497/+591
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo: * Check maximum frequency rate for record/top, emitting better error messages, from Jiri Olsa. * Disable live kvm command if timerfd is not supported, from David Ahern. * Add usage to 'perf list', from David Ahern. * Fix detection of non-core features, from David Ahern. * Consolidate __hists__add_*entry(), cleanup from Namhyung Kim. Signed-off-by: Arnaldo Carvalho de Melo <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2013-11-06ARC: [SMP] Fix build failures for large NR_CPUSVineet Gupta2-3/+21
ST.as only takes S9 (255) for offset. This was going out of range when accessing a task_struct field with 4k NR_CPUS (due to 128b of coumaks itself in there). Workaround by using an intermediate register to do the address scaling. There is some duplication of fix for ctx_sw.c and ctx_sw_asm.S however given that C version will go away soon I'm not bothering to factor out the common code. Reported-by: Noam Camus <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: [SMP] enlarge possible NR_CPUSNoam Camus1-2/+2
Signed-off-by: Noam Camus <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: [SMP] TLB flushVineet Gupta4-3/+99
- Add mm_cpumask setting (aggregating only, unlike some other arches) used to restrict the TLB flush cross-calling - cross-calling versions of TLB flush routines (thanks to Noam) Signed-off-by: Noam Camus <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: [SMP] ASID allocationVineet Gupta3-23/+37
-Track a Per CPU ASID counter -mm-per-cpu ASID (multiple threads, or mm migrated around) Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06arc: export symbol for pm_power_off in reset.cChen Gang1-0/+1
Need export symbol for it, or can not pass compiling, the related error with allmodconfig: MODPOST 2994 modules ERROR: "pm_power_off" [drivers/mfd/retu-mfd.ko] undefined! ERROR: "pm_power_off" [drivers/char/ipmi/ipmi_poweroff.ko] undefined! Signed-off-by: Chen Gang <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06arc: export symbol for save_stack_trace() in stacktrace.cChen Gang1-0/+1
Need export its symbol just like other architectures done, or can not pass compiling with allmodconfig, the related error: MODPOST 2994 modules ERROR: "save_stack_trace" [kernel/backtracetest.ko] undefined! ERROR: "save_stack_trace" [drivers/md/persistent-data/dm-persistent-data.ko] undefined! Signed-off-by: Chen Gang <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06arc: remove '__init' for get_hw_config_num_irq()Chen Gang2-2/+2
get_hw_config_num_irq() may be called by normal iss_model_init_smp() which is a function pointer for 'init_smp' which may be called by first_lines_of_secondary() which also need be normal too. The related warning (with allmodconfig): MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x5814): Section mismatch in reference from the function iss_model_init_smp() to the function .init.text:get_hw_config_num_irq() The function iss_model_init_smp() references the function __init get_hw_config_num_irq(). This is often because iss_model_init_smp lacks a __init annotation or the annotation of get_hw_config_num_irq is wrong. Signed-off-by: Chen Gang <[email protected]>
2013-11-06arc: remove '__init' for first_lines_of_secondary()Chen Gang2-2/+2
first_lines_of_secondary() is a '__init' function, but it may be called by __cpu_up() by _cpu_up() by cpu_up() which is a normal export symbol function. So recommend to remove '__init'. The related warning (with allmodconfig): MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x315c): Section mismatch in reference from the function __cpu_up() to the function .init.text:first_lines_of_secondary() The function __cpu_up() references the function __init first_lines_of_secondary(). This is often because __cpu_up lacks a __init annotation or the annotation of first_lines_of_secondary is wrong. Signed-off-by: Chen Gang <[email protected]>
2013-11-06arc: remove '__init' for setup_processor() and arc_init_IRQ()Chen Gang2-2/+2
They haven't '__init' in definition, but has '__init' in declaration. And normal function start_kernel_secondary() may call setup_processor() which will call arc_init_IRQ(). So need remove '__init' for both of them. The related warning (with allmodconfig): MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x3084): Section mismatch in reference from the function start_kernel_secondary() to the function .init.text:setup_processor() The function start_kernel_secondary() references the function __init setup_processor(). This is often because start_kernel_secondary lacks a __init annotation or the annotation of setup_processor is wrong. Signed-off-by: Chen Gang <[email protected]>
2013-11-06arc: kgdb: add default implementation for kgdb_roundup_cpus()Chen Gang1-0/+12
arc supports kgdb, but need update -- add function kgdb_roundup_cpus(), or can not pass compiling. At present, add the simple generic one just like other architectures(e.g. tile, mips ...). The related error (with allmodconfig): kernel/built-in.o: In function `kgdb_cpu_enter': kernel/debug/debug_core.c:580: undefined reference to `kgdb_roundup_cpus' Signed-off-by: Chen Gang <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Fix bogus gcc warning and micro-optimise TLB iteration loopVineet Gupta1-2/+2
------------------>8---------------------- arch/arc/mm/tlb.c: In function ‘do_tlb_overlap_fault’: arch/arc/mm/tlb.c:688:13: warning: array subscript is above array bounds [-Warray-bounds] (pd0[n] & PAGE_MASK)) { ^ ------------------>8---------------------- While at it, remove the usless last iteration of outer loop when reading a TLB SET for duplicate entries. Suggested-by: Mischa Jonker <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Add support for irqflags tracing and lockdepVineet Gupta4-1/+42
Lockdep required a small fix to stacktrace API which was incorrectly unwindign out of __switch_to for the current call frame. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Reset the value of Interrupt Priority RegisterVineet Gupta1-3/+7
In case bootloader has changed the priority of one/more IRQ lines Reported-by: Noam Camus <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Reduce #ifdef'ery for unaligned access emulationVineet Gupta3-7/+3
Emulation not enabled is treated as if the fixup failed, so no need for special #ifdef checks. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Change calling convention of do_page_fault()Vineet Gupta3-8/+7
switch the args (address, pt_regs) to match with all the other "C" exception handlers. This removes the awkwardness in EV_ProtV for page fault vs. unaligned access. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: cacheflush optim - PTAG can be loop invariant if V-P is constVineet Gupta1-3/+11
Line op needs vaddr (indexing) and paddr (tag match). For page sized flushes (V-P const), each line op will need a different index, but the tag bits wil remain constant, hence paddr can be setup once outside the loop. This improves select LMBench numbers for Aliasing dcache where we have more "preventive" cache flushing. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 3.11-rc7- Linux 3.11.0- 80 4.66 8.88 69.7 112. 268. 8.60 28.0 3489 13.K 27.K # Non alias ARC700 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 68.6 98.5 271. 8.58 28.1 4160 15.K 32.K # Aliasing 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 69.8 99.4 270. 8.73 27.5 3880 15.K 31.K # PTAG loop Inv Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: cacheflush refactor #3: Unify the {d,i}cache flush leaf helpersVineet Gupta1-84/+55
With Line length being constant now, we can fold the 2 helpers into 1. This allows applying any optimizations (forthcoming) to single place. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: cacheflush refactor #2: I and D caches lines to have same sizeVineet Gupta2-22/+16
Having them be different seems an obscure configuration. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: cacheflush refactor #1: push aux reg ascertaining into leaf routineVineet Gupta1-10/+6
ARC dcache supports 3 ops - Inv, Flush, Flush-n-Inv. The programming model however provides 2 commands FLUSH, INV. INV will either discard or flush-n-discard (based on DT_CTRL bit) The leaf helper __dc_line_loop() used to take the AUX register (corresponding to the 2 commands). Now we push that to within the helper, paving way for code consolidations to follow. Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: use __weak instead of __attribute__((weak))Vineet Gupta2-2/+2
Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06ARC: Annotate some functions as staticVineet Gupta1-6/+5
Signed-off-by: Vineet Gupta <[email protected]>
2013-11-06arc: Replace __get_cpu_var usesChristoph Lameter2-4/+4
__get_cpu_var() is used for multiple purposes in the kernel source. One of them is address calculation via the form &__get_cpu_var(x). This calculates the address for the instance of the percpu variable of the current processor based on an offset. Other use cases are for storing and retrieving data from the current processors percpu area. __get_cpu_var() can be used as an lvalue when writing data or on the right side of an assignment. __get_cpu_var() is defined as : #define __get_cpu_var(var) (*this_cpu_ptr(&(var))) __get_cpu_var() always only does an address determination. However, store and retrieve operations could use a segment prefix (or global register on other platforms) to avoid the address calculation. this_cpu_write() and this_cpu_read() can directly take an offset into a percpu area and use optimized assembly code to read and write per cpu variables. This patch converts __get_cpu_var into either an explicit address calculation using this_cpu_ptr() or into a use of this_cpu operations that use the offset. Thereby address calcualtions are avoided and less registers are used when code is generated. At the end of the patchset all uses of __get_cpu_var have been removed so the macro is removed too. The patchset includes passes over all arches as well. Once these operations are used throughout then specialized macros can be defined in non -x86 arches as well in order to optimize per cpu access by f.e. using a global register that may be set to the per cpu base. Transformations done to __get_cpu_var() 1. Determine the address of the percpu instance of the current processor. DEFINE_PER_CPU(int, y); int *x = &__get_cpu_var(y); Converts to int *x = this_cpu_ptr(&y); 2. Same as #1 but this time an array structure is involved. DEFINE_PER_CPU(int, y[20]); int *x = __get_cpu_var(y); Converts to int *x = this_cpu_ptr(y); 3. Retrieve the content of the current processors instance of a per cpu variable. DEFINE_PER_CPU(int, u); int x = __get_cpu_var(y) Converts to int x = __this_cpu_read(y); 4. Retrieve the content of a percpu struct DEFINE_PER_CPU(struct mystruct, y); struct mystruct x = __get_cpu_var(y); Converts to memcpy(this_cpu_ptr(&x), y, sizeof(x)); 5. Assignment to a per cpu variable DEFINE_PER_CPU(int, y) __get_cpu_var(y) = x; Converts to this_cpu_write(y, x); 6. Increment/Decrement etc of a per cpu variable DEFINE_PER_CPU(int, y); __get_cpu_var(y)++ Converts to this_cpu_inc(y) Acked-by: Vineet Gupta <[email protected]> Signed-off-by: Christoph Lameter <[email protected]>
2013-11-06powerpc: Fix fatal SLB miss when restoring PPRBenjamin Herrenschmidt2-8/+9
When restoring the PPR value, we incorrectly access the thread structure at a time where MSR:RI is clear, which means we cannot recover from nested faults. However the thread structure isn't covered by the "bolted" SLB entries and thus accessing can fault. This fixes it by splitting the code so that the PPR value is loaded into a GPR before MSR:RI is cleared. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-06powerpc/powernv: Reserve the correct PE numberGavin Shan3-16/+17
We're assigning PE numbers after the completion of PCI probe. During the PCI probe, we had PE#0 as the super container to encompass all PCI devices. However, that's inappropriate since PELTM has ascending order of priority on search on P7IOC. So we need PE#127 takes the role that PE#0 has previously. For PHB3, we still have PE#0 as the reserved PE. The patch supposes that the underly firmware has built the RID to PE# mapping after resetting IODA tables: all PELTM entries except last one has invalid mapping on P7IOC, but all RTEs have binding to PE#0. The reserved PE# is being exported by firmware by device tree. Signed-off-by: Gavin Shan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-06powerpc/powernv: Add PE to its own PELTVGavin Shan1-1/+11
We need add PE to its own PELTV. Otherwise, the errors originated from the PE might contribute to other PEs. In the result, we can't clear up the error successfully even we're checking and clearing errors during access to PCI config space. Cc: [email protected] Reported-by: [email protected] Signed-off-by: Gavin Shan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-06powerpc/powernv: Add support for indirect XSCOM via debugfsBenjamin Herrenschmidt1-0/+23
Indirect XSCOM addresses normally have the top bit set (of the 64-bit address). This doesn't work via the normal debugfs interface, so we use a different encoding, which we need to convert before calling OPAL. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-06powerpc/scom: Improve debugfs interfaceBenjamin Herrenschmidt1-55/+81
The current debugfs interface to scom is essentially unused and racy. It uses two different files "address" and "data" to perform accesses which is at best impractical for anything but manual use by a developer. This replaces it with an "access" file which represent the entire scom address space which can be lseek/read/writen too. This file only supports accesses that are 8 bytes aligned and multiple of 8 bytes in size. The offset is logically the SCOM address multiplied by 8. Since nothing in userspace exploits that file at the moment, the ABI change is a no-brainer. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-06powerpc/scom: Enable 64-bit addressesBenjamin Herrenschmidt3-9/+9
On P8, XSCOM addresses has a special "indirect" form that requires more than 32-bits, so let's use u64 everywhere in the code instead of u32. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-11-05perf tools: Finish the removal of 'self' argumentsArnaldo Carvalho de Melo21-246/+242
They convey no information, perhaps I was bitten by some snake at some point, complete the detox by naming the last of those arguments more sensibly. Cc: Adrian Hunter <[email protected]> Cc: David Ahern <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Mike Galbraith <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2013-11-05perf tools: Check maximum frequency rate for record/topJiri Olsa4-28/+74
Adding the check for maximum allowed frequency rate defined in following file: /proc/sys/kernel/perf_event_max_sample_rate When we cross the maximum value we fail and display detailed error message with advise. $ perf record -F 3000 ls Maximum frequency rate (2000) reached. Please use -F freq option with lower value or consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. In case user does not specify the frequency and the default value cross the maximum, we display warning and set the frequency value to the current maximum. $ perf record ls Lowering default frequency rate to 2000. Please consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. Same messages are used for 'perf top'. Signed-off-by: Jiri Olsa <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Corey Ashford <[email protected]> Cc: David Ahern <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2013-11-05perf fs: Add procfs supportJiri Olsa3-2/+19
Adding procfs support into fs class. The interface function: const char *procfs__mountpoint(void); provides existing mountpoint path for procfs. Signed-off-by: Jiri Olsa <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Corey Ashford <[email protected]> Cc: David Ahern <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ Fixup namespace ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2013-11-05perf fs: Rename NAME_find_mountpoint() to NAME__mountpoint()Arnaldo Carvalho de Melo5-21/+16
Shorten it, "finding" it is an implementation detail, what callers want is the pathname, not to ask for it to _always_ do the lookup. And the existing implementation already caches it, i.e. it doesn't "finds" it on every call. Cc: Adrian Hunter <[email protected]> Cc: David Ahern <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Mike Galbraith <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2013-11-05arm64: compat: Clear the IT state independent of the 32-bit ARM or Thumb-2 modeT.J. Purtell1-4/+5
The ARM architecture reference specifies that the IT state bits in the PSR must be all zeros in ARM mode or behavior is unspecified. If an ARM function is registered as a signal handler, and that signal is delivered inside a block of instructions following an IT instruction, some of the instructions at the beginning of the signal handler may be skipped if the IT state bits of the Program Status Register are not cleared by the kernel. Signed-off-by: T.J. Purtell <[email protected]> [[email protected]: code comment and commit log updated] Signed-off-by: Catalin Marinas <[email protected]>