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2020-04-28drm/amdkfd: Enable GWS based on FW SupportJoseph Greathouse5-17/+41
Rather than only enabling GWS support based on the hws_gws_support modparm, also check whether the GPU's HWS firmware supports GWS. Leave the old modparm in place in case users want to test GWS on GPUs not yet in the support list. v2: fix broken syntax from the first patch. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdkfd: New IOCTL to allocate queue GWS (v2)Oak Zeng4-1/+68
Add a new kfd ioctl to allocate queue GWS. Queue GWS is released on queue destroy. v2: re-introduce this API with the following fixes squashed in: - drm/amdkfd: fix null pointer dereference on dev - drm/amdkfd: Return proper error code for gws alloc API - drm/amdkfd: Remove GPU ID in GWS queue creation Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: pass unlocked flag to params at amdgpu_vm_bo_update_mappingAlex Sierra1-0/+1
Pass unlocked flag value to amdgpu_vm_update_params.unlocked struct member at amdgpu_vm_bo_update_mapping. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add new unlocked flag for PTE updatesChristian König3-26/+37
For HMM support we need the ability to invalidate PTEs from a MM callback where we can't lock the root PD. Add a new flag to better support this instead of assuming that all invalidation updates are unlocked. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: rename direct to immediate for VM updatesChristian König5-50/+51
To avoid confusion with direct ring submissions rename bottom of pipe VM table changes to immediate updates. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: cleanup IB pool handling a bitChristian König10-56/+71
Fix the coding style, move and rename the definitions to better match what they are supposed to be doing. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: partial revert VM sync changesChristian König1-0/+5
We still need to add the VM update fences to the root PD. So make sure to never sync to those implicitely. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: check ring type for secure IBsAlex Deucher1-0/+6
We don't support secure operation on compute rings at the moment so reject them. Reviewed-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: fix size calculation in amdgpu_ttm_copy_mem_to_memChristian König1-3/+3
When the node is larger than 4GB we overrun the size calculation. Fix this by correctly limiting the size to the window as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add full TMZ support into amdgpu_ttm_map_buffer v2Christian König1-8/+30
This should allow us to also support VRAM->GTT moves. v2: fix missing vram_base_adjustment Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: cleanup amdgpu_ttm_copy_mem_to_mem and amdgpu_map_buffer v2Christian König2-138/+136
Cleanup amdgpu_ttm_copy_mem_to_mem by using fewer variables for the same value. Rename amdgpu_map_buffer to amdgpu_ttm_map_buffer, move it to avoid the forward decleration, cleanup by moving the map decission into the function and add some documentation. No functional change. v2: add some more cleanup suggested by Felix Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Huang Rui <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: Fix per-IB secure flag GFX hangHuang Rui4-29/+32
Since commit "Move to a per-IB secure flag (TMZ)", we've been seeing hangs in GFX. We need to send FRAME CONTROL stop/start back-to-back, every time we flip the TMZ flag. That is, when we transition from TMZ to non-TMZ we have to send a stop with TMZ followed by a start with non-TMZ, and similarly for transitioning from non-TMZ into TMZ. This patch implements this, thus fixing the GFX hang. v1 -> v2: As suggested by Luben, and accept part of implemetation from this patch: - Put "secure" closed to the loop and use optimization - Change "secure" to bool again, and move "secure == -1" out of loop. v3: Small fixes/optimizations. Reported-and-Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: Fine-grained TMZ supportLuben Tuikov1-10/+20
Add fine-grained per-ASIC TMZ support. At the moment TMZ support is experimental for all ASICs which support it. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: stop evicting encrypted BOs to swapChristian König1-0/+3
Swapping out encrypted BOs doesn't work because they can't change their physical location without going through a bounce copy. As a workaround disable evicting encrypted BOs to the system domain for now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add TMZ handling to amdgpu_move_blitChristian König2-10/+20
This way we should be at least able to move buffers from VRAM to GTT. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: also add the TMZ flag to GARTChristian König1-0/+3
This is necessary for TMZ handling during buffer moves and scanout. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: fix the wrong logic checking when secure buffer is created (v3)Huang Rui1-2/+2
While the current amdgpu doesn't support TMZ, it will return the error if user mode would like to allocate secure buffer. v2: we didn't need this checking anymore. v3: only print message once time. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: Move to a per-IB secure flag (TMZ)Luben Tuikov10-52/+44
Move from a per-CS secure flag (TMZ) to a per-IB secure flag. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Indicate use of TMZ buffers to DCHarry Wentland1-6/+23
[Why] Hubp needs to know whether a buffer is being scanned out from the trusted memory zone or not. [How] Check for the TMZ flag on the amdgpu_bo and set the tmz_surface flag in dc_plane_address accordingly. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: implement TMZ accessor (v3)Luben Tuikov10-103/+40
Implement an accessor of adev->tmz.enabled. Let not code around access it as "if (adev->tmz.enabled)" as the organization may change. Instead... Recruit "bool amdgpu_is_tmz(adev)" to return exactly this Boolean value. That is, this function is now an accessor of an already initialized and set adev and adev->tmz. Add "void amdgpu_gmc_tmz_set(adev)" to check and set adev->gmc.tmz_enabled at initialization time. After which one uses "bool amdgpu_is_tmz(adev)" to query whether adev supports TMZ. Also, remove circular header file include. v2: Remove amdgpu_tmz.[ch] as requested. v3: Move TMZ into GMC. Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: remove the alignment placeholder for secure bufferHuang Rui1-4/+0
The alignment should match the page size for secure buffer, so we didn't configure it anymore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: move CS secure flag next the structs where it's usedAlex Deucher1-3/+3
So it's not mixed up with the CTX stuff. Reviewed-by: Zhan Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10Aaron Liu1-1/+1
This patch enables TMZ bit in FRAME_CONTROL for gfx10. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v5Aaron Liu1-1/+2
Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt for sdma v5. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v4Aaron Liu1-1/+2
Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt for sdma v4 Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: expand amdgpu_copy_buffer interface with tmz parameterAaron Liu5-8/+8
This patch expands amdgpu_copy_buffer interface with tmz parameter. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: expand sdma copy_buffer interface with tmz parameterAaron Liu8-10/+17
This patch expands sdma copy_buffer interface with tmz parameter. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.hStephen Rothwell1-1/+4
Signed-off-by: Stephen Rothwell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: set TMZ bits in PTEs for secure BO (v4)Alex Deucher3-1/+26
If a buffer object is secure, i.e. created with AMDGPU_GEM_CREATE_ENCRYPTED, then the TMZ bit of the PTEs that belong the buffer object should be set. v1: design and draft the skeletion of TMZ bits setting on PTEs (Alex) v2: return failure once create secure BO on non-TMZ platform (Ray) v3: amdgpu_bo_encrypted() only checks the BO (Luben) v4: move TMZ flag setting into amdgpu_vm_bo_update (Christian) Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
2020-04-28drm/amdgpu: job is secure iff CS is secure (v5)Huang Rui3-2/+6
Mark a job as secure, if and only if the command submission flag has the secure flag set. v2: fix the null job pointer while in vmid 0 submission. v3: Context --> Command submission. v4: filling cs parser with cs->in.flags v5: move the job secure flag setting out of amdgpu_cs_submit() Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: expand the context control interface with trust flagHuang Rui7-9/+16
This patch expands the context control function to support trusted flag while we want to set command buffer in trusted mode. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: expand the emit tmz interface with trusted flagHuang Rui4-10/+25
This patch expands the emit_tmz function to support trusted flag while we want to set command buffer in trusted mode. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add tmz bit in frame control packetHuang Rui2-0/+2
This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add function to check tmz capability (v4)Huang Rui4-1/+56
Add a function to check tmz capability with kernel parameter and ASIC type. v2: use a per device tmz variable instead of global amdgpu_tmz. v3: refine the comments for the function. (Luben) v4: add amdgpu_tmz.c/h for future use. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add amdgpu_tmz data structureHuang Rui2-1/+41
This patch to add amdgpu_tmz structure which stores all tmz related fields. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add tmz feature parameter (v2)Huang Rui2-0/+13
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel module. Nomally, by default, it should be auto (rely on the hardware capability). But right now, it need to set "off" to avoid breaking other developers' work because it's not totally completed. Will set "auto" till the feature is stable and completely verified. v2: add "auto" option for future use. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: define the TMZ bit for the PTEAlex Deucher1-0/+3
Define the TMZ (encryption) bit in the page table entry (PTE) for Raven and newer asics. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]>
2020-04-28drm/amdgpu: add UAPI to create secure commands (v3)Luben Tuikov1-1/+4
Add a flag to the command submission IOCTL structure which when present indicates that this command submission should be treated as secure. The kernel driver uses this flag to determine whether the engine should be transitioned to secure or unsecure, or the work can be submitted to a secure queue depending on the IP. v3: the flag is now at command submission IOCTL Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: add UAPI for creating encrypted buffersAlex Deucher1-0/+5
Add a flag to the GEM_CREATE ioctl to create encrypted buffers. Buffers with this flag set will be created with the TMZ bit set in the PTEs or engines accessing them. This is required in order to properly access the data from the engines. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Christian König <[email protected]>
2020-04-28drm/amd/display: 3.2.83.1Aric Cyr1-1/+1
Update firmware blobs Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: 3.2.83Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Use cursor locking to prevent flip delaysAric Cyr16-45/+88
[Why] Current locking scheme for cursor can result in a flip missing its vsync, deferring it for one or more vsyncs. Result is a potential for stuttering when cursor is moved. [How] Use cursor update lock so that flips are not blocked while cursor is being programmed. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Internal refactoring to abstract color capsKrunoslav Kovac7-13/+178
[Why&How] modules/color calculates various colour operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. We would hack it with some DCN checks, but a better approach is to abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities, Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Add set backlight to hw sequencer.Yongqiang Sun7-25/+55
[Why & How] Add set backlight to hw sequencer, dmu communication will be handled in hw sequencer for new asics. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Add dummy p-state latency bounding box overrideJoshua Aberback2-0/+8
[Why] For debugging, it can be useful to be able to modify the dummy p-state latency, this will make it easier to do so. Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Add panel cntl id for set backlight level.Yongqiang Sun8-22/+40
[Why & How] Add panel cntl instance when calling set backlight. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Pass command instead of header into DMUB serviceNicholas Kazlauskas10-55/+80
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd. [How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1Sung Lee1-1/+1
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Defer cursor update around VUPDATE for all ASICNicholas Kazlauskas1-14/+14
[Why] Fixes the following scenario: - Flip has been prepared sometime during the frame, update pending - Cursor update happens right when VUPDATE would happen - OPTC lock acquired, VUPDATE is blocked until next frame - Flip is delayed potentially infinitely With the igt@kms_cursor_legacy cursor-vs-flip-legacy test we can observe nearly *13* frames of delay for some flips on Navi. [How] Apply the Raven workaround generically. When close enough to VUPDATE block cursor updates from occurring from the dc_stream_set_cursor_* helpers. This could perhaps be a little smarter by checking if there were pending updates or flips earlier in the frame on the HUBP side before applying the delay, but this should be fine for now. This fixes the kms_cursor_legacy test. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amd/display: Change viewport limit to 12 for DCN2Sung Lee1-2/+2
[WHY & HOW] Viewport limit was set to 16 pixels due to an issue with MPO on small viewports. This restriction does not apply and the viewport limit can now be lowered. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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