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2017-10-29mtd: spi-nor: Add support for mr25h128Philipp Puschmann3-0/+3
Add Everspin mr25h128 16KB MRAM to the list of supported chips. Signed-off-by: Philipp Puschmann <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-29mtd: spi-nor: enable 4B opcodes for mx66l51235lRoman Yeryomin1-1/+1
Signed-off-by: Roman Yeryomin <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-29mtd: spi-nor: stm32-quadspi: fix prefetching outside fsizeLudovic Barre1-1/+11
When memory-mapped mode is used, a prefetching mechanism fully managed by the hardware allows to optimize the read from external the QSPI memory. A 32-bytes FIFO is used for prefetching. When the limit of flash size - fifo size is reached the prefetching mechanism tries to read outside the fsize. The stm32 quadspi hardware become busy and should be aborted. Signed-off-by: Ludovic Barre <[email protected]> Reported-by: Bruno Herrera <[email protected]> Tested-by: Bruno Herrera <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-29mtd: spi-nor: stm32-quadspi: change license textLudovic Barre1-3/+16
-Change the license text with long template. -Change Copyright to STMicroelectronics. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-29mtd: spi-nor: stm32-quadspi: Fix uninitialized error return codeGeert Uytterhoeven1-2/+2
With gcc 4.1.2: drivers/mtd/spi-nor/stm32-quadspi.c: In function ‘stm32_qspi_tx_poll’: drivers/mtd/spi-nor/stm32-quadspi.c:230: warning: ‘ret’ may be used uninitialized in this function Indeed, if stm32_qspi_cmd.len is zero, ret will be uninitialized. This length is passed from outside the driver using the spi_nor.{read,write}{,_reg}() callbacks. Several functions in drivers/mtd/spi-nor/spi-nor.c (e.g. write_enable(), write_disable(), and erase_chip()) call spi_nor.write_reg() with a zero length. Fix this by returning an explicit zero on success. Fixes: 0d43d7ab277a048c ("mtd: spi-nor: add driver for STM32 quad spi flash controller") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Ludovic Barre <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-25spi-nor: intel-spi: Remove EXPERT dependencyBin Meng1-2/+2
The idea to have the intel-spi driver dependent on EXPERT was exactly because we did not want ordinary users playing with the device and inadvertently overwrite their BIOSes (if it is not protected). This seems to be superfluous hence remove it. Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-24mtd: mtk-nor: add suspend/resume supportGuochun Mao1-12/+58
Abstract functions of clock setting, to avoid duplicated code, these functions been used in new feature. Implement suspend/resume functions. Signed-off-by: Guochun Mao <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-24dt-bindings: mtd: add new compatible strings and improve descriptionGuochun Mao1-6/+9
Add "mediatak,mt2712-nor" and "mediatek,mt7622-nor" for nor flash node's compatible strings. Explicate the fallback compatible. Acked-by: Rob Herring <[email protected]> Signed-off-by: Guochun Mao <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-23mtd: spi-nor: Add support for Winbond w25q16dwNeil Armstrong1-0/+5
Add JEDEC entry for the Winbond w25q16fw/w25q16dw with similar flags and format than the Winbond w25q32dw entry. Tested on a Khadas VIM2 SBC board with an Amlogic S912 SoC. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: Add runtime PM supportVignesh R1-1/+15
Add pm_runtime* calls to cadence-quadspi driver. This is required to switch on QSPI power domain on TI 66AK2G SoC during probe. Signed-off-by: Vignesh R <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: Fix error path in probeVignesh R1-2/+2
Fix the reversed goto labels, so that we disable cqspi controller only if its enabled previously. This is a minor cleanup. Signed-off-by: Vignesh R <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuitVignesh R1-2/+6
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Based on DT parameter cdns,rclk-en enable adapted loop-back circuit for boards which do have QSPI return clock provided. This patch also modifies cqspi_readdata_capture() function's bypass parameter to bool to match how its used in the function. Signed-off-by: Vignesh R <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuitVignesh R1-0/+3
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit for boards which do have QSPI return clock provided. Update binding documentation for the same. Signed-off-by: Vignesh R <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: add a delay in write sequenceVignesh R1-1/+26
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this and set this flag for TI 66AK2G SoC. [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf Signed-off-by: Vignesh R <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-17mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatibleVignesh R1-1/+3
Update binding documentation to add a new compatible for TI 66AK2G SoC, to handle TI SoC specific quirks in the driver. Signed-off-by: Vignesh R <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Fall back to use SW sequencer to eraseBin Meng1-1/+49
According to the datasheet, the HW sequencer has a predefined list of opcodes, with only the erase opcode being programmable in LVSCC and UVSCC registers. If these registers don't contain a valid erase opcode (eg: BIOS does not program it), erase cannot be done using the HW sequencer, even though the erase operation does not report any error, the flash remains not erased. If such register setting is detected, let's fall back to use the SW sequencer to erase instead. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'Bin Meng1-8/+8
The ispi->swseq is used for register access. Let's rename it to swseq_reg to better describe its usage. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Remove the unnecessary HSFSTS register RWBin Meng1-3/+2
There is no code that alters the HSFSTS register content in between in intel_spi_write(). Remove the unnecessary RW to save some cycles. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOSBin Meng1-26/+65
At present the driver relies on valid OPMENU0/OPMENU1 register values that are programmed by BIOS to function correctly. However in a real world it's absolutely legitimate for a bootloader to leave these two registers untouched. Intel FSP for Baytrail exactly does like this. When we are booting from any Intel FSP based bootloaders like U-Boot, the driver refuses to work. We can of course program various flash opcodes in the OPMENU0/OPMENU1 registers, and such workaround can be added in either the bootloader codes, or the kernel driver itself. But a graceful solution would be to update the kernel driver to remove such limitation of OPMENU0/1 register dependency. The SPI controller settings are not locked under such configuration. So we can first check the controller locking status, and if it is not locked that means the driver job can be fulfilled by using a chosen OPMENU index to set up the flash opcode every time. While we are here, the missing 'Atomic Cycle Sequence' handling in the SW sequencer codes is also added. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in intel_spi_write()Bin Meng1-5/+0
So far intel_spi_write() uses the HW sequencer to do the write. But the HW sequencer register HSFSTS_CTL does not have such a field for 'Atomic Cycle Sequence', remove it. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Use SW sequencer for BYT/LPTBin Meng1-15/+15
Baytrail/Lynx Point SPI controller's HW sequencer only supports basic operations. This is determined by the chipset design, however current codes try to use register values in OPMENU0/OPMENU1 to see whether SW sequencer should be used, which is wrong. In fact OPMENU0/OPMENU1 can remain unprogrammed by some bootloaders. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Check transfer length in the HW/SW cycleBin Meng1-2/+10
Intel SPI controller only has a 64 bytes FIFO. This adds a sanity check before triggering any HW/SW sequencer work. Additionally for the SW sequencer, if given data length is zero, we should not mark the 'Data Cycle' bit. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Fix broken software sequencing codesBin Meng1-2/+2
There are two bugs in current intel_spi_sw_cycle(): - The 'data byte count' field should be the number of bytes transferred minus 1 - SSFSTS_CTL is the offset from ispi->sregs, not ispi->base Signed-off-by: Bin Meng <[email protected]> Cc: <[email protected]> # v4.11+ Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycleBin Meng1-8/+6
intel_spi_hw_cycle() and intel_spi_sw_cycle() don't use the parameter 'buf' at all. Remove it. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-11spi-nor: intel-spi: Fix number of protected range registers for BYT/LPTBin Meng1-5/+11
The number of protected range registers is not the same on BYT/LPT/ BXT. GPR0 only exists on Apollo Lake and its offset is reserved on other platforms. Signed-off-by: Bin Meng <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: intel-spi: Add support for Intel Cedar Fork SPI serial flashMika Westerberg1-0/+1
Intel Cedar Fork has the same SPI serial flash controller than Intel Denverton. Add the Intel Cedar Fork PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: intel-spi: Add support for Intel Lewisburg SPI serial flashMika Westerberg1-0/+1
Intel Lewisburg chipset exposes the SPI serial flash controller as a PCI device in the same way than Intel Denverton. Add Intel Lewisburg SPI serial flash PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: add support for Gigadevice GD25LQ32Klaus Goger1-0/+5
Tested against GD25LQ32D but the GD25LQ32C datasheet seems to be identically feature-wise. Therefore dropping the suffix as it's probably only indicating the die revision. Signed-off-by: Klaus Goger <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: add support for GD25Q256Andy Yan1-0/+8
Add support for GD25Q256, a 32MiB SPI Nor flash from GigaDevice. Signed-off-by: Andy Yan <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: add a quad_enable callback in struct flash_infoAndy Yan1-0/+11
Some manufacturers may use different bit to set QE on different memories. The GD25Q256 from GigaDevice is an example, which uses S6(bit 6 of the Status Register-1) to set QE, which is different with other supported memories from GigaDevice that use S9(bit 1 of the Status Register-2). This makes it is impossible to select the quad enable method by distinguishing the MFR. This patch introduce a quad_enable function which can be set per memory in the flash_info list table. Signed-off-by: Andy Yan <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: Allow Cadence QSPI support for ARM64Thor Thayer1-1/+1
Allow ARM64 support for the Cadence QSPI interface by adding ARM64 as a dependency. Signed-off-by: Thor Thayer <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: Add spi-nor mtd resume handlerKamal Dasu1-0/+14
Implemented and populated spi-nor mtd PM handlers for resume ops. spi-nor resume op re-initializes spi-nor flash to its probed state by calling the newly implemented spi_nor_init() function. Signed-off-by: Kamal Dasu <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: add spi_nor_init() functionKamal Dasu2-18/+48
This patch extracts some chunks from spi_nor_init_params and spi_nor_scan() and moves them into a new spi_nor_init() function. Indeed, spi_nor_init() regroups all the required SPI flash commands to be sent to the SPI flash memory before performing any runtime operations (Fast Read, Page Program, Sector Erase, ...). Hence spi_nor_init(): 1) removes the flash protection if applicable for certain vendors. 2) sets the Quad Enable bit, if needed, before using Quad SPI protocols. 3) makes the memory enter its (stateful) 4-byte address mode, if needed, for SPI flash memory > 128Mbits not supporting the 4-byte address instruction set. spi_nor_scan() now ends by calling spi_nor_init() once the probe phase has completed. Further patches could also use spi_nor_init() to implement the mtd->_resume() handler for the spi-nor framework. Signed-off-by: Kamal Dasu <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-10mtd: spi-nor: Kill check with no effectRichard Weinberger1-2/+1
header.minor is of type u8 and cannot be negative. Detected by CoverityScan CID#1417858 ("Integer handling issues") Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Richard Weinberger <[email protected]> Signed-off-by: Cyrille Pitchen <[email protected]>
2017-10-08Linux 4.14-rc4Linus Torvalds1-1/+1
2017-10-07Merge tag 'scsi-fixes' of ↵Linus Torvalds8-31/+36
git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi Pull SCSI fixes from James Bottomley: - a couple of serious fixes: use after free and blacklist for WRITE SAME - one error leg fix: write_pending failure - one user experience problem: do not override max_sectors_kb - one minor unused function removal * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: scsi: ibmvscsis: Fix write_pending failure path scsi: libiscsi: Remove iscsi_destroy_session scsi: libiscsi: Fix use-after-free race during iscsi_session_teardown scsi: sd: Do not override max_sectors_kb sysfs setting scsi: sd: Implement blacklist option for WRITE SAME w/ UNMAP
2017-10-07Merge branch 'i2c/for-current-4.14' of ↵Linus Torvalds5-10/+14
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c fixes from Wolfram Sang: "I2C has three driver fixes for the newly introduced drivers and one ID addition for the i801 driver" * 'i2c/for-current-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: i2c-stm32f7: make structure stm32f7_setup static const i2c: ensure termination of *_device_id tables i2c: i801: Add support for Intel Cedar Fork i2c: stm32f7: fix setup structure
2017-10-07Merge tag 'mmc-v4.14-rc3' of ↵Linus Torvalds11-162/+81
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC core: - Fix driver strength selection when selecting hs400es - Delete bounce buffer handling: This change fixes a problem related to how bounce buffers are being allocated. However, instead of trying to fix that, let's just remove the mmc bounce buffer code altogether, as it has practically no use. MMC host: - meson-gx: A couple of fixes related to clock/phase/tuning - sdhci-xenon: Fix clock resource by adding an optional bus clock" * tag 'mmc-v4.14-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-xenon: Fix clock resource by adding an optional bus clock mmc: meson-gx: include tx phase in the tuning process mmc: meson-gx: fix rx phase reset mmc: meson-gx: make sure the clock is rounded down mmc: Delete bounce buffer handling mmc: core: add driver strength selection when selecting hs400es
2017-10-06Merge tag 'hwmon-for-linus-v4.14-rc4' of ↵Linus Torvalds1-8/+11
git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging Pull hwmon fix from Guenter Roeck: "Fix up error path in xgene driver" * tag 'hwmon-for-linus-v4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: hwmon: (xgene) Fix up error handling path mixup in 'xgene_hwmon_probe()'
2017-10-06Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds3-5/+23
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: - build fix to export the clk_bulk_prepare() symbol - suspend fix for Samsung Exynos SoCs where we need to keep clks on across suspend - two critical clk markings for clks that shouldn't ever turn off on Rockchip SoCs - a fix for a copy-paste mistake on Rockchip rk3128 causing some clks to touch the same bit and trample over one another * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle clk: Export clk_bulk_prepare() clk: rockchip: add sclk_timer5 as critical clock on rk3128 clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error clk: rockchip: add pclk_pmu as critical clock on rk3128
2017-10-06Merge tag 'arc-4.14-rc4' of ↵Linus Torvalds17-28/+130
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC udpates from Vineet Gupta: - updates for various platforms - boot log updates for upcoming HS48 family of cores (dual issue) * tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz ARC: fix allnoconfig build warning ARCv2: boot log: identify HS48 cores (dual issue) ARC: boot log: decontaminate ARCv2 ISA_CONFIG register arc: remove redundant UTS_MACHINE define in arch/arc/Makefile ARC: [plat-eznps] Update platform maintainer as Noam left ARC: [plat-hsdk] use actual clk driver to manage cpu clk ARC: [*defconfig] Reenable soft lock-up detector ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency ARC: [plat-axs103] Add temporary quirk to reset ethernet IP
2017-10-06Merge tag 'xfs-4.14-fixes-4' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linuxLinus Torvalds2-3/+30
Pull xfs fixes from Darrick Wong: - fix a race between overlapping copy on write aio - fix cow fork swapping when we defragment reflinked files * tag 'xfs-4.14-fixes-4' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux: xfs: handle racy AIO in xfs_reflink_end_cow xfs: always swap the cow forks when swapping extents
2017-10-06Merge branch 'for-linus' of git://git.kernel.dk/linux-blockLinus Torvalds9-22/+45
Pull block fixes from Jens Axboe: "A collection of fixes for this series. This contains: - NVMe pull request from Christoph, one uuid attribute fix, and one fix for the controller memory buffer address for remapped BARs. - use-after-free fix for bsg, from Benjamin Block. - bcache race/use-after-free fix for a list traversal, fixing a regression in this merge window. From Coly Li. - null_blk change configfs dependency change from a 'depends' to a 'select'. This is a change from this merge window as well. From me. - nbd signal fix from Josef, fixing a regression introduced with the status code changes. - nbd MAINTAINERS mailing list entry update. - blk-throttle stall fix from Joseph Qi. - blk-mq-debugfs fix from Omar, fixing an issue where we don't register the IO scheduler debugfs directory, if the driver is loaded with it. Only shows up if you switch through the sysfs interface" * 'for-linus' of git://git.kernel.dk/linux-block: bsg-lib: fix use-after-free under memory-pressure nvme-pci: Use PCI bus address for data/queues in CMB blk-mq-debugfs: fix device sched directory for default scheduler null_blk: change configfs dependency to select blk-throttle: fix possible io stall when upgrade to max MAINTAINERS: update list for NBD nbd: fix -ERESTARTSYS handling nvme: fix visibility of "uuid" ns attribute bcache: use llist_for_each_entry_safe() in __closure_wake_up()
2017-10-06Merge tag 'pci-v4.14-fixes-4' of ↵Linus Torvalds3-27/+50
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "Fix legacy IDE probe issues exposed by recent PCI core IRQ mapping changes (Bartlomiej Zolnierkiewicz, Lorenzo Pieralisi)" * tag 'pci-v4.14-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: ide: fix IRQ assignment for PCI bus order probing ide: pci: free PCI BARs on initialization failure ide: free hwif->portdev on hwif_init() failure
2017-10-06Merge tag 'arm64-fixes' of ↵Linus Torvalds6-7/+45
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - Bring initialisation of user space undefined instruction handling early (core_initcall) since late_initcall() happens after modprobe in initramfs is invoked. Similar fix for fpsimd initialisation - Increase the kernel stack when KASAN is enabled - Bring the PCI ACS enabling earlier via the iort_init_platform_devices() - Fix misleading data abort address printing (decimal vs hex) * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Ensure fpsimd support is ready before userspace is active arm64: Ensure the instruction emulation is ready for userspace arm64: Use larger stacks when KASAN is selected ACPI/IORT: Fix PCI ACS enablement arm64: fix misleading data abort decoding
2017-10-06Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds7-13/+20
Pull KVM fixes from Radim Krčmář: - fix PPC XIVE interrupt delivery - fix x86 RCU breakage from asynchronous page faults when built without PREEMPT_COUNT - fix x86 build with -frecord-gcc-switches - fix x86 build without X86_LOCAL_APIC * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: add X86_LOCAL_APIC dependency x86/kvm: Move kvm_fastop_exception to .fixup section kvm/x86: Avoid async PF preempting the kernel incorrectly KVM: PPC: Book3S: Fix server always zero from kvmppc_xive_get_xive()
2017-10-06Merge tag 'for-linus' of ↵Linus Torvalds9-14/+34
git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma Pull rdma fixes from Doug Ledford: "This is a pretty small pull request. Only 6 patches in total. There are no outstanding -rc patches on the mailing list after this pull request, so only if some new issues are discovered in the remainder of the rc cycles will you hear from me again. Summary: - a fix for iwpm netlink usage - a fix for error unwinding in mlx5 - two fixes to vlan handling in qedr - a couple small i40iw fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: i40iw: Fix port number for query QP i40iw: Add missing memory barriers RDMA/qedr: Parse vlan priority as sl RDMA/qedr: Parse VLAN ID correctly and ignore the value of zero IB/mlx5: Fix label order in error path handling RDMA/iwpm: Properly mark end of NL messages
2017-10-06Merge branch 'for-4.14-rc4' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux Pull btrfs fixes from David Sterba: "Two more fixes for bugs introduced in 4.13. The sector_t problem with 32bit architecture and !LBDAF config seems serious but the number of affected deployments is hopefully low. The clashing status bits could lead to a confusing in-memory state of the whole-filesystem operations if used with the quota override sysfs knob" * 'for-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux: Btrfs: fix overlap of fs_info::flags values btrfs: avoid overflow when sector_t is 32 bit
2017-10-06Merge tag 'ceph-for-4.14-rc4' of git://github.com/ceph/ceph-clientLinus Torvalds2-10/+9
Pull ceph fixes from Ilya Dryomov: "Two fixups for CephFS snapshot-handling patches in -rc1" * tag 'ceph-for-4.14-rc4' of git://github.com/ceph/ceph-client: ceph: fix __choose_mds() for LSSNAP request ceph: properly queue cap snap for newly created snap realm
2017-10-06ARC: [plat-hsdk]: Add reset controller node to manage ethernet resetEugeniy Paltsev2-0/+10
DW ethernet controller on HSDK hangs sometimes after SW reset, so add reset node to make possible to reset DW ethernet controller HW. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
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