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2020-09-15drm/msm/dp: Add Display Port HPD featureTanmay Shah7-35/+182
Configure HPD registers in DP controller and enable HPD interrupt. Add interrupt to handle HPD connect and disconnect events. Changes in v8: None Signed-off-by: Tanmay Shah <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dpu: add display port support in DPUJeykumar Sankaran2-15/+58
Add display port support in DPU by creating hooks for DP encoder enumeration and encoder mode initialization. changes in v2: - rebase on [2] (Sean Paul) - remove unwanted error checks and switch cases (Jordan Crouse) [1] https://lwn.net/Articles/768265/ [2] https://lkml.org/lkml/2018/11/17/87 changes in V3: -- Moved this change as part of the DP driver changes. -- Addressed compilation issues on the latest code base. Changes in v6: -- Fix checkpatch.pl warning Changes in v7: Remove depends-on tag from commit message. Changes in v8: None Changes in v9: None Signed-off-by: Jeykumar Sankaran <[email protected]> Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dp: add support for DP PLL driverChandan Uddaraju14-17/+1294
Add the needed DP PLL specific files to support display port interface on msm targets. The DP driver calls the DP PLL driver registration. The DP driver sets the link and pixel clock sources. Changes in v2: -- Update copyright markings on all relevant files. -- Use DRM_DEBUG_DP for debug msgs. Changes in v4: -- Update the DP link clock provider names Changes in V5: -- Addressed comments from Stephen Boyd, Rob clark. Changes in V6: -- Remove PLL as separate driver and include PLL as DP module -- Remove redundant clock parsing from PLL module and make DP as clock provider -- Map USB3 DPCOM and PHY IO using hardcoded register address and move mapping form parser to PLL module -- Access DP PHY modules from same base address using offsets instead of deriving base address of individual module from device tree. -- Remove dp_pll_10nm_util.c and include its functionality in dp_pll_10nm.c -- Introduce new data structures private to PLL module Changes in v7: -- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig -- Remove set_parent from determin_rate API -- Remove phy_pll_vco_div_clk from parent list -- Remove flag CLK_DIVIDER_ONE_BASED -- Remove redundant cell-index property parsing Changes in v8: -- Unregister hardware clocks during driver cleanup Changes in v9: -- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL Changes in v10: -- Limit 10nm PLL function scope Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dp: add displayPort driver supportChandan Uddaraju27-3/+8061
Add the needed displayPort files to enable DP driver on msm target. "dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver. Changes in v12: -- Add support of pm ops in display port driver -- Clear bpp depth bits before writing to MISC register -- Fix edid read Previous Change log: https://lkml.kernel.org/lkml/[email protected]/ Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Co-developed-by: Abhinav Kumar <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]> Co-developed-by: Kuogee Hsieh <[email protected]> Signed-off-by: Kuogee Hsieh <[email protected]> Co-developed-by: Guenter Roeck <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> Co-developed-by: Stephen Boyd <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm: add constant N value in helper fileChandan Uddaraju2-1/+2
The constant N value (0x8000) is used by i915 DP driver. Define this value in dp helper header file to use in multiple Display Port drivers. Change i915 driver accordingly. Change in v6: Change commit message Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Jani Nikula <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm: Get rid of the REG_ADRENO offsetsJordan Crouse7-234/+178
As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm: a6xx: Use WHERE_AM_I for eligible targetsJordan Crouse2-3/+93
Support the WHERE_AM_I opcode for the A618, A630 and A640 GPUs if the microcode supports it. The WHERE_AM_I opcode allows the RPTR shadow to be updated in priviliged memory which protects the shadow from being read or written from user submissions. A650 already supports extended APRIV have built in hardware support for to access privilged memory from the CP and can go back to using the hardware RPTR shadow feature. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm: Allow a5xx to mark the RPTR shadow as privilegedJordan Crouse7-13/+109
Newer microcode versions have support for the CP_WHERE_AM_I opcode which allows the RPTR shadow memory to be marked as privileged to protect it from corruption. Move the RPTR shadow into its own buffer and protect it it if the current microcode version supports the new feature. We can also re-enable preemption for those targets that support CP_WHERE_AM_I. Start out by preemptively assuming that we can enable preemption and disable it in a5xx_hw_init if the microcode version comes back as too old. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm: Show process names in gem_describeRob Clark6-9/+34
In $debugfs/gem we already show any vma(s) associated with an object. Also show process names if the vma's address space is a per-process address space. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm/a6xx: Add support for per-instance pagetablesJordan Crouse3-0/+64
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]>
2020-09-12drm/msm: Add support for private address space instancesJordan Crouse5-6/+48
Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces. The default will return a pointer to the global address space. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Add support to create a local pagetableJordan Crouse4-3/+215
Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Set the global virtual address range from the IOMMU domainJordan Crouse2-2/+18
Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables). Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Drop context arg to gpu->submit()Jordan Crouse7-25/+17
Now that we can get the ctx from the submitqueue, the extra arg is redundant. Signed-off-by: Jordan Crouse <[email protected]> [split out of previous patch to reduce churny noise] Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Add a context pointer to the submitqueueJordan Crouse6-4/+30
Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue. Co-developed-by: Rob Clark <[email protected]> Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Set adreno_smmu as gpu's drvdataRob Clark3-4/+6
This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm/gpu: Add dev_to_gpu() helperRob Clark3-9/+12
In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Add private interface for adreno-smmuRob Clark1-0/+36
This interface will be used for drm/msm to coordinate with the qcom_adreno_smmu_impl to enable/disable TTBR0 translation. Once TTBR0 translation is enabled, the GPU's CP (Command Processor) will directly switch TTBR0 pgtables (and do the necessary TLB inv) synchronized to the GPU's operation. But help from the SMMU driver is needed to initially bootstrap TTBR0 translation, which cannot be done from the GPU. Since this is a very special case, a private interface is used to avoid adding highly driver specific things to the public iommu interface. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm: Remove dangling submitqueue referencesRob Clark1-1/+3
Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]>
2020-09-12drm/msm/a6xx: fix a potential overflow issueZhenzhong Duan1-1/+1
It's allocating an array of a6xx_gpu_state_obj structure rathor than its pointers. This patch fix it. Signed-off-by: Zhenzhong Duan <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm/adreno: fix probe without iommuLuca Weiss1-2/+8
The function iommu_domain_alloc returns NULL on platforms without IOMMU such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to gpu->aspace so the correct code path wasn't taken. Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization") Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm/gpu: Add suspend/resume tracepointsRob Clark3-0/+32
Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm/dsi: add support for 7nm DSI PHY/PLLJonathan Marek11-2/+1718
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250. Implementation is based on 10nm driver, but updated based on the downstream 7nm driver. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> (SM8250) Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm/dsi: add DSI config for sm8150 and sm8250Jonathan Marek2-1/+6
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config is re-used as the config is the same. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> (SM8250) Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timingJonathan Marek1-2/+0
The clk_pre/clk_post values in shared_timings are used instead, and these are unused. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> (SM8250) Signed-off-by: Rob Clark <[email protected]>
2020-09-12drm/msm: Drop local dma_parmsRobin Murphy1-9/+1
Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms for platform devices"), struct platform_device already provides a dma_parms structure, so we can save allocating another one. Also the DMA segment size is simply a size, not a bitmask. Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-09drm/msm: Convert shrinker msgs to tracepointsRob Clark2-2/+29
This reduces the spam in dmesg when we start hitting the shrinker, and replaces it with something we can put on a timeline while profiling or debugging system issues. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
2020-09-09drm/msm/gpu: Add GPU freq_change tracesRob Clark3-0/+36
Technically the GMU specific one is a bit redundant, but it was useful to track down a bug. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]>
2020-09-09drm/msm: Drop debug print in _dpu_crtc_setup_lm_bounds()Stephen Boyd1-2/+0
This function is called quite often if you have a blinking cursor on the screen, hello page flip. Let's drop this debug print here because it means enabling the print via the module parameter starts to spam the debug console. Cc: Abhinav Kumar <[email protected]> Cc: Jeykumar Sankaran <[email protected]> Cc: Jordan Crouse <[email protected]> Cc: Sean Paul <[email protected]> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-09drm/msm: Avoid div-by-zero in dpu_crtc_atomic_check()Stephen Boyd1-3/+5
The cstate->num_mixers member is only set to a non-zero value once dpu_encoder_virt_mode_set() is called, but the atomic check function can be called by userspace before that. Let's avoid the div-by-zero here and inside _dpu_crtc_setup_lm_bounds() by skipping this part of the atomic check if dpu_encoder_virt_mode_set() hasn't been called yet. This fixes an UBSAN warning: UBSAN: Undefined behaviour in drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:860:31 division by zero CPU: 7 PID: 409 Comm: frecon Tainted: G S 5.4.31 #128 Hardware name: Google Trogdor (rev0) (DT) Call trace: dump_backtrace+0x0/0x14c show_stack+0x20/0x2c dump_stack+0xa0/0xd8 __ubsan_handle_divrem_overflow+0xec/0x110 dpu_crtc_atomic_check+0x97c/0x9d4 drm_atomic_helper_check_planes+0x160/0x1c8 drm_atomic_helper_check+0x54/0xbc drm_atomic_check_only+0x6a8/0x880 drm_atomic_commit+0x20/0x5c drm_atomic_helper_set_config+0x98/0xa0 drm_mode_setcrtc+0x308/0x5dc drm_ioctl_kernel+0x9c/0x114 drm_ioctl+0x2ac/0x4b0 drm_compat_ioctl+0xe8/0x13c __arm64_compat_sys_ioctl+0x184/0x324 el0_svc_common+0xa4/0x154 el0_svc_compat_handler+0x Cc: Abhinav Kumar <[email protected]> Cc: Jeykumar Sankaran <[email protected]> Cc: Jordan Crouse <[email protected]> Cc: Sean Paul <[email protected]> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Tested-by: Sai Prakash Ranjan <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-09drm/msm/dpu: clean up some impossibilitiesRob Clark1-78/+13
Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]>
2020-09-09drm/msm/dpu: move vblank events to complete_commit()Rob Clark1-1/+1
We could get a vblank event racing with the current atomic commit, resulting in sending the pageflip event to userspace early, causing tearing. On the other hand, complete_commit() ensures that the pending flush is complete. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]>
2020-09-04drm/msm/adreno: remove return value of function XX_printBernard Zhao1-14/+7
XX_print like pfp_print/me_print/meq_print/roq_print are just used in file a5xx_debugfs.c. And these function always return 0, this return value is meaningless. This change is to make the code a bit more readable. Signed-off-by: Bernard Zhao <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm: drop cache sync hackRob Clark1-14/+4
Now that it isn't causing problems to use dma_map/unmap, we can drop the hack of using dma_sync in certain cases. Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm/mdp5: Remove unused downstream bus scaling apisSai Prakash Ranjan2-92/+0
MSM bus scaling has moved on to use interconnect framework and downstream bus scaling apis are not present anymore. Remove them as they are nop anyways in the current code, no functional change. Signed-off-by: Sai Prakash Ranjan <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm/mdp4: Remove unused downstream bus scaling apisSai Prakash Ranjan3-111/+0
MSM bus scaling has moved on to use interconnect framework and downstream bus scaling apis are not present anymore. Remove them as they are nop anyways in the current code, no functional change. Signed-off-by: Sai Prakash Ranjan <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm/dpu: add support for clk and bw scaling for displayKalyan Thota8-23/+233
This change adds support to scale src clk and bandwidth as per composition requirements. Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling. Changes in v1: - Address armv7 compilation issues with the patch (Rob) Signed-off-by: Kalyan Thota <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm: Disable the RPTR shadowJordan Crouse6-27/+43
Disable the RPTR shadow across all targets. It will be selectively re-enabled later for targets that need it. Cc: [email protected] Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm: Disable preemption on all 5xx targetsJordan Crouse1-1/+2
Temporarily disable preemption on a5xx targets pending some improvements to protect the RPTR shadow from being corrupted. Cc: [email protected] Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm: Enable expanded apriv support for a650Jordan Crouse4-4/+19
a650 supports expanded apriv support that allows us to map critical buffers (ringbuffer and memstore) as as privileged to protect them from corruption. Cc: [email protected] Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-04drm/msm: Split the a5xx preemption recordJordan Crouse2-5/+21
The main a5xx preemption record can be marked as privileged to protect it from user access but the counters storage needs to be remain unprivileged. Split the buffers and mark the critical memory as privileged. Cc: [email protected] Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-22drm/msm/a6xx: fix frequency not always being restored on GMU resumeJonathan Marek1-0/+1
The patch reorganizing the set_freq function made it so the gmu resume doesn't always set the frequency, because a6xx_gmu_set_freq() exits early when the frequency hasn't been changed. Note this always happens when resuming GMU after recovering from a hang. Use a simple workaround to prevent this from happening. Fixes: 1f60d11423db ("drm: msm: a6xx: send opp instead of a frequency") Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-22drm/msm/a6xx: add module param to enable debugbus snapshotRob Clark3-1/+8
For production devices, the debugbus sections will typically be fused off and empty in the gpu device coredump. But since this may contain data like cache contents, don't capture it by default. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-22drm/msm/a6xx: fix crashdec section name typoRob Clark1-1/+1
Backport note: maybe wait some time for the crashdec MR[1] to look for both the old typo'd name and the corrected name to land in mesa 20.2 [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6242 Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-22drm/msm/a6xx: fix gmu start on newer firmwareDmitry Baryshkov1-1/+11
New Qualcomm firmware has changed a way it reports back the 'started' event. Support new register values. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-21drm/msm: enable vblank during atomic commitsRob Clark1-0/+36
This has roughly the same effect as drm_atomic_helper_wait_for_vblanks(), basically just ensuring that vblank accounting is enabled so that we get valid timestamp/seqn on pageflip events. Signed-off-by: Rob Clark <[email protected]> Tested-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-18drm/msm: add shutdown support for display platform_driverKrishna Manikandan1-0/+8
Define shutdown callback for display drm driver, so as to disable all the CRTCS when shutdown notification is received by the driver. This change will turn off the timing engine so that no display transactions are requested while mmu translations are getting disabled during reboot sequence. Signed-off-by: Krishna Manikandan <[email protected]> Changes in v2: - Remove NULL check from msm_pdev_shutdown (Stephen Boyd) - Change commit text to reflect when this issue was uncovered (Sai Prakash Ranjan) Signed-off-by: Rob Clark <[email protected]>
2020-08-17drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDRSharat Masetty1-8/+17
This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Also since the icc path voting is handled completely in the opp driver, remove the icc_path handle and its usage in the drm driver. Signed-off-by: Sharat Masetty <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-17drm/msm/gpu: make ringbuffer readonlyRob Clark1-1/+2
The GPU has no business writing into the ringbuffer, let's make it readonly to the GPU. Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support") Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-08-17drm/msm/adreno: fix updating ring fenceRob Clark1-1/+1
We need to set it to the most recent completed fence, not the most recent submitted. Otherwise we have races where we think we can retire submits that the GPU is not finished with, if the GPU doesn't manage to overwrite the seqno before we look at it. This can show up with hang recovery if one of the submits after the crashing submit also hangs after it is replayed. Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers") Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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