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2018-09-26drm/amdgpu: move more defines into amdgpu_irq.hChristian König35-95/+94
Everything that isn't related to the IH ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: move more interrupt processing into amdgpu_irq.cChristian König3-21/+38
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by: Christian König <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Move fence SW fallback warning v3Andrey Grodzovsky2-5/+9
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-off-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: cleanup amdgpu_ih.cChristian König9-102/+84
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: make function pointers mandatoryChristian König20-90/+55
We always want those to be setup correctly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: drop extra newline in amdgpu_iv traceChristian König1-1/+1
That is superflous here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: fix the page fault of raven2Huang Rui2-2/+4
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Disable dpm features on smu7/8 when suspendRex Zhu2-18/+32
Need to disable dpm features before halt rlc. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Remove redundant code in gfx_v8_0.cRex Zhu1-20/+0
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hang Zhou <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Halt rlc/cp in rlc_safe_modeRex Zhu1-27/+59
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hang Zhou <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Refine function nameRex Zhu4-11/+11
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2Andrey Grodzovsky1-2/+3
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by: Andrey Grodzovsky <[email protected]> Suggested-by: Christian Konig <[email protected]> Reviewed-and-Tested-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Vega20 bring up on amdkfd sideShaoyun Liu8-0/+29
Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]>
2018-09-26drm/amdgpu: Add vega20 support on kfd probeShaoyun Liu1-0/+1
Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]>
2018-09-26drm/amd: Interface change to support 64 bit page_table_baseShaoyun Liu9-23/+28
amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Make the number of SDMA queues variableShaoyun Liu4-4/+17
Vega20 supports 8 SDMA queues per engine Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10Emily Deng3-11/+37
Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by: Emily Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Doorbell assignment for 8 sdma user queue per engineShaoyun Liu3-25/+33
Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: remove unnecessary forward declarationFelix Kuehling1-2/+0
struct vi_sdma_mqd is defined in vi_structs.h. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Add wavefront context save state retrieval ioctlJay Cornwall9-1/+159
Wavefront context save data is of interest to userspace clients for debugging static wavefront state. The MQD contains two parameters required to parse the control stack and the control stack itself is kept in the MQD from gfx9 onwards. Add an ioctl to fetch the context save area and control stack offsets and to copy the control stack to a userspace address if it is kept in the MQD. Signed-off-by: Jay Cornwall <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Report SDMA firmware version in the topologyFelix Kuehling3-3/+11
Also save the version in struct kfd_dev so we only need to query it once. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Enable BAD_OPCODE intr for gfx8Harish Kasiviswanathan1-1/+2
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in response to bad opcodes in a CP queue. Signed-off-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: KFD doesn't support TONGA SRIOVEmily Deng1-16/+0
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV environment, it will let compute ring IB test fail. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Shaoyun.liu <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: reflect atomic support in IO link propertiesEric Huang3-12/+39
Add the flags of properties according to Asic type and pcie capabilities. Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Add warning message for INT SW fallback.Andrey Grodzovsky1-0/+1
Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26Revert "drm/amdgpu: remove fence fallback"Andrey Grodzovsky3-0/+58
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:No action when VCN PG state is unchangedJames Zhu2-2/+11
When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: remove redundant null pointer check before kfreezhong jiang1-6/+2
kfree has taken the null pointer into account. hence it is safe to remove the redundant null pointer check before kfree. Signed-off-by: zhong jiang <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: print smc feature mask in debugfs amdgpu_pm_infoAlex Deucher1-0/+5
Print the enabled smc feature mask in amdgpu_pm_info for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega20Alex Deucher1-0/+5
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega12Alex Deucher1-1/+5
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega10Alex Deucher3-4/+11
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: add new AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK sensorAlex Deucher1-0/+1
For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20Alex Deucher3-24/+34
For consistency with other asics. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12Alex Deucher3-12/+22
For consistency with other asics. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: Move vega10_enable_smc_featuresAlex Deucher6-12/+15
to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add get_argument callback for vega20Alex Deucher4-32/+15
For consistency with other vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Raise dispclk value for dce120 by 15%Nicholas Kazlauskas1-0/+3
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by: Nick Sarnie <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: fix gamma not being appliedSivapiriyanKumarasamy1-5/+14
[WHY] Previously night light forced a full update by applying a transfer function update regardless of if it was changed. This logic was removed, Now gamma surface updates are only applied when there is also a plane info update, this does not work in cases such as using the night light slider. [HOW] When moving the night light slider we will perform a full update if the gamma has changed and there is a surface, even when the surface has not changed. Also get stream updates in setgamma prior to update planes and stream. Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Remove mst_hotplug_workLeo Li2-12/+0
[Why] The work struct's schedule call was removed a while ago, making this useless. [How] Remove it. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Guard against null stream dereference in do flipNicholas Kazlauskas1-1/+14
[Why] During suspend under some hardware configurations can result in a series of atomic commits with a NULL stream status - which causes a NULL pointer dereference. This should be guarded. [How] Exit early from the function - if we can't access the stream then there isn't anything that can be done here. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Stereo 3D support in VSCEric Bernstein1-4/+54
[Why] Need to add strere 3D information in VSC [How] Update mod_build_vsc_infopacket with stereo info Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: dc 3.1.67Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Steven Chiu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: program v_update and v_ready with proper fieldSu Sung Chung3-13/+13
[WHY] There are two different variables used to calculate v_update and v_ready, one for validation and the other for performance parameter calculation. Before the variable for validation was used which caused underflow on 1080edp with vsr enabled [HOW] program v_update and v_ready with the variables for performance parameter calculation Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Add color bit info to freesync infoframeSivapiriyanKumarasamy4-21/+198
Parse the native color bit and send it to freesync module for future use Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: add pp_smu NULL pointer checkCharlene Liu1-1/+1
add pp_smu NULL ptr check Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: use proper pipe_ctx indexSamson Tam1-2/+18
Use link->link_index as index to pipe_ctx[] to get proper link information instead of using index 0 to avoid potential miss matches. Signed-off-by: Samson Tam <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Refactor FPGA-specific link setupNikola Cornij3-40/+32
FPGA doesn't program backend, so we don't need certain link settings (audio stream for example). Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Return error immediately if load firmware failedRex Zhu1-4/+6
this can avoid hard hang and be useful for debug. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Honour DC's clock limits on RvRex Zhu1-8/+17
Honour display's request for min engine clock/memory clock. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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