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2015-08-14Merge branches 'pci/hotplug', 'pci/iommu', 'pci/irq' and ↵Bjorn Helgaas19-271/+209
'pci/virtualization' into next * pci/hotplug: PCI: pciehp: Remove ignored MRL sensor interrupt events PCI: pciehp: Remove unused interrupt events PCI: pciehp: Handle invalid data when reading from non-existent devices PCI: Hold pci_slot_mutex while searching bus->slots list PCI: Protect pci_bus->slots with pci_slot_mutex, not pci_bus_sem PCI: pciehp: Simplify pcie_poll_cmd() PCI: Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slot * pci/iommu: PCI: Remove pci_ats_enabled() PCI: Stop caching ATS Invalidate Queue Depth PCI: Move ATS declarations to linux/pci.h so they're all together PCI: Clean up ATS error handling PCI: Use pci_physfn() rather than looking up physfn by hand PCI: Inline the ATS setup code into pci_ats_init() PCI: Rationalize pci_ats_queue_depth() error checking PCI: Reduce size of ATS structure elements PCI: Embed ATS info directly into struct pci_dev PCI: Allocate ATS struct during enumeration iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth * pci/irq: PCI: Kill off set_irq_flags() usage * pci/virtualization: PCI: Add ACS quirks for Intel I219-LM/V
2015-08-13PCI: Remove pci_ats_enabled()Bjorn Helgaas2-5/+3
Remove pci_ats_enabled(). There are no callers outside the ATS code itself. We don't need to check ats_cap, because if we don't find an ATS capability, we'll never set ats_enabled. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Stop caching ATS Invalidate Queue DepthBjorn Helgaas2-6/+4
Stop caching the Invalidate Queue Depth in struct pci_dev. pci_ats_queue_depth() is typically called only once per device, and it returns a fixed value per-device, so callers who need the value frequently can cache it themselves. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Move ATS declarations to linux/pci.h so they're all togetherBjorn Helgaas2-42/+9
Move ATS declarations to linux/pci.h so they're all in one place. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Clean up ATS error handlingBjorn Helgaas1-5/+5
There's no need to BUG() if we enable ATS when it's already enabled. We don't need to BUG() when disabling ATS on a device that doesn't support ATS or if it's already disabled. If ATS is enabled, certainly we found an ATS capability in the past, so it should still be there now. Clean up these error paths. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Use pci_physfn() rather than looking up physfn by handBjorn Helgaas1-4/+4
Use the pci_physfn() helper rather than looking up physfn by hand. No functional change. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Inline the ATS setup code into pci_ats_init()Bjorn Helgaas1-6/+1
The ATS setup code in ats_alloc_one() is only used by pci_ats_init(), so inline it there. No functional change. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Rationalize pci_ats_queue_depth() error checkingBjorn Helgaas1-4/+4
We previously returned -ENODEV for devices that don't support ATS (except that we always returned 0 for VFs, whether or not they support ATS). For consistency, always return -EINVAL (not -ENODEV) if the device doesn't support ATS. Return zero for VFs that support ATS. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Reduce size of ATS structure elementsBjorn Helgaas1-3/+3
The extended capabilities list is linked with 12-bit pointers, and the ATS Smallest Translation Unit and Invalidate Queue Depth fields are both 5 bits. Use u16 and u8 to hold the extended capability address and the stu and qdep values. No functional change. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Embed ATS info directly into struct pci_devBjorn Helgaas4-53/+27
The pci_ats struct is small and will get smaller, so I don't think it's worth allocating it separately from the pci_dev struct. Embed the ATS fields directly into struct pci_dev. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-13PCI: Allocate ATS struct during enumerationBjorn Helgaas5-57/+56
Previously, we allocated pci_ats structures when an IOMMU driver called pci_enable_ats(). An SR-IOV VF shares the STU setting with its PF, so when enabling ATS on the VF, we allocated a pci_ats struct for the PF if it didn't already have one. We held the sriov->lock to serialize threads concurrently enabling ATS on several VFS so only one would allocate the PF pci_ats. Gregor reported a deadlock here: pci_enable_sriov sriov_enable virtfn_add mutex_lock(dev->sriov->lock) # acquire sriov->lock pci_device_add device_add BUS_NOTIFY_ADD_DEVICE notifier chain iommu_bus_notifier amd_iommu_add_device # iommu_ops.add_device init_iommu_group iommu_group_get_for_dev iommu_group_add_device __iommu_attach_device amd_iommu_attach_device # iommu_ops.attach_device attach_device pci_enable_ats mutex_lock(dev->sriov->lock) # deadlock There's no reason to delay allocating the pci_ats struct, and if we allocate it for each device at enumeration-time, there's no need for locking in pci_enable_ats(). Allocate pci_ats struct during enumeration, when we initialize other capabilities. Note that this implementation requires ATS to be enabled on the PF first, before on any of the VFs because the PF controls the STU for all the VFs. Link: http://permalink.gmane.org/gmane.linux.kernel.iommu/9433 Reported-by: Gregor Dick <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]>
2015-08-11PCI: Add ACS quirks for Intel I219-LM/VAlex Williamson1-0/+3
The Intel 100-series chipset now includes the integrated Ethernet as part of a multifunction package. The Ethernet function does not include native ACS support, but Intel confirms that the device is not capable of peer-to- peer within the package. We can therefore quirk it to expose the isolation. Signed-off-by: Alex Williamson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: John Ronciak <[email protected]>
2015-08-11PCI: Kill off set_irq_flags() usageRob Herring7-9/+0
set_irq_flags is ARM-specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions, and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE, and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jingoo Han <[email protected]> CC: Kishon Vijay Abraham I <[email protected]> CC: Murali Karicheri <[email protected]> CC: Thierry Reding <[email protected]> CC: Stephen Warren <[email protected]> CC: Alexandre Courbot <[email protected]> CC: Jingoo Han <[email protected]> CC: Pratyush Anand <[email protected]> CC: Simon Horman <[email protected]> CC: Michal Simek <[email protected]> CC: "Sören Brinkmann" <[email protected]>
2015-08-10PCI: pciehp: Remove ignored MRL sensor interrupt eventsBjorn Helgaas2-20/+7
We queued interrupt events for the MRL being opened or closed, but the code in interrupt_event_handler() that handles these events ignored them. Stop enabling MRL interrupts and remove the ignored events. Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-10PCI: pciehp: Remove unused interrupt eventsBjorn Helgaas1-7/+3
The list of interrupt events (INT_BUTTON_IGNORE, INT_PRESENCE_ON, etc.) was copied from other hotplug drivers, but pciehp doesn't use them all. Remove the interrupt events that aren't used by pciehp. Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-10PCI: pciehp: Handle invalid data when reading from non-existent devicesJarod Wilson1-0/+17
It's platform-dependent, but an MMIO read to a non-existent PCI device generally returns data with all bits set. This happens when the host bridge or Root Complex times out waiting for a response from the device and fabricates return data to complete the CPU's read. One example, reported in the bugzilla below, involved this hierarchy: pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port pci 0000:07:00.0: BCM57762 NIC Unplugging the Thunderbolt switch and the NIC below it resulted in this: pciehp 0000:03:03.0: Surprise Removal tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff pciehp 0000:06:00.0: unloading service driver pciehp pciehp 0000:06:00.0: pcie_isr: intr_loc 11f pciehp 0000:06:00.0: Switch interrupt received pciehp 0000:06:00.0: Latch open on Slot pciehp 0000:06:00.0: Attention button interrupt received pciehp 0000:06:00.0: Button pressed on Slot pciehp 0000:06:00.0: Presence/Notify input change pciehp 0000:06:00.0: Card present on Slot pciehp 0000:06:00.0: Power fault interrupt received pciehp 0000:06:00.0: Data Link Layer State change pciehp 0000:06:00.0: Link Up event The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0 and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver remove methods. Since the NIC was already gone, tg3 received 0xffffffff when it tried to read from the device. The resulting timeout is a tg3 issue and not of interest here. Similarly, since the 06:00.0 Thunderbolt switch was already gone, pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp thought that was valid status showing that many events had happened: the latch had been opened, the attention button had been pressed, a card was now present, and the link was now up. These are all wrong, of course, but pciehp went on to try to power up and enumerate devices below the non-existent bridge: pciehp 0000:06:00.0: PCI slot - powering on due to button press pciehp 0000:06:00.0: Surprise Insertion pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff [bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()] Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841 Suggested-by: Bjorn Helgaas <[email protected]> Signed-off-by: Jarod Wilson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-08-04Merge branches 'pci/irq', 'pci/misc', 'pci/resource' and ↵Bjorn Helgaas31-215/+239
'pci/virtualization' into next * pci/irq: PCI/MSI: Free legacy IRQ when enabling MSI/MSI-X PCI: Add helpers to manage pci_dev->irq and pci_dev->irq_managed PCI, x86: Implement pcibios_alloc_irq() and pcibios_free_irq() PCI: Add pcibios_alloc_irq() and pcibios_free_irq() * pci/misc: PCI: Remove unused "pci_probe" flags PCI: Add VPD function 0 quirk for Intel Ethernet devices PCI: Add dev_flags bit to access VPD through function 0 PCI / ACPI: Fix pci_acpi_optimize_delay() comment PCI: Remove a broken link in quirks.c PCI: Remove useless redundant code PCI: Simplify pci_find_(ext_)capability() return value checks PCI: Move PCI_FIND_CAP_TTL to pci.h and use it in quirks PCI: Add pcie_downstream_port() (true for Root and Switch Downstream Ports) PCI: Fix pcie_port_device_resume() comment PCI: Shift PCI_CLASS_NOT_DEFINED consistently with other classes PCI: Revert aeb30016fec3 ("PCI: add Intel USB specific reset method") PCI: Fix TI816X class code quirk PCI: Fix generic NCR 53c810 class code quirk PCI: Use PCI_CLASS_SERIAL_USB instead of bare number PCI: Add quirk for Intersil/Techwell TW686[4589] AV capture cards PCI: Remove Intel Cherrytrail D3 delays * pci/resource: PCI: Call pci_read_bridge_bases() from core instead of arch code * pci/virtualization: PCI: Restore ACS configuration as part of pci_restore_state()
2015-08-04Merge branches 'pci/host-designware', 'pci/host-xgene' and 'pci/host-xilinx' ↵Bjorn Helgaas5-21/+36
into next * pci/host-designware: PCI: designware: Don't complain missing *config* reg space if va_cfg0 is set * pci/host-xgene: PCI: xgene: Add support for a 64-bit prefetchable memory window arm64: dts: Add APM X-Gene PCIe 64-bit prefetchable window PCI: xgene: Drop owner assignment from platform_driver * pci/host-xilinx: PCI: xilinx: Check for MSI interrupt flag before handling as INTx
2015-07-30PCI: Hold pci_slot_mutex while searching bus->slots listYijing Wang5-15/+19
Previously, pci_setup_device() and similar functions searched the pci_bus->slots list without any locking. It was possible for another thread to update the list while we searched it. Add pci_dev_assign_slot() to search the list while holding pci_slot_mutex. [bhelgaas: changelog, fold in CONFIG_SYSFS fix] Tested-by: Guenter Roeck <[email protected]> Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-30PCI: Protect pci_bus->slots with pci_slot_mutex, not pci_bus_semYijing Wang2-8/+13
Rajat Jain reported a deadlock when PCIe hot-add and AER recovery happen at the same time: thread 1: pciehp_enable_slot pciehp_configure_device pci_bus_add_devices pci_bus_add_device device_attach device_lock(dev) # acquire device lock ... pciehp_probe init_slot pci_hp_register pci_create_slot down_write(pci_bus_sem) # deadlock here thread 2: aer_isr_one_error aer_process_err_device do_recovery broadcast_error_message(..., report_error_detected) pci_walk_bus(..., cb=report_error_detected, ...) down_read(&pci_bus_sem) # acquire pci_bus_sem report_error_detected(dev) # cb() device_lock(dev) # deadlock here Previously, the bus->devices and bus->slots list were protected by pci_bus_sem. In pci_create_slot(), we held it for writing so we could add to the bus->slots list. Add a new local pci_slot_mutex to protect bus->slots. Hold pci_bus_sem for reading while searching the bus->devices list. [bhelgaas: changelog] Link: http://lkml.kernel.org/r/CAA93t1qpPqbih+UB0McA_d_+2rVaNkXsinAUxYzK9+JXSS+L-g@mail.gmail.com Reported-by: Rajat Jain <[email protected]> Tested-by: Guenter Roeck <[email protected]> Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-30PCI/MSI: Free legacy IRQ when enabling MSI/MSI-XJiang Liu1-1/+4
Once MSI/MSI-X is enabled by the device driver, a PCI device won't use legacy IRQs again until MSI/MSI-X is disabled. Call pcibios_free_irq() when enabling MSI/MSI-X and pcibios_alloc_irq() when disabling MSI/MSI-X. This allows arch code to manage resources associated with the legacy IRQ. [bhelgaas: changelog] Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
2015-07-30PCI: Add helpers to manage pci_dev->irq and pci_dev->irq_managedJiang Liu4-14/+27
Add pci_has_managed_irq(), pci_set_managed_irq(), and pci_reset_managed_irq() to simplify code. No functional change. [bhelgaas: changelog] Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
2015-07-30PCI, x86: Implement pcibios_alloc_irq() and pcibios_free_irq()Jiang Liu5-37/+16
To support IOAPIC hotplug, we need to allocate PCI IRQ resources on demand and free them when not used anymore. Implement pcibios_alloc_irq() and pcibios_free_irq() to dynamically allocate and free PCI IRQs. Remove mp_should_keep_irq(), which is no longer used. [bhelgaas: changelog] Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
2015-07-30PCI: Add pcibios_alloc_irq() and pcibios_free_irq()Jiang Liu2-6/+22
Add pcibios_alloc_irq() and pcibios_free_irq(), which are called when binding/unbinding PCI device drivers. PCI arch code may implement these to manage IRQ resources for hotplugged devices. [bhelgaas: changelog] Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
2015-07-27PCI: Remove unused "pci_probe" flagsBjorn Helgaas5-43/+10
The following flags are only used on x86, but they got copied to FR-V, MN10300, and SuperH: PCI_PROBE_BIOS PCI_PROBE_CONF1 PCI_PROBE_CONF2 PCI_ASSIGN_ROMS PCI_NO_CHECKS PCI_BIOS_IRQ_SCAN PCI_ASSIGN_ALL_BUSSES FR-V and MN10300 do test for PCI_ASSIGN_ROMS, but they never set it, so it's dead code. Remove the unused flags above. Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-23PCI: Call pci_read_bridge_bases() from core instead of arch codeLorenzo Pieralisi12-42/+11
When we scan a PCI bus, we read PCI-PCI bridge window registers with pci_read_bridge_bases() so we can validate the resource hierarchy. Most architectures call pci_read_bridge_bases() from pcibios_fixup_bus(), but PCI-PCI bridges are not arch-specific, so this doesn't need to be in arch-specific code. Call pci_read_bridge_bases() directly from the PCI core instead of from arch code. For alpha and mips, we now call pci_read_bridge_bases() always; previously we only called it if PCI_PROBE_ONLY was set. [bhelgaas: changelog] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Ralf Baechle <[email protected]> CC: James E.J. Bottomley <[email protected]> CC: Michael Ellerman <[email protected]> CC: Bjorn Helgaas <[email protected]> CC: Richard Henderson <[email protected]> CC: Benjamin Herrenschmidt <[email protected]> CC: David Howells <[email protected]> CC: Russell King <[email protected]> CC: Tony Luck <[email protected]> CC: David S. Miller <[email protected]> CC: Ingo Molnar <[email protected]> CC: Guenter Roeck <[email protected]> CC: Michal Simek <[email protected]> CC: Chris Zankel <[email protected]>
2015-07-23PCI: designware: Don't complain missing *config* reg space if va_cfg0 is setMurali Karicheri1-1/+1
Currently on Keystone SoCs, we always complain: keystone-pcie 21021000.pcie: missing *config* reg space Keystone uses an older version of DesignWare hardware that doesn't have ATU support. So va_cfg0_base and va_cfg1_base are already set up in ks_dw_pcie_host_init() before calling dw_pcie_host_init(), and they point to the remote config space address va (both same for Keystone). Add a check to avoid this boot noise on Keystone. Signed-off-by: Murali Karicheri <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-21PCI: Add VPD function 0 quirk for Intel Ethernet devicesMark Rustad1-0/+9
Set the PCI_DEV_FLAGS_VPD_REF_F0 flag on all Intel Ethernet device functions other than function 0, so that on multi-function devices, we will always read VPD from function 0 instead of from the other functions. [bhelgaas: changelog] Signed-off-by: Mark Rustad <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Alexander Duyck <[email protected]> CC: [email protected]
2015-07-21PCI: Add dev_flags bit to access VPD through function 0Mark Rustad2-1/+62
Add a dev_flags bit, PCI_DEV_FLAGS_VPD_REF_F0, to access VPD through function 0 to provide VPD access on other functions. This is for hardware devices that provide copies of the same VPD capability registers in multiple functions. Because the kernel expects that each function has its own registers, both the locking and the state tracking are affected by VPD accesses to different functions. On such devices for example, if a VPD write is performed on function 0, *any* later attempt to read VPD from any other function of that device will hang. This has to do with how the kernel tracks the expected value of the F bit per function. Concurrent accesses to different functions of the same device can not only hang but also corrupt both read and write VPD data. When hangs occur, typically the error message: vpd r/w failed. This is likely a firmware bug on this device. will be seen. Never set this bit on function 0 or there will be an infinite recursion. Signed-off-by: Mark Rustad <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Alexander Duyck <[email protected]> CC: [email protected]
2015-07-21PCI: xgene: Add support for a 64-bit prefetchable memory windowDuc Dang1-2/+10
X-Gene PCIe controller has registers to support multiple memory ranges. Add support for a 64-bit prefetchable memory window. [bhelgaas: changelog] Signed-off-by: Duc Dang <[email protected]> Signed-off-by: Tanmay Inamdar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-21arm64: dts: Add APM X-Gene PCIe 64-bit prefetchable windowDuc Dang1-9/+14
Add a large window (up to 64GB) for X-Gene PCIe nodes to support devices that require huge BARs. Each X-Gene PCIe node will now have two memory windows: a 32-bit non-prefetchable window and a 64-bit prefetchable window. [bhelgaas: changelog] Signed-off-by: Duc Dang <[email protected]> Signed-off-by: Tanmay Inamdar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-21PCI: Restore ACS configuration as part of pci_restore_state()Alexander Duyck1-0/+3
Previously we did not restore ACS state after a PCIe reset. This meant that we could not reassign interfaces after a system suspend because the D0->D3 transition disabled ACS, and we didn't restore it when going back to D0. Restore ACS configuration in pci_restore_state(). [bhelgaas: changelog] Signed-off-by: Alexander Duyck <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Allen Kay <[email protected]> CC: Chris Wright <[email protected]> CC: Alex Williamson <[email protected]>
2015-07-21PCI: xilinx: Check for MSI interrupt flag before handling as INTxRussell Joyce1-8/+11
Occasionally both MSI and INTx bits in the interrupt decode register are set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt message should be checked to ensure that the correct handler is used. If this check is not in place and the interrupt message type is MSI, the INTx handler will be used erroneously when both type bits are set. This will also be followed by a second read of the message FIFO, which can result in the function returning early and the interrupt decode register not being cleared if the FIFO is now empty. Signed-off-by: Russell Joyce <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-20iommu/vt-d: Cache PCI ATS state and Invalidate Queue DepthBjorn Helgaas1-10/+18
We check the ATS state (enabled/disabled) and fetch the PCI ATS Invalidate Queue Depth in performance-sensitive paths. It's easy to cache these, which removes dependencies on PCI. Remember the ATS enabled state. When enabling, read the queue depth once and cache it in the device_domain_info struct. This is similar to what amd_iommu.c does. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Joerg Roedel <[email protected]> Acked-by: Joerg Roedel <[email protected]>
2015-07-15PCI: pciehp: Simplify pcie_poll_cmd()Yijing Wang1-9/+5
Move first slot status read into while to simplify code. Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-15PCI: Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slotYijing Wang1-61/+61
Now in pci_hotplug_core.c, we randomly name a struct hotplug_slot and a struct pci_slot. It's easy to confuse them, so let us use "slot" for a struct hotplug_slot and "pci_slot" for a struct pci_slot. No functional change. Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-15PCI / ACPI: Fix pci_acpi_optimize_delay() commentSrinidhi Kasagar1-1/+1
The function takes ACPI handle, not the device itself. Fix the comment Signed-off-by: Srinidhi Kasagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Remove a broken link in quirks.cRami Rosen1-1/+0
Remove a broken link in drivers/pci/quirks.c. Signed-off-by: Rami Rosen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Remove useless redundant codeBjorn Helgaas1-2/+0
Remove redundant code from __pci_bus_find_cap_start(). No functional change. Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Simplify pci_find_(ext_)capability() return value checksWei Yang1-3/+3
The return value of the pci_find_(ext_)capability() is either zero or the position of a capability. It is never negative. This patch consolidates the form of check from (pos <= 0) to (!pos). Signed-off-by: Wei Yang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Move PCI_FIND_CAP_TTL to pci.h and use it in quirksWei Yang3-5/+6
Some quirks search for a HyperTransport capability and use a hard-coded TTL value of 48 to avoid an infinite loop. Move the definition of PCI_FIND_CAP_TTL to pci.h and use it instead of the hard-coded TTL values. [bhelgaas: changelog] Signed-off-by: Wei Yang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: xgene: Drop owner assignment from platform_driverKrzysztof Kozlowski1-1/+0
platform_driver_register() automatically supplies THIS_MODULE, so we don't need to set it in the platform_driver struct. Remove the xgene_msi_driver.owner assignment. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Add pcie_downstream_port() (true for Root and Switch Downstream Ports)Bjorn Helgaas1-10/+13
As used in the PCIe spec, "Downstream Port" includes both Root Ports and Switch Downstream Ports. We sometimes checked for PCI_EXP_TYPE_DOWNSTREAM when we should have checked for PCI_EXP_TYPE_ROOT_PORT or PCI_EXP_TYPE_DOWNSTREAM. For a Root Port without a slot, the effect of this was that using pcie_capability_read_word() to read PCI_EXP_SLTSTA returned zero instead of showing the Presence Detect State bit hardwired to one as the PCIe Spec, r3.0, sec 7.8, requires. (This read is completed in software because previous PCIe spec versions didn't require PCI_EXP_SLTSTA to exist at all.) Nothing in the kernel currently depends on this (pciehp only reads PCI_EXP_SLTSTA on ports with slots), so this is a cleanup and not a functional change. Add a pcie_downstream_port() helper function and use it. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
2015-07-14PCI: Fix pcie_port_device_resume() commentBjorn Helgaas1-1/+1
The function comment claimed this was pcie_port_device_suspend(), but it's really pcie_port_device_resume(). Perils of cut and paste. Use the correct function name in the comment. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
2015-07-14PCI: Shift PCI_CLASS_NOT_DEFINED consistently with other classesBjorn Helgaas2-6/+6
The PCI class in dev->class is a three-byte value comprising a base class, sub-class, and interface type. PCI_CLASS_NOT_DEFINED includes the base class and sub-class, but not the interface type, so it should be shifted to make space for the interface. It happens that PCI_CLASS_NOT_DEFINED is zero, so it doesn't matter in the end, but we should still use it consistently with other class definitions. Treat PCI_CLASS_NOT_DEFINED as a base class/sub-class value that should appear in bits 8-23 of dev->class. Signed-off-by: Bjorn Helgaas <[email protected]>
2015-07-14PCI: Revert aeb30016fec3 ("PCI: add Intel USB specific reset method")Bjorn Helgaas1-24/+0
Revert aeb30016fec3 ("PCI: add Intel USB specific reset method"). We checked for "dev->class == PCI_CLASS_SERIAL_USB", but dev->class contains the entire three-byte base class/sub-class/interface, while PCI_CLASS_SERIAL_USB is only the two-byte base class/sub-class. This error meant that we used the Intel device-specific reset on devices with class code 0x000c03 instead of those with class code 0x0c03xx. 0x000c03 is a reserved value in the 0x00 backwards compatibility base class and shouldn't match any devices, so I think reset_intel_generic_dev() always failed. I considered adding a shift, but I can't test it, so it's as likely to break something as to fix something. Signed-off-by: Bjorn Helgaas <[email protected]> CC: Yu Zhao <[email protected]> CC: Mathias Nyman <[email protected]>
2015-07-14PCI: Fix TI816X class code quirkBjorn Helgaas1-3/+6
In fixup_ti816x_class(), we assigned "class = PCI_CLASS_MULTIMEDIA_VIDEO". But PCI_CLASS_MULTIMEDIA_VIDEO is only the two-byte base class/sub-class and needs to be shifted to make space for the low-order interface byte. Shift PCI_CLASS_MULTIMEDIA_VIDEO to set the correct class code. Fixes: 63c4408074cb ("PCI: Add quirk for setting valid class for TI816X Endpoint") Signed-off-by: Bjorn Helgaas <[email protected]> CC: Hemant Pedanekar <[email protected]>
2015-07-14PCI: Fix generic NCR 53c810 class code quirkBjorn Helgaas2-18/+9
In the generic quirk fixup_rev1_53c810(), added by a5312e28c195 ("[PATCH] PCI: NCR 53c810 quirk"), we assigned "class = PCI_CLASS_STORAGE_SCSI". But PCI_CLASS_STORAGE_SCSI is only the two-byte base class/sub-class and needs to be shifted to make space for the low-order interface byte. Furthermore, we had a similar quirk, pci_fixup_ncr53c810(), for arch/x86, which assigned class correctly. The arch code is linked before the PCI core, so arch quirks run before generic quirks. Therefore, on x86, the x86 arch quirk ran first, and the generic quirk did nothing because it saw that dev->class was already set. But on other arches, the generic quirk set the wrong class code. Fix the generic quirk to set the correct class code and remove the now-unnecessary x86-specific quirk. Signed-off-by: Bjorn Helgaas <[email protected]> CC: Matthew Wilcox <[email protected]>
2015-07-14PCI: Use PCI_CLASS_SERIAL_USB instead of bare numberBjorn Helgaas1-4/+6
be6646bfbaec ("PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device") added a quirk to override the PCI class code of the AMD Nolan device. Use PCI_CLASS_SERIAL_USB instead of a bare number to improve greppability. Also add a log message about what we're doing. No functional change except the new message. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Huang Rui <[email protected]> CC: Jason Chang <[email protected]> CC: Felipe Balbi <[email protected]>
2015-07-14PCI: Add quirk for Intersil/Techwell TW686[4589] AV capture cardsKrzysztof =?utf-8?Q?Ha=C5=82asa?=1-0/+22
Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) class code. Fix it. Signed-off-by: Krzysztof Hałasa <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
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