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Reported-by: Maarten Lankhorst <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
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Pull slave-dmaengine updates from Vinod Koul:
"Once you have some time from extended weekend celebrations please
consider pulling the following to get:
- Various fixes and PCI driver for dw_dmac by Andy
- DT binding for imx-dma by Markus & imx-sdma by Shawn
- DT fixes for dmaengine by Lars
- jz4740 dmac driver by Lars
- and various fixes across the drivers"
What "extended weekend celebrations"? I'm in the merge window, who has
time for extended celebrations..
* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits)
DMA: shdma: add DT support
DMA: shdma: shdma_chan_filter() has to be in shdma-base.h
DMA: shdma: (cosmetic) don't re-calculate a pointer
dmaengine: at_hdmac: prepare clk before calling enable
dmaengine/trivial: at_hdmac: add curly brackets to if/else expressions
dmaengine: at_hdmac: remove unsuded atc_cleanup_descriptors()
dmaengine: at_hdmac: add FIFO configuration parameter to DMA DT binding
ARM: at91: dt: add header to define at_hdmac configuration
MIPS: jz4740: Correct clock gate bit for DMA controller
MIPS: jz4740: Remove custom DMA API
MIPS: jz4740: Register jz4740 DMA device
dma: Add a jz4740 dmaengine driver
MIPS: jz4740: Acquire and enable DMA controller clock
dma: mmp_tdma: disable irq when disabling dma channel
dmaengine: PL08x: Avoid collisions with get_signal() macro
dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically
dma: dw: add PCI part of the driver
dma: dw: split driver to library part and platform code
dma: move dw_dmac driver to an own directory
dw_dmac: don't check resource with devm_ioremap_resource
...
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git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux
Pull first stage of __cpuinit removal from Paul Gortmaker:
"The two commits here 1) dummy out all the __cpuinit macros so that we
no longer generate such sections, and then 2) remove all the section
processing that we used to do for those sections.
This makes all the __cpuinit and friends no-ops, so that we can remove
the use cases of it at our leisure. Expect stage 2, which does the
tree wide removal sweep at the end of the merge window."
* 'cpuinit-delete' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux:
modpost: remove all traces of cpuinit/cpuexit sections
init.h: remove __cpuinit sections from the kernel
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer core updates from Thomas Gleixner:
"The timer changes contain:
- posix timer code consolidation and fixes for odd corner cases
- sched_clock implementation moved from ARM to core code to avoid
duplication by other architectures
- alarm timer updates
- clocksource and clockevents unregistration facilities
- clocksource/events support for new hardware
- precise nanoseconds RTC readout (Xen feature)
- generic support for Xen suspend/resume oddities
- the usual lot of fixes and cleanups all over the place
The parts which touch other areas (ARM/XEN) have been coordinated with
the relevant maintainers. Though this results in an handful of
trivial to solve merge conflicts, which we preferred over nasty cross
tree merge dependencies.
The patches which have been committed in the last few days are bug
fixes plus the posix timer lot. The latter was in akpms queue and
next for quite some time; they just got forgotten and Frederic
collected them last minute."
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
hrtimer: Remove unused variable
hrtimers: Move SMP function call to thread context
clocksource: Reselect clocksource when watchdog validated high-res capability
posix-cpu-timers: don't account cpu timer after stopped thread runtime accounting
posix_timers: fix racy timer delta caching on task exit
posix-timers: correctly get dying task time sample in posix_cpu_timer_schedule()
selftests: add basic posix timers selftests
posix_cpu_timers: consolidate expired timers check
posix_cpu_timers: consolidate timer list cleanups
posix_cpu_timer: consolidate expiry time type
tick: Sanitize broadcast control logic
tick: Prevent uncontrolled switch to oneshot mode
tick: Make oneshot broadcast robust vs. CPU offlining
x86: xen: Sync the CMOS RTC as well as the Xen wallclock
x86: xen: Sync the wallclock when the system time is set
timekeeping: Indicate that clock was set in the pvclock gtod notifier
timekeeping: Pass flags instead of multiple bools to timekeeping_update()
xen: Remove clock_was_set() call in the resume path
hrtimers: Support resuming with two or more CPUs online (but stopped)
timer: Fix jiffies wrap behavior of round_jiffies_common()
...
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git://git.linaro.org/people/mszyprowski/linux-dma-mapping
Pull ARM DMA mapping updates from Marek Szyprowski:
"This contains important bugfixes and an update for IOMMU integration
support for ARM architecture"
* 'for-v3.11' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
ARM: dma: Drop __GFP_COMP for iommu dma memory allocations
ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in unmapping as clean
ARM: dma-mapping: NULLify dev->archdata.mapping pointer on detach
ARM: dma-mapping: convert DMA direction into IOMMU protection attributes
ARM: dma-mapping: Get pages if the cpu_addr is out of atomic_pool
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git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag
Pull Metag architecture changes from James Hogan:
- Infrastructure and DT files for TZ1090 SoC (pin control drivers
already merged via pinctrl tree).
- Panic on boot instead of just warning if cache aliasing possible.
- Various SMP/hotplug fixes.
- Various other randconfig/sparse fixes.
* tag 'metag-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: (24 commits)
metag: move EXPORT_SYMBOL(csum_partial) to metag_ksyms.c
metag: cpu hotplug: route_irq: preserve irq mask
metag: kick: add missing irq_enter/exit to kick_handler()
metag: smp: don't spin waiting for CPU to start
metag: smp: enable irqs after set_cpu_online
metag: use clear_tasks_mm_cpumask()
metag: tz1090: select and instantiate pinctrl-tz1090-pdc
metag: tz1090: select and instantiate pinctrl-tz1090
metag: don't check for cache aliasing on smp cpu boot
metag: panic if cache aliasing possible
metag: *.dts: include using preprocessor
metag: add <dt-bindings/> symlink
metag/.gitignore: Extend the *.dtb pattern to match the dtb.S files
metag/traps: include setup.h for the per_cpu_trap_init declaration
metag/traps: Mark die() as __noreturn to match the declaration.
metag/processor.h: Add missing cpuinfo_op declaration.
metag/setup: Restrict scope for the capabilities variable
metag/mm/cache: Restrict scope for metag_lnkget_probe
metag/asm/irq.h: Declare init_IRQ
metag/kernel/irq.c: Declare root_domain as static
...
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git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen
Pull Xen ARM update rom Stefano Stabellini:
"Just one commit this time: the implementation of the tmem hypercall
for arm and arm64"
* tag 'xenarm-for-3.11-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen:
xen/arm and xen/arm64: implement HYPERVISOR_tmem_op
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Pull irqdomain refactoring from Grant Likely:
"This is the long awaited simplification of irqdomain. It gets rid of
the different types of irq domains and instead both linear and tree
mappings can be supported in a single domain. Doing this removes a
lot of special case code and makes irq domains simpler to understand
overall"
* tag 'irqdomain-for-linus' of git://git.secretlab.ca/git/linux:
irq: fix checkpatch error
irqdomain: Include hwirq number in /proc/interrupts
irqdomain: make irq_linear_revmap() a fast path again
irqdomain: remove irq_domain_generate_simple()
irqdomain: Refactor irq_domain_associate_many()
irqdomain: Beef up debugfs output
irqdomain: Clean up aftermath of irq_domain refactoring
irqdomain: Eliminate revmap type
irqdomain: merge linear and tree reverse mappings.
irqdomain: Add a name field
irqdomain: Replace LEGACY mapping with LINEAR
irqdomain: Relax failure path on setting up mappings
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Signed-off-by: Al Viro <[email protected]>
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Sigh, should have noticed myself.
Reported-by: [email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
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Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to force a performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to limit the selected power levels via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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This allows you to force specific power levels within a power
state. Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:
auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level
Signed-off-by: Alex Deucher <[email protected]>
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r1xx asics have a slightly different surface register
setup compared to newer asics. There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.
With this fixed, the special rn50 handling can go.
Noticed-by: Mark Kettenis <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state. The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected. This change
switches to the "balanced" profile by default which ends up being
the internal performance profile. When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.
For most asics this changes nothing. For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.
Signed-off-by: Alex Deucher <[email protected]>
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Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.
This improves the out of the box performance with SI asics.
Signed-off-by: Alex Deucher <[email protected]>
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Pull crypto update from Herbert Xu:
- Do not idle omap device between crypto operations in one session.
- Added sha224/sha384 shims for SSSE3.
- More optimisations for camellia-aesni-avx2.
- Removed defunct blowfish/twofish AVX2 implementations.
- Added unaligned buffer self-tests.
- Added PCLMULQDQ optimisation for CRCT10DIF.
- Added support for Freescale's DCP co-processor
- Misc fixes.
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (44 commits)
crypto: testmgr - test hash implementations with unaligned buffers
crypto: testmgr - test AEADs with unaligned buffers
crypto: testmgr - test skciphers with unaligned buffers
crypto: testmgr - check that entries in alg_test_descs are in correct order
Revert "crypto: twofish - add AVX2/x86_64 assembler implementation of twofish cipher"
Revert "crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher"
crypto: camellia-aesni-avx2 - tune assembly code for more performance
hwrng: bcm2835 - fix MODULE_LICENSE tag
hwrng: nomadik - use clk_prepare_enable()
crypto: picoxcell - replace strict_strtoul() with kstrtoul()
crypto: dcp - Staticize local symbols
crypto: dcp - Use NULL instead of 0
crypto: dcp - Use devm_* APIs
crypto: dcp - Remove redundant platform_set_drvdata()
hwrng: use platform_{get,set}_drvdata()
crypto: omap-aes - Don't idle/start AES device between Encrypt operations
crypto: crct10dif - Use PTR_RET
crypto: ux500 - Cocci spatch "resource_size.spatch"
crypto: sha256_ssse3 - add sha224 support
crypto: sha512_ssse3 - add sha384 support
...
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Pull ubi fixes from Artem Bityutskiy:
"A couple of fixes and clean-ups, allow for assigning user-defined UBI
device numbers when attaching MTD devices by using the "mtd=" module
parameter"
* tag 'upstream-3.11-rc1' of git://git.infradead.org/linux-ubi:
UBI: support ubi_num on mtd.ubi command line
UBI: fastmap break out of used PEB search
UBI: document UBI_IOCVOLUP better in user header
UBI: do not abort init when ubi.mtd devices cannot be found
UBI: drop redundant "UBI error" string
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Pull ubifs fix from Artem Bityutskiy:
"Only a single patch which fixes a message"
* tag 'upstream-3.11-rc1' of git://git.infradead.org/linux-ubifs:
UBIFS: correct mount message
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smp_call_function_* must not be called from softirq context.
But clock_was_set() which calls on_each_cpu() is called from softirq
context to implement a delayed clock_was_set() for the timer interrupt
handler. Though that almost never gets invoked. A recent change in the
resume code uses the softirq based delayed clock_was_set to support
Xens resume mechanism.
linux-next contains a new warning which warns if smp_call_function_*
is called from softirq context which gets triggered by that Xen
change.
Fix this by moving the delayed clock_was_set() call to a work context.
Reported-and-tested-by: Artem Savkov <[email protected]>
Reported-by: Sasha Levin <[email protected]>
Cc: David Vrabel <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: H. Peter Anvin <[email protected]>,
Cc: Konrad Wilk <[email protected]>
Cc: John Stultz <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Al Viro <[email protected]>
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Signed-off-by: Al Viro <[email protected]>
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Up to commit 5d33b883a (clocksource: Always verify highres capability)
we had no sanity check when selecting a clocksource, which prevented
that a non highres capable clocksource is used when the system already
switched to highres/nohz mode.
The new sanity check works as Alex and Tim found out. It prevents the
TSC from being used. This happens because on x86 the boot process
looks like this:
tsc_start_freqency_validation(TSC);
clocksource_register(HPET);
clocksource_done_booting();
clocksource_select()
Selects HPET which is valid for high-res
switch_to_highres();
clocksource_register(TSC);
TSC is not selected, because it is not yet
flagged as VALID_HIGH_RES
clocksource_watchdog()
Validates TSC for highres, but that does not make TSC
the current clocksource.
Before the sanity check was added, we installed TSC unvalidated which
worked most of the time. If the TSC was really detected as unstable,
then the unstable logic removed it and installed HPET again.
The sanity check is correct and needed. So the watchdog needs to kick
a reselection of the clocksource, when it qualifies TSC as a valid
high res clocksource.
To solve this, we mark the clocksource which got the flag
CLOCK_SOURCE_VALID_FOR_HRES set by the watchdog with an new flag
CLOCK_SOURCE_RESELECT and trigger the watchdog thread. The watchdog
thread evaluates the flag and invokes clocksource_select() when set.
To avoid that the clocksource_done_booting() code, which is about to
install the first real clocksource anyway, needs to go through
clocksource_select and tick_oneshot_notify() pointlessly, split out
the clocksource_watchdog_kthread() list walk code and invoke the
select/notify only when called from clocksource_watchdog_kthread().
So clocksource_done_booting() can utilize the same splitout code
without the select/notify invocation and the clocksource_mutex
unlock/relock dance.
Reported-and-tested-by: Alex Shi <[email protected]>
Cc: Hans Peter Anvin <[email protected]>
Cc: Tim Chen <[email protected]>
Cc: Andi Kleen <[email protected]>
Tested-by: Peter Zijlstra <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Davidlohr Bueso <[email protected]>
Cc: John Stultz <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
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This patch adds Device Tree support to the shdma driver. No special DT
properties are used, only standard DMA DT bindings are implemented. Since
shdma controllers reside on SoCs, their configuration is SoC-specific and
shall be passed to the driver from the SoC platform data, using the
auxdata procedure.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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shdma_chan_filter() is a function, provided by the shdma-base.c module,
move its declaration to the appropriate header.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Use an existing pointer instead of retrieving it again.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
[[email protected]: remove return code checking in at_dma_resume_noirq()]
Signed-off-by: Nicolas Ferre <[email protected]>
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Correct coding style following the patch:
7c407d3e54dcc0c79119553c8d5ef176c1d5bc3a (DMA: AT91:
Get residual bytes in dma buffer).
Signed-off-by: Nicolas Ferre <[email protected]>
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Since patch 7c407d3e54dcc0c79119553c8d5ef176c1d5bc3a (DMA: AT91:
Get residual bytes in dma buffer), the function
atc_cleanup_descriptors() is not used anymore. We remove it to prevent
warnings.
Reported-by: Arnd Bergmann <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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For most devices the FIFO configuration is the same i.e. when half FIFO size is
available/filled, a source/destination request is serviced. But USART devices
have to do it when there is enough space/data available to perform a single
AHB access so the ASAP configuration.
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
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DMA-cell content is a concatenation of several values. In order to keep this
stuff human readable, macros are introduced.
The values for the FIFO configuration are not the same as the ones used in the
configuration register in order to keep backward compatibility. Most devices
use the half FIFO configuration but USART ones have to use the ASAP
configuration. This parameter was not initially planed to be into the at91 dma
dt binding. The third cell will be used to store this parameter, it will
become a concatenation of the FIFO configuration and of the peripheral ID. In
order to keep backward compatibility i.e. FIFO configuration is equal to 0, we
have to perform a translation since the value to put in the register to set
half FIFO is 1.
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
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Signed-off-by: Maarten ter Huurne <[email protected]>
Signed-off-by: Lars-Peter Clausen <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Now that all users of the custom jz4740 DMA API have been converted to use
the dmaengine API instead we can remove the custom API and move all the code
talking to the hardware to the dmaengine driver.
Signed-off-by: Lars-Peter Clausen <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Register a device for the newly added jz4740 dmaengine driver.
Signed-off-by: Lars-Peter Clausen <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
[manually edited to align struct assignment]
Signed-off-by: Vinod Koul <[email protected]>
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This patch adds dmaengine support for the JZ4740 DMA controller. For now the
driver will be a wrapper around the custom JZ4740 DMA API. Once all users of the
custom JZ4740 DMA API have been converted to the dmaengine API the custom API
will be removed and direct hardware access will be added to the dmaengine
driver.
Signed-off-by: Lars-Peter Clausen <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Previously, it was assumed that the DMA controller clock is not gated
when the kernel starts running. While that is the power-on state, it is
safer to not rely on that.
Signed-off-by: Maarten ter Huurne <[email protected]>
Signed-off-by: Lars-Peter Clausen <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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mask dma irq when disabling dma channel, so that interrupt status
will not be set and interrupt won't come again.
Signed-off-by: Qiao Zhou <[email protected]>
Acked-by: Zhangfei Gao <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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As pointed out by Arnd Bergmann there is a get_signal macro definied in
linux/signal.h which can conflict with the platform data callback
function of the same name leading to confusing errors from the compiler
(especially if signal.h manages to get pulled into the driver itself due
to header dependencies). Avoid such errors by renaming get_signal and
put_signal in the platform data to get_xfer_signal and put_xfer_signal.
Signed-off-by: Mark Brown <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Signed-off-by: Vinod Koul <[email protected]>
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This is the PCI part of the DesignWare DMAC driver. The controller is usually
used in the Intel hardware such as Intel Medfield.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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To simplify the driver development let's split driver to library and platform
code parts. It helps us to add PCI driver in future.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
[Fixed compile error and few checkpatch issues]
Signed-off-by: Vinod Koul <[email protected]>
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The dw_dmac driver is going to be split into multiple files. To make this more
convenient move it to an own directory.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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The microcode bus address (pl330_dmac.mcode_bus) is currently a u32,
which fails to compile when building on a system with 64-bit bus
addresses.
This patch uses dma_addr_t to represent the address instead.
Cc: Jassi Brar <[email protected]>
Cc: Vinod Koul <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Acked-by: Jassi Brar <[email protected]>
Acked-by: Grant Likely <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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The PL330 driver probes the peripheral and primecell IDs of the device to
make sure that it is indeed an AMBA PL330. However, it does this by
making byte accesses to a device mapping of the word-aligned ID
registers, which is either UNPREDICTABLE or generates an alignment fault
(depending on the presence of the virtualisation extensions).
Rather than fix this code, we can actually rip most of it out and let
the AMBA bus driver correctly do the probing for us.
Cc: Jassi Brar <[email protected]>
Cc: Vinod Koul <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Acked-by: Jassi Brar <[email protected]>
Acked-by: Grant Likely <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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Update imx-sdma driver to adopt generic DMA device tree bindings. It
calls of_dma_controller_register() with imx-sdma specific of_dma_xlate
to get the generic DMA device tree helper support. The #dma-cells for
imx-sdma must be 3, which includes request ID, peripheral type and
priority.
The existing way of requesting channel, clients directly call
dma_request_channel(), still work there, and will be removed after
all imx-sdma clients get converted to generic DMA device tree helper.
Signed-off-by: Shawn Guo <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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read SIRFSOC_DMA_CH_ADDR register to get current dma transfer position, then
update dma residue so that things like ALSA drivers work as ALSA drivers need
the right residue value.
Signed-off-by: Rongjun Ying <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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