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2023-07-27drm/amd/pm: Clean up errors in navi10_ppt.cRan Sun1-12/+13
Fix the following errors reported by checkpatch: ERROR: open brace '{' following function definitions go on the next line ERROR: space required before the open parenthesis '(' ERROR: space required after that ',' (ctx:VxV) ERROR: spaces required around that '=' (ctx:VxW) Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-27drm/amd/pm: add missing spaces before '('Ran Sun1-3/+3
ERROR: space required before the open parenthesis '(' Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-27drm/radeon: Move assignment outside if conditionRan Sun1-2/+4
Fixes the following checkpatch errors: ERROR: do not use assignment in if condition Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-27drm/radeon: that open brace { should be on the previous lineRan Sun1-24/+12
ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-27drm/radeon: that open brace { should be on the previous lineRan Sun1-2/+1
ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-27drm/radeon: add missing spaces after ',' and else should follow close brace '}'Ran Sun1-3/+2
ERROR: else should follow close brace '}' ERROR: space required after that ',' (ctx:VxV) Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Restore HQD persistent state registerLijo Lazar1-1/+2
On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: add missing spaces before ';'Ran Sun1-2/+2
ERROR: space required after that ';' (ctx:BxV) Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon/si_dpm: open brace '{' following struct go on the same lineRan Sun1-34/+17
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metricsWenyou Yang3-9/+172
To acquire the voltage and current info from gpu_metrics interface, but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible, add new gpu_metrics_v2_4 structure. Reviewed-by: Mario Limonciello <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Wenyou Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: load sdma ucode in the guest machineYuanShang3-8/+14
[why] User mode driver need to check the sdma ucode version to see whether the sdma engine supports a new type of PM4 packet. In SRIOV, sdma is loaded by the host. And, there is no way to check the sdma ucode version of CHIP_NAVI12 and CHIP_SIENNA_CICHLID of the host in the guest machine. [how] Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID in the guest machine. Signed-off-by: YuanShang <[email protected]> Reviewed-By: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Use seq_puts() instead of seq_printf()Srinivasan Shanmugam1-11/+11
For a constant format without additional arguments, use seq_puts() instead of seq_printf(). Also, it fixes the following warning. WARNING: Prefer seq_puts to seq_printf And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Block comments should align the * on each line Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl'Srinivasan Shanmugam1-6/+8
Fixes the following: WARNING: min() should probably be min_t(size_t, size, sizeof(ip)) + ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Missing a blank line after declarations Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Remove else after return in 'is_fru_eeprom_supported'Srinivasan Shanmugam1-4/+5
Expressions under 'else' branch under case 'CHIP_SIENNA_CICHLID' in function 'is_fru_eeprom_supported' are executed whenever the expression in 'if' is False. Otherwise, return from case occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return false; + } else { Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Remove else after return in 'dm_vblank_get_counter' & ↵Srinivasan Shanmugam1-14/+17
'amdgpu_dm_backlight_get_level' Expressions under 'else' branch in function 'dm_vblank_get_counter' & 'amdgpu_dm_backlight_get_level' are executed whenever the expression in 'if' is False. Otherwise, return from function occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return 0; + else { WARNING: else is not generally useful after a break or return + return convert_brightness_to_user(&caps, avg); + } else { Cc: Rodrigo Siqueira <[email protected]> Cc: Aurabindo Pillai <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Add -ENOMEM error handling when there is no memorySrinivasan Shanmugam4-9/+17
Return -ENOMEM, when there is no sufficient dynamically allocated memory Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Check APU flag to disable RASStanley.Yang1-1/+2
Only disable RAS by default for aqua vanjaram on APU platform. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: fix the indexing issue during rlcg access ctrl initShiwu Zhang1-4/+3
In case that the GET_INST() is used for looping, only loops for the times of actual num of xcc, otherwise GET_INST() will return the invalid index, a.k.a -1 And also remove the redundant mask checking in case of GET_INST() Signed-off-by: Shiwu Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: add VISIBLE info in amdgpu_bo_print_infoPierre-Eric Pelloux-Prayer1-13/+21
This allows tools to distinguish between VRAM and visible VRAM. Use the opportunity to fix locking before accessing bo. v2: squash in unused variable fix Reviewed-by: Christian König <[email protected]> Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdkfd: avoid svm dump when dynamic debug disabledAlex Sierra1-1/+3
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists from svm_range_debug_dump when dynamic debug is disabled. Otherwise, it could drop performance, specially with big number of SVM ranges. Make sure both svm_range_set_attr and svm_range_debug_dump functions are dynamically enabled to print svm_range_debug_dump debug traces. Signed-off-by: Alex Sierra <[email protected]> Tested-by: Alex Sierra <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: ERROR: "foo * bar" should be "foo *bar"Ran Sun1-2/+2
Fix two occurrences of the checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: open brace '{' following struct go on the same lineRan Sun1-2/+1
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/pm: open brace '{' following struct go on the same lineRan Sun1-14/+7
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd: open brace '{' following struct go on the same lineRan Sun1-4/+2
Fix the checkpatch error as open brace '{' following struct should go on the same line. Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Unlock on error path in ↵Dan Carpenter1-1/+1
dm_handle_mst_sideband_msg_ready_event() This error path needs to unlock the "aconnector->handle_mst_msg_ready" mutex before returning. Fixes: bb4fa525f327 ("drm/amd/display: Add polling method to handle MST reply packet") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: 3.2.244Aric Cyr1-1/+1
This version brings along following fixes: - Fix underflow issue on 175hz timing - Add interface to modify DMUB panel power options - Remove check for default eDP panel_mode - Add new sequence for 4-lane HBR3 on vendor specific retimers - Update DPG test pattern programming - Correct unit conversion for vstartup - Exit idle optimizations before attempt to access PHY - Refactor recout calculation with a more generic formula - Read down-spread percentage from lut to adjust dprefclk. - Don't apply FIFO resync W/A if rdivider = 0 - Prevent invalid pipe connections - Rearrange dmub_cmd defs order - Add VESA SCR case for default aux backlight - Guard DCN31 PHYD32CLK logic against chip family - Correct grammar mistakes Acked-by: Alex Hung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Fix underflow issue on 175hz timingLeo Ma1-1/+6
[Why] Screen underflows happen on 175hz timing for 3 plane overlay case. [How] Based on dst y prefetch value clamp to equ or oto for bandwidth calculation. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Leo Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Add interface to modify DMUB panel power optionsPaul Hsieh2-0/+15
[Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Rearrange dmub_cmd defs orderAnthony Koo1-28/+26
- Rearranged defs order Acked-by: Alex Hung <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Remove check for default eDP panel_modeTaimur Hassan1-25/+24
[Why] DPCD read is skipped first time after driver initialization. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Fix style issues in amdgpu_gem.cSrinivasan Shanmugam1-19/+19
Fixes the following to align to linux coding style: WARNING: braces {} are not necessary for any arm of this statement WARNING: Missing a blank line after declarations ERROR: space prohibited before that close parenthesis ')' WARNING: unnecessary whitespace before a quoted newline WARNING: %LX is non-standard C, use %llX Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Add new sequence for 4-lane HBR3 on vendor specific retimersOvidiu Bunea1-1/+66
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by: Michael Strauss <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Update DPG test pattern programmingWenjing Liu2-74/+78
[Why] Last ODM slice could be slightly larger than other slice because it can be including the residual. [How] Update DPG pattern programming sequence to use a different width for last odm slice. Reviewed-by: Chris Park <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Correct unit conversion for vstartupReza Amini1-1/+24
[Why] vstartup is calculated to be a large number. It works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [How] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Reza Amini <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Exit idle optimizations before attempt to access PHYLeo Chen1-0/+3
[Why & How] DMUB may hang when powering down pixel clocks due to no dprefclk. It is fixed by exiting idle optimization before the attempt to access PHY. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Leo Chen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Refactor recout calculation with a more generic formulaWenjing Liu4-168/+404
[Why] Current recout calculation has a few assumptions and implementation for MPO + ODM combine calculation is very specific. The equation has too many cases without enough comments to document the detail. [How] The change remove the following assumptions: 1. When MPO is enabled, we only allow ODM Combine 2:1 2. ODM Combine always has even segment width. 3. Secondary MPO plane's pipe_ctx copies pre_odm_pipe from its top pipe. The change applies a generic formula with more details in comment to document this solution so it is eaiser to learn and debug later. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.Martin Tsai2-2/+38
[Why] Panels show corruption with high refresh rate timings when ss is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Martin Tsai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Don't apply FIFO resync W/A if rdivider = 0Alvin Lee1-1/+4
[Description] It is not valid to set the WDIVIDER value to 0, so do not re-write to DISPCLK_WDIVIDER if the current value is 0 (i.e., it is at it's initial value and we have not made any requests to change DISPCLK yet). Reviewed-by: Saaem Rizvi <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Prevent invalid pipe connectionsEthan Bitnun1-3/+34
[Description] - Prevent ODM pipe connections between pipes that are not part of the same plane when adding a plane to context - Re-attach child pipes of ODM slice about to be disconnected to prevent any lost pipes with invalid tops/bottoms - We cannot split if head_pipe is not in ODM. Preventing this avoids creating an invalid context with an invalid pipe. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Ethan Bitnun <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Update ring scheduler info as neededLijo Lazar1-1/+1
Not all rings have scheduler associated. Only update scheduler data for rings with scheduler. It could result in out of bound access as total rings are more than those associated with particular IPs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Enabling FW workaround through shared memory for VCN4_0_2sguttula2-0/+15
This patch will enable VCN FW workaround using DRM KEY INJECT WORKAROUND method, which is helping in fixing the secure playback. Signed-off-by: sguttula <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Add VESA SCR case for default aux backlightIswara Nagulendran1-4/+14
[How & Why] When determining default aux backlight level, read from DPCD address 0x734 for VESA SCR on OLED. Reviewed-by: Felipe Clark <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Iswara Nagulendran <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: Prefer dev_* variant over printkSrinivasan Shanmugam1-4/+8
Changed from pr_err/info to dev_* variants so that we get better debug info when there are multiple GPUs in the system. Fixes: 09edeb4c1680 ("drm/radeon: Prefer pr_err/_info over printk") Suggested-by: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: Fix style issues in radeon _encoders.c & _gart.cSrinivasan Shanmugam2-29/+30
Conform to Linux kernel coding style. Fixes the following & other checks in radeon_encoders.c & radeon_gart.c: WARNING: Missing a blank line after declarations WARNING: Block comments use * on subsequent lines WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/amdgpu: Fix warnings in amdgpu/amdgpu_display.cSrinivasan Shanmugam1-17/+25
Fixes the below checkpatch.pl warnings: WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line WARNING: suspect code indent for conditional statements (8, 12) WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: Avoid externs & do not initialize globals to 0 in radeon_drv.cSrinivasan Shanmugam2-37/+27
Fixes the following: - WARNING: externs should be avoided in .c files - ERROR: do not initialise globals to 0 - WARNING: Missing a blank line after declarations Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Guard DCN31 PHYD32CLK logic against chip familyGeorge Shen1-1/+2
[Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Correct grammar mistakesReza Amini1-9/+11
[Why] There are grammer mistakes in comments [How] Correct grammar mistakes Reviewed-by: Anthony Koo <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Reza Amini <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Return -ENOMEM when there is no memory in 'amdgpu_gfx_mqd_sw_init'Srinivasan Shanmugam1-3/+8
Return -ENOMEM, when there is no sufficient dynamically allocated memory to create MQD backup for ring Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Fix do not add new typedefs in amdgpu_fw_attestation.cSrinivasan Shanmugam1-20/+18
Fixes the following to align to coding style: WARNING: do not add new typedefs +typedef struct FW_ATT_DB_HEADER WARNING: do not add new typedefs +typedef struct FW_ATT_RECORD WARNING: Symbolic permissions 'S_IRUSR' are not preferred. Consider using octal permissions '0400'. + S_IRUSR, ERROR: "(foo*)" should be "(foo *)" WARNING: please, no space before tabs Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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