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2018-12-03drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan1-1/+41
This patch configures DSI video mode dual link by programming DSS_CTL registers. v2: Use new bitfield definitions from Anusha's patch Correct register to be programmed and use max depth buffer value (James) v3 by Jani: - checkpatch fixes Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/d8962f4e1beffc2099b8bef8cb5a5191aa1d9efd.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan1-0/+31
This patch implements compute config for Gen11 DSI encoder which is required at the time of modeset. For DSI 8X clock is AFE clock which is 5 times port clock. v2 by Jani: - drop the enable nop hook - fixed_mode is always true - HAS_GMCH_DISPLAY() is always false v3 by Jani: - set encoder->compute_config dropped during rebase v4 by Jani: - squash Vandita's port clock patch - remove todo comment Co-developed-by: Vandita Kulkarni <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/a21574173caa5e2932d9e3c537b0931097ab5ac2.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan1-0/+59
This patch read out the current hw state for DSI and return true if encoder is active. v2 by Jani: - Squash connector get hw state hook here - Squash encode get hw state fix here v3 by Jani: - Add encoder->get_power_domains() (Imre) v4 by Jani: - Make encoder->get_power_domains() sensible... (Imre) v5 by Jani: - Power domains are bit positions, not bits (Stan, Imre) Cc: Imre Deak <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ec6da32a55b9fb045527f14e41ed3dce86d46a97.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add get config functionality for DSIVandita Kulkarni3-2/+19
This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Use the same method to get port clock like other DDI encoders. Used during the atomic modeset. v2 by Jani: - Squash Madhav's and Vandita's get config bits together - Move cnl_calc_wrpll_link() to intel_drv.h - Drop extra temp variables - Use enc_to_intel_dsi() instead of open coding Co-developed-by: Madhav Chauhan <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f21fa4258068d04582f2bf30735e5536a8043bdf.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan1-0/+147
Allocate DSI host structure for each DSI port available on gen11 and register them with DSI fwk of DRM. Some of the DSI host operations are also registered as part of this. Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI exported functions. A wrapper function is also added as "DSI host transfer" for sending DSI data/cmd. Add DSI packet payload to command payload queue using credit based mechanism for *long* packets. v2 by Jani: - indentation - Use the new credit available helper - Use int for free_credits - Add intel_dsi local variable for better code flow - Use the new credit available helper - Use int for free_credits, i, and j v3 by Jani: - Squash DSI host allocation and transfer patches together Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/af4f168ed8737d44687d8b6f21ecaa7e805eb695.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Fill DSI ports infoMadhav Chauhan1-0/+8
This patch fills backlight, CABC and general port info for Gen11 DSI. Signed-off-by: Madhav Chauhan <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/48c9f867d61a60dc7c2ce744ac2325655652c55f.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Use the same pll functions for dsiVandita Kulkarni1-5/+11
The same pll manager functions can be used to enable dpll for mipi. Hence enabling the IO power and esc clock as part of pre pll enable call. v2 by Jani: - fix function parameter indent (Madhav) Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/07db5b1ce59c00295fad8a8e81908d59d8d76915.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Allocate DSI encoder/connectorMadhav Chauhan1-8/+109
This patch allocates memory for DSI encoder and connector which will be used for various DSI encoder/connector operations and attaching the same to DRM subsystem. This patch also extracts DSI modes info from VBT and save the desired mode info to connector. v2 by Jani: - Drop GEN11 prefix from encoder name - Drop extra parenthesis - Drop extra local variable - Squash encoder power domain here v3 by Jani: - Squash connector and connector helper functions here - Move intel_dsi_vbt_init call here Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/0197023b92ffa2d59064e30fd4ca22b6a4cff16c.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan2-2/+5
This patch calculates various DPLL dividers and parameters for DSI encoder and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock. v2: Extend haswell_crtc_compute_clock() for Gen11 DSI v3: Rebase v4: use port clock instead of bitrate. v5: Reabse and remove divide by 5 v6 by Jani: - Fix indent (Madhav) - Fix dpll state calc for EDP and DP MST Co-developed-by: Vandita Kulkarni <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Sanitize DDI port clock gating for DSI portsImre Deak2-17/+53
The requirement for the DDI port clock gating for a port in DSI mode is the opposite wrt. the case when the port is in DDI mode: the clock should be gated when the port is active and ungated when the port is inactive. Note that we cannot simply keep the DDI clock gated when the port will be only used in DSI mode: it must be gated/ungated at a specific spot in the DSI enable/disable sequence. Ensure the above for all ports of a DSI encoder, also adding a sanity check that we haven't registered another encoder using the same port (VBT should never allow this to happen). Cc: Madhav Chauhan <[email protected]> Cc: Vandita Kulkarni <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Clint Taylor <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Imre Deak <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ceb14d5a68e8e23988d923d4290a4f981789e616.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula3-62/+34
Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions. Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion. Cc: Madhav Chauhan <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f8e2982ceea4c05dc254a0c15e2b3be1d5f271d3.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/selftests: Terminate hangcheck sanitycheck forciblyChris Wilson1-3/+9
If all else fails and we are stuck eternally waiting for the undying request, abandon all hope. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/ringbuffer: Clear semaphore sync registers on ring initChris Wilson1-0/+7
Ensure that the sync registers are cleared every time we restart the ring to avoid stale values from creeping in from random neutrinos. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108888 Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/meson: Fix an Alpha Primary Plane bug on Meson GXL/GXM SoCsNeil Armstrong3-0/+40
On the Amlogic GXL & GXM SoCs, a bug occurs on the primary plane when alpha is used where the alpha is not aligned with the pixel content. The workaround Amlogic implemented is to reset the OSD1 plane hardware block each time the plane is (re)enabled, solving the issue. In the reset, we still need to save the content of 2 registers which depends on the status of the plane, in addition to reload the scaler conversion matrix at the same time. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Maxime Jourdan <[email protected]> Reviewed-by: Maxime Jourdan <[email protected]> [narmstrong: fixed typo in commit log] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/v3d: Fix prime imports of buffers from other drivers.Eric Anholt1-0/+1
v3d_bo_get_pages() checks this to decide to map the imported buffer instead of the backing shmem file. The caller was about to set this value anyway, and there's no error path in between. Ideally we wouldn't even allocate the shmem file for our imports, but that's a more invasive fix. Signed-off-by: Eric Anholt <[email protected]> Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+") Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Daniel Vetter <[email protected]> Reviewed-by: Dave Emett <[email protected]>
2018-11-30drm/v3d: Drop the "dev" argument to lock/unlock of BO reservations.Eric Anholt1-11/+9
They were unused, as Dave Emett noticed in TFU review. Signed-off-by: Eric Anholt <[email protected]> Cc: Dave Emett <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Daniel Vetter <[email protected]>
2018-11-30drm/v3d: Add support for submitting jobs to the TFU.Eric Anholt8-51/+427
The TFU can copy from raster, UIF, and SAND input images to UIF output images, with optional mipmap generation. This will certainly be useful for media EGL image input, but is also useful immediately for mipmap generation without bogging the V3D core down. For now we only run the queue 1 job deep, and don't have any hang recovery (though I don't think we should need it, with TFU). Queuing multiple jobs in the HW will require synchronizing the YUV coefficient regs updates since they don't get FIFOed with the job. v2: Change the ioctl to IOW instead of IOWR, always set COEF0, explain why TFU is AUTH, clarify the syncing docs, drop the unused TFU interrupt regs (you're expected to use the hub's), don't take &bo->base for NULL bos. v3: Fix a little whitespace alignment (noticed by checkpatch), rebase on drm_sched_job_cleanup() changes. Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Dave Emett <[email protected]> (v2) Link: https://patchwork.freedesktop.org/patch/264607/
2018-11-30drm/i915/psr: Get pipe id following atomic guidelinesJosé Roberto de Souza2-15/+5
As stated in struct drm_encoder, crtc field should only be used by non-atomic drivers. So here caching the pipe id in intel_psr_enable() what is way more simple and efficient than at every call to intel_psr_flush()/invalidate() get the drm.mode_config.connection_mutex lock to safely be able to get the pipe id by reading drm_connector_state.crtc. This should fix the null pointer dereference crash below as the previous way to get the pipe id was prone to race conditions. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959 Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/amdgpu: wait for IB test on first device openChristian König1-3/+3
Instead of delaying that to the first query. Otherwise we could try to use the SDMA for VM updates before the IB tests are done. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entitiesAlex Deucher1-0/+1
Looks like it was missed when setting support was added. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm/amdgpu: don't expose fan attributes on APUsAlex Deucher1-0/+13
They don't have a fan controller. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm/amdgpu: Fix num_doorbell calculation issueOak Zeng1-2/+5
When paging queue is enabled, it use the second page of doorbell. The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the kernel doorbells are in the first page. So with paging queue enabled, the total kernel doorbell range should be original num_doorbell plus one page (0x400 in dword), not *2. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm/ttm: fix LRU handling in ttm_buffer_object_transferChristian König1-1/+3
We need to set the NO_EVICT flag on the ghost object or otherwise we are adding it to the LRU. When it is added to the LRU we can run into a race between destroying and evicting it again. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm/amd/display: Fix NULL ptr deref for commit_planes_to_streamNicholas Kazlauskas1-1/+1
[Why] With scaling, underscan and abm changes we can end up calling commit_planes_to_stream in commit_tail. This call uses dm_state->context which can be NULL if the commit was a fast update. [How] Use dc_state instead since that can't be NULL unless the system ran out of memory. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108912 Fixes: e64abff2f133 ("drm/amd/display: Use private obj helpers for dm_atomic_state") Signed-off-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-30drm: Fix up drm_atomic_state_helper.[hc] extractionDaniel Vetter4-164/+164
I've misplaced two functions by accident: - drm_atomic_helper_duplicate_state is really part of the resume/suspend/shutdown device-wide helpers. - drm_atomic_helper_legacy_gamma_set is part of the legacy ioctl compat helpers. Move them both back. Fixes: 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[hc]") Cc: Ville Syrjälä <[email protected]> Reviewed-by: Sean Paul <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/i915/selftests: Fix live_workarounds to actually do resetsTvrtko Ursulin1-12/+53
The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy request. Thanks to Chris for helping with reset magic. v2: * Grab RPM ref over reset. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/i915/selftests: Extract spinner codeTvrtko Ursulin4-250/+290
Pull out spinner code to a standalone file to enable it to be shortly used by other and new test cases. Plain code movement - no functional changes. Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm: Fix compiler warning in drm_atomic_helper.cSean Paul1-0/+3
Kbuild was complaining about: >> drivers/gpu/drm/drm_atomic_helper.c:3169:27: warning: 'state' may be used uninitialized in this function [-Wmaybe-uninitialized] Now state can't actually be used uninitialized, but we'll assign a value anyways so it stops bellyaching. Kbuild config: link: https://lists.01.org/pipermail/kbuild-all/2018-November/055374.html tree: git://anongit.freedesktop.org/drm/drm-misc for-linux-next head: b7ea04d299c78b6cf96ab281a1683ff62a74f969 commit: b7ea04d299c78b6cf96ab281a1683ff62a74f969 [4/4] drm: Add DRM_MODESET_LOCK_BEGIN/END helpers config: x86_64-randconfig-x017-201847 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: git checkout b7ea04d299c78b6cf96ab281a1683ff62a74f969 # save the attached .config to linux build tree make ARCH=x86_64 Fixes: b7ea04d299c7 ("drm: Add DRM_MODESET_LOCK_BEGIN/END helpers") Cc: Daniel Vetter <[email protected]> Cc: Sean Paul <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Sean Paul <[email protected]> Cc: David Airlie <[email protected]> Cc: [email protected] Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Sean Paul <[email protected]> [seanpaul added extra details on airlied's suggestion] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30Merge drm/drm-next into drm-misc-nextSean Paul1-3/+0
Need to pick up the following patch to fix htmldocs build 167bfe534dc2 ("Documentation: drm: Remove dangling pointer from drm-mm.rst") Signed-off-by: Sean Paul <[email protected]>
2018-11-30drm/i915/icl: Remove Wa_1604302699Tvrtko Ursulin1-5/+0
It seems that the documentation does not reference this any more, plus, bit 28 does not stick when written to the register. Therefore I can only assume this is something which was documented in the past but got removed from the hardware in the meantime. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/i915: Remove whitelist application from ringbuffer backendTvrtko Ursulin1-2/+0
There is no white-listing before Gen8 and after the removal ringbuffer support for these platforms we can remove the call to this no-op. Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/i915: Fixup stub definitions for intel_opregion_suspend|resumeChris Wilson1-3/+3
248 "multiple definition of ...". E.g.: LD [M] drivers/gpu/drm/i915/i915.o ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume': i915_irq.c:(.text+0x58f0): multiple definition of `intel_opregion_resume'; drivers/gpu/drm/i915/i915_drv.o:i915_drv.c:(.text+0x2d40): first defined here Reported-by: Randy Dunlap <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Fixes: a950adc6c343 ("drm/i915: Stop calling intel_opregion unregister/register in suspend/resume") Signed-off-by: Chris Wilson <[email protected]> Acked-by: Randy Dunlap <[email protected]> # build tested Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Allow YUV formats on cursor planesBoris Brezillon1-12/+4
Now that scaling is allowed on cursor planes, we can also allow YUV formats. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Allow scaling on cursor planeBoris Brezillon1-17/+2
Now that async update has been reworked to allow scaled planes to be updated asynchronously when the scaling params do not change, we can remove the NO_SCALING constraint on cursor planes. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Rework the async update logicBoris Brezillon1-21/+66
vc4_plane_atomic_async_check() was only based on the state->{crtc,src}_{w,h} which was fine since scaling was not allowed on the cursor plane. We are about to change that to properly support underscan, and, in order to make the async check more reliable, we call vc4_plane_mode_set() from there and check that only the pos0, pos2 and ptr0 entries in the dlist have changed. In vc4_plane_atomic_async_update(), we no longer call vc4_plane_atomic_check() since vc4_plane_mode_set() has already been called in vc4_plane_atomic_async_check(), and we don't need to allocate a new LBM region (we reuse the one from the current state). Note that we now have to manually update each field of the current plane state since it's no longer updated in place (not sure we have to sync all of them, but it's harmless if we do). We also drop the vc4_plane_async_set_fb() call (ptr0 dlist entry has been properly updated in vc4_plane_mode_set()) Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Don't check plane state more than onceBoris Brezillon2-0/+16
We are about to use vc4_plane_mode_set() in the async check path, but async check can decide that async update is not possible and force the driver to fallback to a sync update. All the checks that have been done on the plane state during async check stay valid, and checking it again is not necessary. Add a ->checked field to vc4_plane_state, and use it to track the status of the state (checked or not). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Move LBM creation out of vc4_plane_mode_set()Boris Brezillon2-28/+54
We are about to use vc4_plane_mode_set() in the async check path, and async updates require that LBM size stay the same since they reuse the LBM from the previous state. So we definitely don't want to allocate a new LBM region that we know for sure will be free right away. Move the LBM allocation out of vc4_plane_mode_set() and call the new function (vc4_plane_update_lbm()) from vc4_plane_atomic_check(). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30drm/vc4: Make vc4_lbm_size() return 0 when vertical scaling is disabledBoris Brezillon1-3/+6
LBM is not needed when vertical scaling is disabled. Return 0 in this case to avoid allocating LBM memory that will anyway be unused. While at it, drop the test on ->is_unity which is now redundant. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-30Documentation: drm: Remove dangling pointer from drm-mm.rstSean Paul1-3/+0
Fixes htmldocs build error: Error: Cannot open file ../drivers/gpu/drm/drm_global.c Fixes: 2bb42410b1bd ("drm: Remove drm_global.{c,h} v2") Cc: Thomas Zimmermann <[email protected]> Cc: Christian König <[email protected]> Cc: Junwei Zhang <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Sean Paul <[email protected]> Cc: David Airlie <[email protected]> Cc: Christian Koenig <[email protected]> Cc: Huang Rui <[email protected]> Cc: [email protected] Signed-off-by: Sean Paul <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/fec: Disable FEC state.Anusha Srivatsa1-4/+24
Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled. v2: - rebased. - Add additional check for compression state. (Gaurav) v3: rebased. v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi) v5: Remove unnecessary checks (Ville) v6: Resolve warnings. Add crtc_state as an argument to intel_disable_ddi_buf(). (Manasi) Cc: [email protected] Cc: Gaurav K Singh <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa2-0/+25
If FEC is supported, the corresponding DP_TP_CTL register bits have to be configured. The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and wait till FEC_STATUS in DP_TP_CTL[28] is 1. Also add the warn message to make sure that the control register is already active while enabling FEC. v2: - Change commit message. Configure fec state after link training (Manasi, Gaurav) - Remove redundent checks (Manasi) - Remove the registers that get added automagically (Anusha) v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav) v4: rebased. v5: - Move the code to the proper spot, according to spec.(Ville) - Use fec state as a check too. v6: Pass intel_encoder, instead of intel_dp. (Ville) v7: Remove unwanted comments (Manasi) Cc: [email protected] Cc: Gaurav K Singh <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/fec: Set FEC_READY in FEC_CONFIGURATIONAnusha Srivatsa1-0/+11
If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd register: FEC_CONFIGURATION. This has to happen before link training. v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready - change commit message. (Gaurav) v3: rebased. (r-b Manasi) v4: Use fec crtc state, before setting FEC_READY bit. (Anusha) v5: Move to intel_ddi.c - Make the function static (Anusha) v6: Dont pass state as a separate argument (Ville) v7: (From Manasi) * Correct the debug print (Ville) Cc: [email protected] Cc: Gaurav K Singh <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29i915/dp/fec: Add fec_enable to the crtc state.Anusha Srivatsa2-5/+26
For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error correction on other scenarios too if needed. v2: - Control compression_enable with the fec_enable parameter in crtc state and with intel_dp_supports_fec() (Ville) - intel_dp_can_fec()/intel_dp_supports_fec()(manasi) v3: Check for FEC support along with setting crtc state. v4: add checks to intel_dp_source_supports_dsc.(manasi) - Move intel_dp_supports_fec() closer to intel_dp_supports_dsc() (Anusha) v5: Move fec check to intel_dp_supports_dsc(Ville) v6: Remove warning. rebase. v7: change crtc state to include DP sink and fec capability of source.(Manasi) v8: Set fec_enable in crtc in intel_dp_compute_config(). v9 (From Manasi): * Combine the !edp and !fec_support check * Derive dev_priv from intel_dp directly v10 (From Manasi): * Rebase Suggested-by: Ville Syrjala <[email protected]> Cc: [email protected] Cc: Ville Syrjala <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dsc: Enable and disable appropriate power wells for VDSCManasi Navare3-0/+34
A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during VDSC enabling/disabling. v4: * Get VDSC power domain only if compression en is set in crtc_state (Ville, Imre) v3: * Call it intel_dsc_power_domain, add to intel_ddi_get_power_domains (Ville) v2: * Fix tabs, const crtc_state, fix comments (Ville) Suggested-by: Ville Syrjala <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Imre Deak <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dp: Disable DSC in source by disabling DSS CTL bitsManasi Navare3-0/+34
1. Disable Left/right VDSC branch in DSS Ctrl reg depending on the number of VDSC engines being used 2. Disable joiner in DSS Ctrl reg v4: * Remove encoder, make crtc_state const (Ville) v3 (From Manasi): * Add Disable PG2 for VDSC on eDP v2 (From Manasi): * Use old_crtc_state to find dsc params * Add a condition to disable only if dsc state compression is enabled * Use correct DSS CTL regs Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: Gaurav K Singh <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dp: Configure Display stream splitter registers during DSC enableManasi Navare1-0/+22
Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v4: * Remove redundant comment (Ville) v3: * Use cpu_transcoder instead of encoder->type (Ville) v2: * Rebase (Manasi) Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dp: Populate DSC PPS SDP and send PPS infoframesManasi Navare1-0/+21
DSC PPS secondary data packet infoframes are filled with DSC picure parameter set metadata according to the DSC standard. These infoframes are sent to the sink device and used during DSC decoding. v3: * Rename to intel_dp_write_pps_sdp (Ville) * Use const intel_crtc_state (Ville) v2: * Rebase ond drm-tip Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare2-2/+20
Infoframes are used to send secondary data packets. This patch adds support for DSC Picture parameter set secondary data packets in the existing write_infoframe helpers. v3: * Unused variables cleanup (Ville) v2: * Rebase on drm-tip (Manasi) Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enablingManasi Navare3-0/+413
After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the pipe and after compression is enabled on the sink. v7: * Remove unnecessary comments, leftovers (Ville) * No need for explicit val &= ~ (Ville) v6: intel_dsc_enable to be part of pre_enable hook (Ville) v5: * make crtc_state const (Ville) v4: * Use cpu_transcoder instead of encoder->type for using EDP transcoder DSC registers(Ville) * Keep all PSS regs together (Anusha) v3: * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe are used (Manasi) * Add DSC slice_row_per_frame in PPS16 (Manasi) v2: * Enable PG2 power well for VDSC on eDP Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> [manasi: fixup the line longer than 100 chars while applying] Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-29drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSIManasi Navare2-1/+4
On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2. v3: * Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville) * Move it around TRANSCODER power domain defs (Ville) v2: * Fix the power well mismatch CI error (Ville) * Rename as VDSC_PIPE_A (Imre) * Fix a whitespace (Anusha) * Fix Comments (Imre) Cc: Ville Syrjala <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Imre Deak <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Ville Syrjala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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