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2018-12-05drm: Add a new helper to validate damage during atomic_checkDeepak Rawat3-0/+40
This helper function makes sure that damage from plane state is discarded for full modeset. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]>
2018-12-05drm: Add a new plane property to send damage during plane updateLukasz Spintzyk10-1/+244
FB_DAMAGE_CLIPS is an optional plane property to mark damaged regions on the plane in framebuffer coordinates of the framebuffer attached to the plane. The layout of blob data is simply an array of "struct drm_mode_rect". Unlike plane src coordinates, damage clips are not in 16.16 fixed point. As plane src in framebuffer cannot be negative so are damage clips. In damage clip, x1/y1 are inclusive and x2/y2 are exclusive. This patch also exports the kernel internal drm_rect to userspace as drm_mode_rect. This is because "struct drm_clip_rect" is not sufficient to represent damage for current plane size. Driver which are interested in enabling FB_DAMAGE_CLIPS property for a plane should enable this property using drm_plane_enable_damage_clips. v2: - Input validation on damage clips against framebuffer size. - Doc update, other minor changes. Signed-off-by: Lukasz Spintzyk <[email protected]> Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]>
2018-12-05drm/exynos: mixer: Fix color range settingChristoph Manszewski2-9/+17
Color format and color range was set based on resolution. Change that, by splitting range and format. Leave color format setting as it is, set color range based on drm_display_mode using drm_default_quant_range helper function. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20181128 using modetest. Signed-off-by: Christoph Manszewski <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-05drm/exynos: mixer: Fix color format settingChristoph Manszewski1-8/+2
Fix color format decision based on height(pixels). According to CEA-861-E: "High Definition (HD) - A CE video format that, inclusively, has between 720 to 1080 active vertical lines (Vactive) lines per video frame." Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20181128 using modetest. Signed-off-by: Christoph Manszewski <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-05drm/exynos: decon: Make pixel blend mode configurableChristoph Manszewski2-10/+70
The decon hardware supports different blend modes. Add pixel blend mode property and make it configurable, by modifying the blend equation. Tested on TM2 with Exynos 5433 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-05drm/exynos: decon: Make plane alpha configurableChristoph Manszewski2-0/+40
The decon hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TM2 with Exynos 5433 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-05Merge tag 'imx-drm-next-2018-12-03' of ↵Dave Airlie11-268/+940
git://git.pengutronix.de/git/pza/linux into drm-next drm/imx: update image-convert with fixes for multi-tiled scaling Update the ipu-v3 mem2mem image-convert code, with some fixes for race conditions, alignment issues, and visual artifacts due to tile alignment and scaling factor issues when scaling images larger than hardware limitations in multiple tiles. This will allow the V4L2 mem2mem scaler driver to write output images larger than 1024x1024 pixels. Also switch drm/imx source files to SPDX license identifiers, constify struct clk_ops in imx-tve, and add a timeout warning to the busy wait in ipu_plane_disable(). Signed-off-by: Dave Airlie <[email protected]> From: Philipp Zabel <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Update DRIVER_DATE to 20181204Jani Nikula1-2/+2
Signed-off-by: Jani Nikula <[email protected]>
2018-12-04drm/i915/icl: fix transcoder state readoutJani Nikula1-21/+31
Commit 2ca711caeca2 ("drm/i915/icl: Consider DSI for getting transcoder state") clobbers the previously read TRANS_DDI_FUNC_CTL_EDP register contents with TRANS_DDI_FUNC_CTL_DSI0 contents. Fix the state readout, and handle DSI 1 while at it. Use a bitmask for iterating and logging transcoders, because the allowed combinations are a bit funky. Fixes: 2ca711caeca2 ("drm/i915/icl: Consider DSI for getting transcoder state") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108928 Cc: Ville Syrjala <[email protected]> Cc: Madhav Chauhan <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Allocate a common scratch pageChris Wilson7-86/+74
Currently we allocate a scratch page for each engine, but since we only ever write into it for post-sync operations, it is not exposed to userspace nor do we care for coherency. As we then do not care about its contents, we can use one page for all, reducing our allocations and avoid complications by not assuming per-engine isolation. For later use, it simplifies engine initialisation (by removing the allocation that required struct_mutex!) and means that we can always rely on there being a scratch page. v2: Check that we allocated a large enough scratch for I830 w/a Fixes: 06e562e7f515 ("drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5") # v4.18.20 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108850 Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Cc: Joonas Lahtinen <[email protected]> Cc: <[email protected]> # v4.18.20+
2018-12-04drm/tinydrm: Use kmemdup rather than duplicating its implementation in ↵YueHaibing1-2/+1
repaper_spi_transfer() use kmemdup rather than duplicating its implementation Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Noralf Trønnes <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Trim unused workaround list entriesTvrtko Ursulin1-1/+15
The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab. v2: * Simplify with kmemdup. (Chris Wilson) v3: * Refactor for __size removal. Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Fuse per-context workaround handling with the common frameworkTvrtko Ursulin9-209/+168
Convert the per context workaround handling code to run against the newly introduced common workaround framework and fuse the two to use the existing smarter list add helper, the one which does the sorted insert and merges registers where possible. This completes migration of all four classes of workarounds onto the common framework. Existing macros are kept untouched for smaller code churn. v2: * Rename to list name ctx_wa_list and move from dev_priv to engine. v3: * API rename and parameters tweaking. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Move register white-listing to the common workaround frameworkTvrtko Ursulin6-73/+60
Instead of having a separate list of white-listed registers we can trivially move this to the common workarounds framework. This brings us one step closer to the goal of driving all workaround classes using the same code. v2: * Use GEM_DEBUG_WARN_ON for the sanity check. (Chris Wilson) v3: * API rename. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915/selftests: Add tests for GT and engine workaround verificationTvrtko Ursulin6-47/+214
Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is not affecting workarounds not belonging to itself.) v2: * Rebase for series refactoring. * Add spinner for actual engine reset! * Add idle reset test as well. (Chris Wilson) * Share existing global_reset_lock. (Chris Wilson) v3: * intel_engine_verify_workarounds can be static. * API rename. (Chris Wilson) * Move global reset lock out of the loop. (Chris Wilson) v4: * Add missing rpm puts. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Verify GT workaround state after GPU initTvrtko Ursulin4-0/+40
Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver. Initially we only do this after GPU initialization. v2: Chris Wilson: * Simplify verification by realizing it's a simple xor and and. * Remove verification from engine reset path. * Return bool straight away from the verify API. v3: * API rename. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Introduce per-engine workaroundsTvrtko Ursulin5-119/+153
We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected. This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla). Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over. Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges. v2: * Move Wa_1406609255:icl to engine workarounds as well. * Rename API. (Chris Wilson) * Drop redundant IS_KABYLAKE. (Chris Wilson) * Re-order engine wa/ init so latest platforms are first. (Rodrigo Vivi) Signed-off-by: Tvrtko Ursulin <[email protected]> Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945 Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds") Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: [email protected] Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Record GT workarounds in a listTvrtko Ursulin5-168/+354
To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied. The added data structure is a simple array of register, mask and value items, which is allocated on demand as workarounds are added to the list. This is a temporary implementation which later in the series gets fused with the existing per context workaround list handling. It is separated at this stage since the following patch fixes a bug which needs to be as easy to backport as possible. Also, since in the following patch we will be adding a new class of workarounds (per engine) which can be applied from interrupt context, we straight away make the provision for safe read-modify-write cycle. v2: * Change dev_priv to i915 along the init path. (Chris Wilson) * API rename. (Chris Wilson) v3: * Remove explicit list size tracking in favour of growing the allocation in power of two chunks. (Chris Wilson) v4: Chris Wilson: * Change wa_list_finish to early return. * Copy workarounds using the compiler for static checking. * Do not bother zeroing unused entries. * Re-order struct i915_wa_list. v5: * kmalloc_array. * Whitespace cleanup. Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: change i915_sw_fence license to MITJonathan Gray2-8/+4
Change the license of the i915_sw_fence files to MIT matching most of the other i915 files. This makes it possible to use them in a new port of i915 to OpenBSD. Besides some mechanical tree wide changes Chris Wilson is the sole author of these files with Intel holding the copyright. Intel's legal team have given permission to change the license according to Joonas Lahtinen. v2: expand commit message and note permission from Intel legal Signed-off-by: Jonathan Gray <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915: Complete the fences as they are cancelled due to wedgingChris Wilson3-48/+30
We inspect the requests under the assumption that they will be marked as completed when they are removed from the queue. Currently however, in the process of wedging the requests will be removed from the queue before they are completed, so rearrange the code to complete the fences before the locks are dropped. <1>[ 354.473346] BUG: unable to handle kernel NULL pointer dereference at 0000000000000250 <6>[ 354.473363] PGD 0 P4D 0 <4>[ 354.473370] Oops: 0000 [#1] PREEMPT SMP PTI <4>[ 354.473380] CPU: 0 PID: 4470 Comm: gem_eio Tainted: G U 4.20.0-rc4-CI-CI_DRM_5216+ #1 <4>[ 354.473393] Hardware name: Intel Corporation NUC7CJYH/NUC7JYB, BIOS JYGLKCPX.86A.0027.2018.0125.1347 01/25/2018 <4>[ 354.473480] RIP: 0010:__i915_schedule+0x311/0x5e0 [i915] <4>[ 354.473490] Code: 49 89 44 24 20 4d 89 4c 24 28 4d 89 29 44 39 b3 a0 04 00 00 7d 3a 41 8b 44 24 78 85 c0 74 13 48 8b 93 78 04 00 00 48 83 e2 fc <39> 82 50 02 00 00 79 1e 44 89 b3 a0 04 00 00 48 8d bb d0 03 00 00 <4>[ 354.473515] RSP: 0018:ffffc900001bba90 EFLAGS: 00010046 <4>[ 354.473524] RAX: 0000000000000003 RBX: ffff8882624c8008 RCX: f34a737800000000 <4>[ 354.473535] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff8882624c8048 <4>[ 354.473545] RBP: ffffc900001bbab0 R08: 000000005963f1f1 R09: 0000000000000000 <4>[ 354.473556] R10: ffffc900001bba10 R11: ffff8882624c8060 R12: ffff88824fdd7b98 <4>[ 354.473567] R13: ffff88824fdd7bb8 R14: 0000000000000001 R15: ffff88824fdd7750 <4>[ 354.473578] FS: 00007f44b4b5b980(0000) GS:ffff888277e00000(0000) knlGS:0000000000000000 <4>[ 354.473590] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 354.473599] CR2: 0000000000000250 CR3: 000000026976e000 CR4: 0000000000340ef0 <4>[ 354.473611] Call Trace: <4>[ 354.473622] ? lock_acquire+0xa6/0x1c0 <4>[ 354.473677] ? i915_schedule_bump_priority+0x57/0xd0 [i915] <4>[ 354.473736] i915_schedule_bump_priority+0x72/0xd0 [i915] <4>[ 354.473792] i915_request_wait+0x4db/0x840 [i915] <4>[ 354.473804] ? get_pwq.isra.4+0x2c/0x50 <4>[ 354.473813] ? ___preempt_schedule+0x16/0x18 <4>[ 354.473824] ? wake_up_q+0x70/0x70 <4>[ 354.473831] ? wake_up_q+0x70/0x70 <4>[ 354.473882] ? gen6_rps_boost+0x118/0x120 [i915] <4>[ 354.473936] i915_gem_object_wait_fence+0x8a/0x110 [i915] <4>[ 354.473991] i915_gem_object_wait+0x113/0x500 [i915] <4>[ 354.474047] i915_gem_wait_ioctl+0x11c/0x2f0 [i915] <4>[ 354.474101] ? i915_gem_unset_wedged+0x210/0x210 [i915] <4>[ 354.474113] drm_ioctl_kernel+0x81/0xf0 <4>[ 354.474123] drm_ioctl+0x2de/0x390 <4>[ 354.474175] ? i915_gem_unset_wedged+0x210/0x210 [i915] <4>[ 354.474187] ? finish_task_switch+0x95/0x260 <4>[ 354.474197] ? lock_acquire+0xa6/0x1c0 <4>[ 354.474207] do_vfs_ioctl+0xa0/0x6e0 <4>[ 354.474217] ? __fget+0xfc/0x1e0 <4>[ 354.474225] ksys_ioctl+0x35/0x60 <4>[ 354.474233] __x64_sys_ioctl+0x11/0x20 <4>[ 354.474241] do_syscall_64+0x55/0x190 <4>[ 354.474251] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4>[ 354.474260] RIP: 0033:0x7f44b3de65d7 <4>[ 354.474267] Code: b3 66 90 48 8b 05 b1 48 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 81 48 2d 00 f7 d8 64 89 01 48 <4>[ 354.474293] RSP: 002b:00007fff974948e8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 <4>[ 354.474305] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f44b3de65d7 <4>[ 354.474316] RDX: 00007fff97494940 RSI: 00000000c010646c RDI: 0000000000000007 <4>[ 354.474327] RBP: 00007fff97494940 R08: 0000000000000000 R09: 00007f44b40bbc40 <4>[ 354.474337] R10: 0000000000000000 R11: 0000000000000246 R12: 00000000c010646c <4>[ 354.474348] R13: 0000000000000007 R14: 0000000000000000 R15: 0000000000000000 v2: Avoid floating requests. v3: Can't call dma_fence_signal() under the timeline lock! v4: Can't call dma_fence_signal() from inside another fence either. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/vkms: Remove set but not used variable 'vkms_obj'YueHaibing1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/vkms/vkms_plane.c: In function 'vkms_prepare_fb': drivers/gpu/drm/vkms/vkms_plane.c:144:26: warning: variable 'vkms_obj' set but not used [-Wunused-but-set-variable] It never used since introduction in commit 8ce1bb0b5337 ("drm/vkms: map/unmap buffers in [prepare/cleanup]_fb hooks") Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/i915/dp: Fix inconsistent indentingChris Wilson1-7/+6
Always show the FEC capability as it is initialised to 0 before error. Fixing, drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register") Signed-off-by: Chris Wilson <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> Cc: Manasi Navare <[email protected]> Cc: Anusha Srivatsa <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/sun4i: Add compatible for H6 display engineJernej Skrabec1-0/+1
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC. Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-04drm/exynos/iommu: merge IOMMU and DMA codeAndrzej Hajda4-209/+128
As DMA code is the only user of IOMMU code both files can be merged. It allows to remove stub functions, after slight adjustment of exynos_drm_register_dma. Since IOMMU functions are used locally they can be marked static. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-04drm/exynos/iommu: replace preprocessor conditionals with C conditionalsAndrzej Hajda1-72/+36
Using C conditionals is preferred solution - it provides better code coverage, makes code more clear. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-04drm/exynos/iommu: move IOMMU specific stuff into exynos_drm_iommu.cAndrzej Hajda2-72/+72
Since __exynos_iommu* functions are used only in exynos_drm_iommu.c we can move them there. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-04drm/exynos/iommu: integrate IOMMU/DMA internal APIAndrzej Hajda17-58/+61
Exynos DRM drivers should work with and without IOMMU. Providing common API generic to both scenarios should make code cleaner and allow further code improvements. The patch removes including of exynos_drm_iommu.h as the file contains mostly IOMMU specific stuff, instead it exposes exynos_drm_*_dma functions and puts them into exynos_drm_dma.c. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-04drm/exynos/iommu: remove DRM_EXYNOS_IOMMU Kconfig symbolAndrzej Hajda3-7/+2
DRM_EXYNOS_IOMMU symbol is not configurable, it is always equal to EXYNOS_IOMMU. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-04drm/exynos: simplify DMA mappingAndrzej Hajda11-54/+37
Moving DMA mapping creation to drm_iommu_attach_device allows to avoid looping through all components and maintaining DMA device flags. v2: take care of configurations without IOMMU Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2018-12-03drm/i915: Move display device info capabilities to its own structJosé Roberto de Souza6-78/+103
This helps separate what capabilities are display capabilities. v3: Moving display struct right after flags (Lucas) Cc: Jani Nikula <[email protected]> Suggested-by: Jani Nikula <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915: Add HAS_DISPLAY() and use itJosé Roberto de Souza7-12/+14
Right now it is decided if GEN has display by checking the num_pipes, so lets make it explicit and use a macro. Cc: Jani Nikula <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/dp: Fix link compute m_n calc for DSCManasi Navare1-1/+1
Fix the intel_link_compute_m_n in case of display stream compression. This patch passes the compressed_bpp to intel_link_compute_m_n if compression is enabled. Fixes: a4a157777c80 ("drm/i915/dp: Compute DSC pipe config in atomic check") Cc: Ville Syrjala <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/v3d: Add more tracepoints for V3D GPU rendering.Eric Anholt3-3/+121
The core scheduler tells us when the job is pushed to the scheduler's queue, and I had the job_run functions saying when they actually queue the job to the hardware. By adding tracepoints for the very top of the ioctls and the IRQs signaling job completion, "perf record -a -e v3d:.\* -e gpu_scheduler:.\* <job>; perf script" gets you a pretty decent timeline. Signed-off-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Dave Emett <[email protected]>
2018-12-03drm/v3d: Add missing fence timeline name for TFU.Eric Anholt1-2/+8
We shouldn't be returning v3d-render for our new queue. Signed-off-by: Eric Anholt <[email protected]> Fixes: 83d5139982db ("drm/v3d: Add support for submitting jobs to the TFU.") Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Dave Emett <[email protected]>
2018-12-03drm/syncobj: use dma_fence_get_stubChristian König1-44/+14
Extract of useful code from the timeline work. Let's use just a single stub fence instance instead of allocating a new one all the time. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Link: https://patchwork.freedesktop.org/patch/265248/
2018-12-03dma-buf: add dma_fence_get_stubChristian König2-1/+36
Extract of useful code from the timeline work. This provides a function to return a stub or dummy fence which is always signaled. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Link: https://patchwork.freedesktop.org/patch/265248/
2018-12-03drm/i915/sysfs: make attrs arrays constJani Nikula1-2/+2
They don't need to be modified. Cc: Greg Kroah-Hartman <[email protected]> Cc: "Rafael J. Wysocki" <[email protected]> Reviewed-by: Rafael J. Wysocki <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03sysfs: constify sysfs create/remove files harderJani Nikula2-6/+6
Let the passed in array be const (and thus placed in rodata) instead of a mutable array of const pointers. Cc: Greg Kroah-Hartman <[email protected]> Cc: "Rafael J. Wysocki" <[email protected]> Reviewed-by: Rafael J. Wysocki <[email protected]> Reviewed-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/vgpu: Disallow loading on old vGPU hostsChris Wilson3-40/+22
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we actually broke the force-mmio mode for our execlists implementation. No one noticed, so ergo no one is actually using an old vGPU host (where we required the older method) and so can simply remove the broken support. v2: csb_read can go as well (Mika) Reported-by: Mika Kuoppala <[email protected]> Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/panel: simple: Add AUO G101EVN010 panel supportAlex Gonzalez2-0/+39
The change adds support for the AU Optronics G101EVN010 10.1" TFT LCD panel. Signed-off-by: Alex Gonzalez <[email protected]> Reviewed-by: Rob Herring <[email protected]> [[email protected]: sort new entry alphabetically] Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rateChris Wilson1-5/+1
Change the on-cpu check to on-runqueue to catch if the waiter has been woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to perform the seqno check) but is sleeping due to being preempted off the cpu. Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/icl: add pll mapping for DSIJani Nikula1-0/+25
Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function. v2: add posting read (Madhav) Cc: Madhav Chauhan <[email protected]> Cc: Vandita Kulkarni <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-03drm/i915/icl: Ungate DSI clocksMadhav Chauhan1-0/+19
Ungate the clocks on the selected port. Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/2a01b3158feda624f98581b780854fe3df8c328d.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Gate clocks for DSIMadhav Chauhan1-0/+20
As per BSPEC, depending on the DSI transcoder being used, DDI clock for the associated port should be gated. This patch does the same. Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/e032bc3d8fff91b8c2631c73121268214615a7e8.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: add dummy DSI GPIO element execution functionJani Nikula1-1/+9
Add dummy debug logging GPIO element execution function for ICL. Reviewed-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f59009ea0a0ebc489a5ec66f387d9dcf7264141f.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define display GPIO pins for DSIMadhav Chauhan1-0/+12
Display Pins are the only GPIOs that need to be used by driver for DSI panels. So driver should now have its own implementation to toggle these pins based on GPIO info received from VBT sequences. Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/e7e3bb05d4f48b1876169a69f495bcf6d511fda5.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan1-0/+11
There are two panel power sequencers. Each register has two addressable instances. This patch defines both the instances of Panel power control register Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/99bb687b17a9165527a6210a79271c8175c8a4e3.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan1-0/+1
This patch define missing bitfield for shortplug ctl ddi register which will be used for ICL DSI GPIO programming. Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/4b9feb75eb6c303556b91c8a23c505a4593a99a1.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get pipe timings for DSIMadhav Chauhan1-1/+2
Transcoder timings for Gen11 DSI encoder is available at pipe level unlike in older platform where port specific registers need to be accessed. v2 by Jani: - get timings for (!dsi || icl) instead of (dsi && icl). Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f60e0c1aee08248e758da3219d3239898b43ba41.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Consider DSI for getting transcoder stateMadhav Chauhan1-7/+24
For Gen11 DSI, we use similar registers like for eDP to find if DSI encoder is connected or not to a pipe. This patch refactors existing hsw_get_transcoder_state() to handle this. v2 by Jani: - Add WARN_ON(dsi && edp) (Ville) Signed-off-by: Madhav Chauhan <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/2e10b977dfc7aa985a8559d6cd59ed0981848e95.1543500286.git.jani.nikula@intel.com
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