aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2020-04-09drm/amd/display: blank dp stream before power off receiverXiaodong Yan1-0/+8
[why] power off dp receiver directly cause garbage during hw init [how] blank dp stream and then power off receiver Signed-off-by: Xiaodong Yan <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Power down hw blocks on bootSung Lee3-0/+34
[WHY] On headless boot a DIG may be turned on by VBIOS on RN. This leads to display_count being non-zero in hybrid graphics cases leading to SMU DISPLAY_OFF message not being sent. [HOW] Power down hardware on boot if seamless boot is not occurring (power_down_display_on_boot == 1) Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Remove hdcp display state with mst fixIsabel Zhang6-47/+26
[Why] Due to previous code changes, displays transition from active to active and added state immediately, making it redundant to have both display states. Previous change to fix this caused HDCP to get into a bad state when monitor is connected to MST hub, this change fixes that issue. [How] Change code behavior so when a device is added successfully the state remains as active and when addition is unsuccessful change state to inactive. This removes need for added and active state. Signed-off-by: Isabel Zhang <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Implement abm config table copy to dmcubWyatt Wood6-9/+37
[Why] Driver must pass abm config table to dmub fw. This provides various parameters for abm functionality. [How] There is too much data to be passed in an inbox message, so we must pass this data using an indirect buffer. Copy the table to cw7 via x86, driver copies to fw_state structure. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Program DSC before enabling linkNikola Cornij1-5/+12
[why] Link or DIG BE can't be exposed to a higher stream bandwidth than they can handle. When DSC is required to fit the stream into the link bandwidth, DSC has to be programmed before the link is enabled to ensure this. Without it, intermittent issues such as black screen after S3 or a hot-plug can be seen with DSC timings like 4k144Hz or 8k60Hz. [how] Move DSC programming from before enabling stream to before enabling link Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: prevent loop from occuring in pipe listJosip Pavic1-3/+2
[Why] If no free pipes are available, acquire_first_split_pipe is called to get a pipe to use. This call may alter the ordering of the pipes in the list so that, for example, the tail pipe changes. If acquire_first_split_pipe returns the tail pipe, we'll have free_pipe == tail_pipe. What tail_pipe refers to is not the current tail_pipe, but what was previously the tail pipe - i.e. prior to the call to acquire_first_split_pipe The logic that follows will link free_pipe to the tail pipe, referring to the current tail pipe. However, since tail_pipe is cached from before the call to acquire_first_split_pipe, the wrong tail pipe will be used, and it will end up being linked to itself, creating a loop that, if traversed, will result in a soft hang. [How] Do not cache the tail pipe. Instead, check the tail pipe after the call to acquire_first_split_pipe is made. Signed-off-by: Josip Pavic <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: 3.2.78Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu resetJack Zhang1-0/+2
[PATCH 2/2] kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdkfd Avoid destroy hqd when GPU is on resetJack Zhang3-7/+2
This reverts commit 5161bba4311f in order to split it into two different patches, and this will make it easier to understand. [PATCH 1/2] porting to gfx10 from commit 1b0bfcff463f390c40 ("drm/amdgpu: Avoid destroy hqd when GPU is on reset") Originally, MEC is touched without GPU initialized first. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: update RAS related dmesg printJohn Clements2-7/+12
prefix RAS error related dmesg print with pci device info Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: resolve mGPU RAS query instabilityJohn Clements1-5/+15
upon receiving uncorrectable error, query every GPU node for ras errors Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/amdgpu: Correct gfx10's CG sequenceChengming Gui1-8/+15
Incorrect CG sequence will cause gfx timedout, if we keep switching power profile mode (enter profile mod such as PEAK will disable CG, exit profile mode EXIT will enable CG) when run Vulkan test case(case used for test: vkexample). Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: add SPM golden settings for Navi12Tianci.Yin1-0/+1059
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: add SPM golden settings for Navi14Tianci.Yin1-0/+627
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: add SPM golden settings for Navi10(v2)Tianci.Yin1-0/+1059
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: Print UTCL2 client ID on a gpuvm faultOak Zeng2-0/+6
UTCL2 client ID is useful information to get which UTCL2 client caused the gpuvm fault. Print it out for debug purpose Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian Konig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/powerplay: fix a typoNirmoy Das1-1/+1
Util -> Until Fixes: 567c8fc4a0d28b63f ("drm/amd/powerplay: implement the is_dpm_running()") Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu/vcn: add shared memory restore after wake up from sleep.James Zhu2-1/+28
VCN shared memory needs restore after wake up during S3 test. v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: Fix oops when pp_funcs is unset in ACPI eventAaron Ma1-1/+2
On ARCTURUS and RENOIR, powerplay is not supported yet. When plug in or unplug power jack, ACPI event will issue. Then kernel NULL pointer BUG will be triggered. Check for NULL pointers before calling. Signed-off-by: Aaron Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu/psp: dont warn on missing optional TA'sAlex Deucher1-3/+3
Replace dev_warn() with dev_info() and note that they are optional to avoid confusing users. The RAS TAs only exist on server boards and the HDCP and DTM TAs only exist on client boards. They are optional either way. Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: rework sched_list generationNirmoy Das35-197/+144
Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: sync ring type and drm hw_ip typeNirmoy Das1-10/+10
Use AMDGPU_HW_IP_* to set amdgpu_ring_type enum values Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu resetJack Zhang3-0/+8
kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. v2:add a bugfix for kiq ring test fail Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/display: fix the broken logic in dc_link.cYifan Zhang1-1/+2
Add missing braces. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/powerplay: avoid using pm_en before it is initializedTiecheng Zhou1-1/+2
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Tiecheng Zhou <[email protected]> Signed-off-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/powerplay: implement the is_dpm_running()Prike Liang1-0/+12
As the pmfw hasn't exported the interface of SMU feature mask to APU SKU so just force on all the features to driver inquired interface at early initial stage. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/display: re-order asic declarationsShirish S1-2/+4
Fixes build error of: "use of undeclared identifier 'RENOIR_A0'" To fix the same, this patch re-orders the ASIC declarations accordingly. Fixes: 41ef3dcd86443fa ("drm/amd/display: Fix RV2 Variant Detection") Signed-off-by: Shirish S <[email protected]> Reviewed-by: Zhan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLKYuxian Dai2-1/+7
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by: Yuxian Dai <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03amdgpu/drm: remove psp access on navi10 for sriovAlex Sierra1-9/+9
Navi ASICs don't require to access through PSP to osssys registers. This on SR-IOV configuration. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/display: Guard calls to hdcp_ta and dtm_taBhawanpreet Lakha3-167/+257
[Why] The buffer used when calling psp is a shared buffer. If we have multiple calls at the same time we can overwrite the buffer. [How] Add mutex to guard the shared buffer. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-03drm/amd/display: remove mod_hdcp_hdcp2_get_link_encryption_status()Bhawanpreet Lakha2-31/+0
It is not being used, so remove it Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/dc: Kill dc_conn_log_hex_linux()Lyude Paul3-45/+1
DRM already supports tracing DPCD transactions, there's no reason for the existence of this function. Also, it prints one byte per-line which is way too loud. So, just remove it. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/amdgpu_dm/mst: Remove useless sideband tracingLyude Paul1-43/+0
We already trace DPCD reads/writes on both MST and SST, there's no reason to have this code here (plus, toggling these things with a define at the top of the file isn't how we do things in the kernel). Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn: fix spelling mistake "fimware" -> "firmware"Colin Ian King1-1/+1
There is a spelling mistake in a dev_err error message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: fix and cleanup amdgpu_gem_object_close v4Christian König1-18/+25
The problem is that we can't add the clear fence to the BO when there is an exclusive fence on it since we can't guarantee the the clear fence will complete after the exclusive one. To fix this refactor the function and also add the exclusive fence as shared to the resv object. v2: fix warning v3: add excl fence as shared instead v4: squash in fix for fence handling in amdgpu_gem_object_close Signed-off-by: Christian König <[email protected]> Reviewed-by: xinhui pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/display: code cleanup of dc_link file on func dc_link_constructMelissa Wen1-44/+50
Removes codestyle issues in dc_link file, on dc_link_construct and translate_encoder_to_transmitter as suggested by checkpatch.pl. Types covered: CHECK: Lines should not end with a '(' WARNING: Missing a blank line after declarations CHECK: Alignment should match open parenthesis CHECK: Comparison to NULL could be written CHECK: Logical continuations should be on the previous line CHECK: Blank lines aren't necessary after an open brace '{' Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/display: code cleanup on dc_link from is_same_edid to get_ddc_lineMelissa Wen1-68/+62
Removes codestyle issues on the file dc_link between is_same_edid and get_ddc_line as suggested by checkpatch.pl. Types covered: CHECK: Blank lines aren't necessary after an open brace '{' CHECK: Blank lines aren't necessary before a close brace '}' WARNING: braces {} are not necessary for single statement blocks CHECK: Comparison to NULL could be written CHECK: Lines should not end with a '(' CHECK: Alignment should match open parenthesis CHECK: Using comparison to false is error prone CHECK: Using comparison to true is error prone WARNING: Avoid multiple line dereference - prefer 'link->dpcd_caps.sink_count.bits.SINK_COUNT' CHECK: Unnecessary parentheses around WARNING: Missing a blank line after declarations Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/display: codestyle cleanup on dc_link file until detect_dp funcMelissa Wen1-60/+49
Removes codestyle issues on the file dc_link until detect_dp func as suggested by checkpatch.pl. Types covered: CHECK: Please don't use multiple blank lines CHECK: Comparison to NULL could be written ERROR: space required before the open parenthesis '(' CHECK: Alignment should match open parenthesis CHECK: Lines should not end with a '(' WARNING: please, no space before tabs WARNING: Comparisons should place the constant on the right side of the test WARNING: braces {} are not necessary for single statement blocks CHECK: Please don't use multiple blank lines Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/display: cleanup codestyle type BLOCK_COMMENT_STYLE on dc_linkMelissa Wen1-10/+15
Solve comments alignment problems on dc_link file Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: enable VCN2.5 DPG mode for ArcturusJames Zhu1-1/+1
Enable VCN2.5 DPG mode for arcturus after below items are applied. ASD: 0x21000023 SOS: 0x17003B VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 VBIOS: 23 Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn2.5: Add firmware w/r ptr reset syncJames Zhu1-5/+48
Add firmware write/read point reset sync through shared memory Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn2.0: Add firmware w/r ptr reset syncJames Zhu1-3/+39
Add firmware write/read point reset sync through shared memory Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn: Add firmware share memory supportJames Zhu2-0/+37
Added firmware share memory support for VCN. Current multiple queue mode is enabled only. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn2.5: stall DPG when WPTR/RPTR resetJames Zhu1-0/+21
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR resetJames Zhu1-0/+16
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn: fix race condition issue for dpg unpause mode switchJames Zhu2-11/+22
Couldn't only rely on enc fence to decide switching to dpg unpaude mode. Since a enc thread may not schedule a fence in time during multiple threads running situation. v3: 1. Rename enc_submission_cnt to dpg_enc_submission_cnt 2. Add dpg_enc_submission_cnt check in idle_work_handler v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu/vcn: fix race condition issue for vcn startJames Zhu2-7/+16
Fix race condition issue when multiple vcn starts are called. v2: Removed checking the return value of cancel_delayed_work_sync() to prevent possible races here. v3: Add total_submission_cnt to avoid gate power unexpectedly. v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: skip access sdma_v5_0 registers under SRIOV (v2)Yintian Tao1-36/+76
Due to the new L1.0b0c011b policy, many SDMA registers are blocked which raise the violation warning. There are total 6 pair register needed to be skipped when driver init and de-init. mmSDMA0/1_CNTL mmSDMA0/1_F32_CNTL mmSDMA0/1_UTCL1_PAGE mmSDMA0/1_UTCL1_CNTL mmSDMA0/1_CHICKEN_BITS, mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL v2: squash in warning fix Signed-off-by: Yintian Tao <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: stop disable the scheduler during HW finiChristian König20-104/+10
When we stop the HW for example for GPU reset we should not stop the front-end scheduler. Otherwise we run into intermediate failures during command submission. The scheduler should only be stopped in very few cases: 1. We can't get the hardware working in ring or IB test after a GPU reset. 2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset. 3. In amdgpu_ring_fini() when the driver unloads. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Nirmoy Das <[email protected]> Test-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/powerplay: added mutex protection on msg issuingEvan Quan3-2/+18
This could avoid the possible race condition. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.