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2015-09-03MIPS: Lasat: Move from deprecated __initcall to arch_initcall.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: unaligned: Move from deprecated __initcall to arch_initcall.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Sibyte: Move bus watcher from deprecated __initcall to device_initcallRalf Baechle1-1/+1
Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Rearrange ENTRYLO field definitionsJames Hogan2-34/+36
The generic field definitions (i.e. present before MIPS32/MIPS64) in mipsregs.h are conventionally not prefixed with MIPS_, so rename the recently added MIPS_ENTRYLO_* definitions for the G, V, D, and C fields to ENTRYLO_*. Also rearrange to put the EntryLo and EntryHi definitions in the right place in the file. Fixes: 8ab6abcb6aa4 ("MIPS: mipsregs.h: Add EntryLo bit definitions") Reported-by: Maciej W. Rozycki <[email protected]> Signed-off-by: James Hogan <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10725/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: dump_tlb: Dump FrameMask register if existsJames Hogan1-0/+8
The FrameMask register is relevant to the TLB so it should be dumped by dump_tlb_regs(), however it is only present in certain cores (r10000, r12000, r14000, r16000). Add dumping of it, conditional upon current_cpu_type(). Suggested-by: Joshua Kinard <[email protected]> Suggested-by: Maciej W. Rozycki <[email protected]> Signed-off-by: James Hogan <[email protected]> Cc: Joshua Kinard <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10724/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: dump_tlb: Only dump PageGrain if interestingJames Hogan1-1/+2
The PageGrain register may not exist if certain architectural features aren't present, therefore only print out its value when dumping the TLB registers if it is expected to contain fields relevant to the TLB. Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Reported-by: Joshua Kinard <[email protected]> Reported-by: Maciej W. Rozycki <[email protected]> Signed-off-by: James Hogan <[email protected]> Cc: Joshua Kinard <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10723/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Probe for small (1KiB) page supportJames Hogan3-0/+7
Probe Config3 for small page support. This will be useful to give clues as to whether the PageGrain register exists. Signed-off-by: James Hogan <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10722/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Refactor dumping of TLB registers for r3k/r4kJames Hogan6-28/+34
The TLB registers are dumped in a couble of places: - sysrq_tlbdump_single() - when dumping TLB state. - do_mcheck() - in response to a machine check error. The main TLB registers also differ between r3k and r4k, but r4k appears to be assumed. Refactor this code into a dump_tlb_regs() function, implemented for both r3k and r4k, and used by both of the above functions. Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Suggested-by: Maciej W. Rozycki <[email protected]> Signed-off-by: James Hogan <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10721/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03Documentation/sysrq.txt: Mention MIPS TLB dump (x)James Hogan1-0/+1
Commit d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs") added the 'x' sysrq key for dumping MIPS TLB entries, but didn't document it in Documentation/sysrq.txt. Add mention of the MIPS use of the 'x' SysRq key. Reported-by: Maciej W. Rozycki <[email protected]> Signed-off-by: James Hogan <[email protected]> Acked-by: Jonathan Corbet <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10720/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructionsMarkos Chandras1-1/+19
Commit c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") added support for emulating the new R6 BC1{EQ,NE}Z branches but it missed the case where the instruction that caused the exception was not on a DS. Signed-off-by: Markos Chandras <[email protected]> Fixes: c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") Cc: <[email protected]> # 4.0+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10738/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Allow m{f,t}hc emulation on MIPS R6Markos Chandras1-2/+2
The mfhc/mthc instructions are supported on MIPS R6 so emulate them if needed. Signed-off-by: Markos Chandras <[email protected]> Cc: <[email protected]> # 4.0+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10737/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Fix indentationMarkos Chandras1-4/+4
Fix indentation for the final 'else' blocks. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10735/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: cp1emu: Fix closing bracket for the d_fmt caseMarkos Chandras1-1/+4
The double format (d_fmt) case uses an opening bracket which then closes at the end of the word format (w_fmt). This can be rather confusing so add the closing bracket at the end of the d_fmt case and use another one for the w_fmt one. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10733/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Kconfig: Drop the EXPERIMENTAL tag from MIPS R6Markos Chandras1-2/+2
The MIPS R6 ISA support has been part of mainline since v4.0 and it should be in a good shape nowadays so it is not an experimental feature anymore. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10731/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle1-1/+1
These are bitfields and treating them as signed values doesn't make any sense. Signed-off-by: Ralf Baechle <[email protected]> Reported-by: Chris Packham <[email protected]>
2015-09-03MIPS: Use unsigned int when reading CP0 registersChris Packham1-2/+2
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There is little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. This has come up via u-boot[1] which sync's asm/mipsregs.h with the kernel. In u-boots case the value read from read_c0_count() is assigned to an unsigned long [2] which triggers a sign extension and causes a bug. U-boot should probably be more explicit about the types used for the timer_read_counter() API but that aside is there any reason to treat these values as signed integers? A quick grep around the arch/mips makes me thing that there may be some bugs lurking when read_c0_count() starts to yield a negative value but I haven't really explored any of them. [1] - http://lists.denx.de/pipermail/u-boot/2015-July/219086.html [2] - http://git.denx.de/?p=u-boot.git;a=blob;f=arch/mips/cpu/time.c#l11 Signed-off-by: Chris Packham <[email protected]> Cc: [email protected] Cc: Daniel Schwierzeck <[email protected]> Cc: Chris Packham <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10718/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: malta: Use generic platform_maar_initPaul Burton1-25/+0
The default implementation of platform_maar_init is sufficient for Malta boards where we want to allow speculation in the regions of memory corresponding to DDR & disallow it elsewhere. Drop the custom implementation such that the default is used, reducing the duplication of information provided by the Malta platform code. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: James Hogan <[email protected]> Cc: Markos Chandras <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10677/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: mm: default platform_maar_init using bootmem dataPaul Burton1-2/+34
Introduce a default weak implementation of platform_maar_init which makes use of the data that platforms already provide to the bootmem allocator. This should hopefully cover the most common configurations, reduce the duplication of information provided by platforms & leaves platforms with the option of providing a custom implementation if required. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Paolo Bonzini <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: [email protected] Cc: Ard Biesheuvel <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10676/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: MSA unaligned memory access supportLeonid Yegoshin1-0/+72
The MSA architecture specification allows for hardware to not implement unaligned vector memory accesses in some or all cases. A typical example of this is the I6400 core which does not implement unaligned vector memory access when the memory crosses a page boundary. The architecture also requires that such memory accesses complete successfully as far as userland is concerned, so the kernel is required to emulate them. This patch implements support for emulating unaligned MSA ld & st instructions by copying between the user memory & the tasks FP context in struct thread_struct, updating hardware registers from there as appropriate in order to avoid saving & restoring the entire vector context for each unaligned memory access. Tested both using an I6400 CPU and with a QEMU build hacked to produce AdEL exceptions for unaligned vector memory accesses. [[email protected]: - Remove #ifdef's - Move msa_op into enum major_op rather than #define - Replace msa_{to,from}_wd with {read,write}_msa_wr_{b,h,w,l} and the format-agnostic wrappers, removing the custom endian mangling for big endian systems. - Restructure the msa_op case in emulate_load_store_insn to share more code between the load & store cases. - Avoid the need for a temporary union fpureg on the stack by simply reusing the already suitably aligned context in struct thread_struct. - Use sizeof(*fpr) rather than hardcoding 16 as the size for user memory checks & copies. - Stop recalculating the address of the unaligned vector memory access and rely upon the value read from BadVAddr as we do for other unaligned memory access instructions. - Drop the now unused val8 & val16 fields in union fpureg. - Rewrite commit message. - General formatting cleanups.] Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Leonid Yegoshin <[email protected]> Cc: Huacai Chen <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Cc: Jie Chen <[email protected]> Cc: Markos Chandras <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10573/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Introduce accessors for MSA vector registersPaul Burton3-0/+261
Introduce accessor functions allowing the kernel to access arbitrary vector registers using an arbitrary data format. The accessors are implemented in assembly, using macros to avoid massive duplication, in order to make use of the existing support for MSA with & without toolchain support. The accessors will be used in a later patch. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Manuel Lauss <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10572/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Declare MSA MI10 instruction formatsLeonid Yegoshin1-1/+30
Declare a struct describing the MSA MI10 instruction format used for ld & st instructions, for use by subsequent patches. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Leonid Yegoshin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: [email protected] Cc: Markos Chandras <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10571/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Remove "__weak" definition from arch-specific linkage.hBjorn Helgaas1-1/+0
"__weak" is defined in include/linux/compiler-gcc.h. We shouldn't need an arch-specific definition. Remove the "__weak" definition from arch/mips/include/asm/linkage.h. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10689/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Remove "weak" from mips_cdmm_phys_base() declarationBjorn Helgaas2-3/+15
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). mips_cdmm_phys_base() is defined only in arch/mips/mti-malta/malta-memory.c so there's no problem with multiple definitions. But it works better to have a weak default implementation and allow a strong function to override it. Then we don't have to test whether a definition is present, and if there are ever multiple strong definitions, we get a link error instead of calling a random definition. Add a weak mips_cdmm_phys_base() definition and remove the weak annotation from the declaration in arch/mips/include/asm/cdmm.h. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10688/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Remove "weak" from get_c0_fdc_int() declarationBjorn Helgaas2-4/+7
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). The most elegant solution is to have a weak default implementation and allow a strong function to override it. Then we don't have to test whether a definition is present, and if there are ever multiple strong definitions, we get a link error instead of calling a random definition. Add a weak get_c0_fdc_int() definition with the default code and remove the weak annotation from the declaration. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10687/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Remove "weak" from get_c0_compare_int() declarationBjorn Helgaas2-5/+8
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). get_c0_compare_int() is defined in several files. Each definition is weak, so I assume Kconfig prevents two or more from being included. The caller contains default code used when get_c0_compare_int() isn't defined at all. Add a weak get_c0_compare_int() definition with the default code and remove the weak annotation from the declaration. Then the platform implementations will be strong and will override the weak default. If multiple platforms are ever configured in, we'll get a link error instead of calling a random platform's implementation. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10686/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: MT: Remove "weak" from vpe_run() declarationBjorn Helgaas2-6/+6
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). That's not a problem for vpe_run() because Kconfig ensures there's never more than one definition: - vpe_run() is defined in arch/mips/kernel/vpe-mt.c if CONFIG_MIPS_VPE_LOADER_MT=y - vpe_run() is defined in arch/mips/mti-malta/malta-amon.c if CONFIG_MIPS_CMP=y - CONFIG_MIPS_VPE_LOADER_MT cannot be set if CONFIG_MIPS_CMP=y But it's simpler to verify correctness if we remove "weak" from the picture and test the config symbols directly. Remove "weak" from the vpe_run() declaration and use #if to test whether a definition should be present. Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10684/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: VPE: Exit vpe_release() early if vpe_run() isn't definedBjorn Helgaas1-1/+6
vpe_run() is a weak symbol. If there's no definition of it, its value is zero. If vpe_run is zero, return failure early. We're going to fail anyway, so there's no point in getting a VPE and attempting to load it. Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10683/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: Remove "weak" from platform_maar_init() declarationBjorn Helgaas1-1/+1
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). platform_maar_init() is defined in: - arch/mips/mm/init.c (where it is marked "weak") - arch/mips/mti-malta/malta-memory.c (without annotation) The "weak" attribute on the platform_maar_init() extern declaration applies to the platform-specific definition in arch/mips/mti-malta/malta-memory.c, so both definitions are weak, and which one we get depends on link order. Remove the "weak" attribute from the declaration. That makes the malta definition strong, so it will always be preferred if it is present. Signed-off-by: Bjorn Helgaas <[email protected]> CC: [email protected] Reviewed-by: James Hogan <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10682/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it staticBjorn Helgaas2-11/+8
There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need to be weak, and it doesn't need an extern declaration. Remove the extern mips_cpc_phys_base() declaration and make it static. [[email protected]: Fixed conflict.] Signed-off-by: Bjorn Helgaas <[email protected]> CC: [email protected] Cc: Andrew Bresticker <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10681/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.hPaul Burton2-57/+0
The debug.h header provided some MIPS-specific debug macros, which are no longer used at all. Remove them. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10693/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: ops-emma2rh: Drop nonsensical db_assertPaul Burton1-4/+2
The db_assert call checks whether the bus_num pointer is non-NULL, but does so after said pointer has been dereferenced by the assignment on the previous line. Thus the check is pointless & likely to have been optimised out by the compiler anyway. The check_args function is static & only ever called from the local file with bus_num being a pointer to an on-stack variable, so the check seems somewhat overzealous anyway. Simply remove it. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10692/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: rt3883: Prepare rt3883_pci_irq_handler for irq argument removalThomas Gleixner1-2/+2
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: Jiang Liu <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10706/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: netlogic: Prepare ipi handlers for irq argument removalThomas Gleixner1-2/+4
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: Jiang Liu <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10705/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: octeon: Replace the homebrewn flow handlerThomas Gleixner1-11/+11
The gpio interrupt handling of octeon contains a homebrewn flow handler which calls either handle_level_irq or handle_edge_irq depending on the trigger type. Thats an extra conditional and call in the interrupt handling path. The proper way to handle different types and therefor different flows is to update the handler in the irq_set_type() callback. Remove the extra indirection and add the handler update to octeon_irq_ciu_gpio_set_type(). At mapping time it defaults to handle_level_irq which gets updated if the device tree contains a different trigger type. Signed-off-by: Thomas Gleixner <[email protected]> Cc: David Daney <[email protected]> Cc: Jiang Liu <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10704/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: ath91: Remove pointless irqdisable/enableThomas Gleixner1-16/+2
The various interrupt flow handlers in ath79 are cascading interrupt handlers. They all have a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. Signed-off-by: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10703/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: alchemy: Remove pointless irqdisable/enableThomas Gleixner1-2/+4
bcsr_csc_handler() is a cascading interrupt handler. It has a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. [[email protected]: Fold in followup fix from Thomas Gleixner.] Signed-off-by: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10702/ Patchwork: https://patchwork.linux-mips.org/patch/10708/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: bcm63xx: Use irq_set_handler_locked()Thomas Gleixner1-2/+2
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner <[email protected]> Cc: Jiang Liu <[email protected]> Cc: Julia Lawall <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10701/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: alchemy: Use irq_set_chip_handler_name_locked()Thomas Gleixner1-2/+2
Hand in irq_data and avoid the redundant lookup of irq_desc. Originally-from: Jiang Liu <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: LKML <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10700/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: irq: Use access helper irq_data_get_affinity_mask()Jiang Liu3-8/+11
This is a preparatory patch for moving irq_data struct members. Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10699/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: pci-rt3883: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+1
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10698/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: pci-ar724x: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10697/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: pci-ar71xx: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10696/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: jz4740: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: Julia Lawall <[email protected]> Cc: [email protected] Cc: LKML <[email protected]> Cc: Jiang Liu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10695/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: Set up FTLB probability for I6400Markos Chandras2-5/+15
Set up the I6400 FTLB probability similar to P5600 and proAptiv. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10652/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6Markos Chandras1-1/+10
R6 has dropped the MMUExtDef field from the config4 register and it now returns 0. However, the return value means nothing in that case and the only supported configuration for R6 is the VTLB+FTLB (MMUextDef == 3). As a result, rework the code so that the correct value is set for R6 cores. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10651/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: Add default case for the FTLB enable/disable codeMarkos Chandras1-3/+10
Add a default case for the FTLB enable/disable code. This will be used to detect that something went wrong in the set_ftlb_enable() function either because that function knows nothing about the running core, or simply because the core can't turn its FTLB on/off. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10650/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLBMarkos Chandras1-1/+0
We are so early in the boot process where we really don't want to stall and wait for CP0 FTLB related changes become visible so just drop the cp0 hazard barrier. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10649/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqsMarkos Chandras2-9/+28
CM3 uses a 64-bit counter and compare registers so add support for them in the GIC counter interrupt. Signed-off-by: Markos Chandras <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10648/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMsMarkos Chandras2-47/+84
Previously, the GIC accessors were only accessing u32 registers but newer CMs may actually be 64-bit on MIPS64 cores. As a result of which, extended these accessors to support 64-bit reads and writes. Signed-off-by: Markos Chandras <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10709/ Signed-off-by: Ralf Baechle <[email protected]>
2015-08-26MIPS: CM: Add support for reporting CM cache errorsMarkos Chandras3-111/+254
The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10646/ Signed-off-by: Ralf Baechle <[email protected]>
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