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2022-11-17drm/amdgpu: add irq source id definition for VCN/JPEG 4.0Tao Zhou1-0/+3
Add interrupt source id macros. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: add RAS error query for JPEG 4.0Tao Zhou2-0/+70
Initialize JPEG RAS structure and add error query interface. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: add RAS query support for VCN 4.0Tao Zhou2-0/+66
Initialize VCN RAS structure and add RAS status query function. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: define common jpeg_set_ras_funcsTao Zhou3-12/+19
Make the code reusable. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: define common vcn_set_ras_funcsTao Zhou3-12/+19
So the code can be reused. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: enable RAS for VCN/JPEG v4.0Tao Zhou1-1/+2
Set support flag for VCN/JPEG 4.0. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: Enable mode-1 reset for RAS recovery in fatal error modeYiPeng Chai2-1/+10
The patch is enabling mode-1 reset for RAS recovery in fatal error mode. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: Add support for RAS table at 0x40000Luben Tuikov1-1/+6
Add support for RAS table at I2C EEPROM address of 0x40000, since on some ASICs it is not at 0, but at 0x40000. Cc: Alex Deucher <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Tested-by: Kent Russell <[email protected]> Reviewed-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: Interpret IPMI data for product information (v2)Luben Tuikov1-98/+85
Don't assume FRU MCU memory locations for the FRU data fields, or their sizes, instead read and interpret the IPMI data, as stipulated in the IPMI spec version 1.0 rev 1.2. Extract the Product Name, Product Part/Model Number, and the Product Serial Number by interpreting the IPMI data. Check the checksums of the stored IPMI data to make sure we don't read and give corrupted data back the the user. Eliminate small I2C reads, and instead read the whole Product Info Area in one go, and then extract the information we're seeking from it. Eliminates a whole function, making this file smaller. v2: Clarify changes in the commit message. Cc: Alex Deucher <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Tested-by: Kent Russell <[email protected]> Reviewed-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: Bug-fix: Reading I2C FRU data on newer ASICsLuben Tuikov1-11/+25
Set the new correct default FRU MCU I2C address for newer ASICs, so that we can correctly read the Product Name, Product Part/Model Number and Serial Number. On newer ASICs, the FRU MCU was moved to I2C address 0x58. Cc: Alex Deucher <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Tested-by: Kent Russell <[email protected]> Reviewed-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: Allow non-standard EEPROM I2C addressLuben Tuikov1-1/+1
Allow non-standard EEPROM I2C address of 0x58, where the Device Type Identifier is 1011b, where we form 1011000b = 0x58 I2C address, as on some ASICs the FRU data lives there. Cc: Alex Deucher <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Tested-by: Kent Russell <[email protected]> Reviewed-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/i915/audio: Realign some function argumentsVille Syrjälä1-6/+6
Fix up some function argument alignment fails. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2022-11-17drm/i915/audio: Unify get_saved_enc()Ville Syrjälä1-9/+7
Make the two branches of get_saved_enc() look alike. Currently they look different even though they do exactly the same thing apart from == vs. != for the MST comparison. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Treat HDMI as DVI when cloningVille Syrjälä1-9/+9
When doing HDMI+non-HDMI cloning the other sink can't get the infoframes/etc. so stuff like limited range output is not a good idea. Similarly when doing HDMI+HDMI cloning on g4x (only platform where we allow it) only one of the ports can receive infoframes and so again using any fancy stuff is a bad idea. We also don't track the inforames/audio state per-port so we'd end up with some kind of random mismash state when multipled encoders try to compute the same stuff. And the hardware will in fact automagically disable audio/infoframe transmission if you try to enable it for multiple HDMI ports at the same time. Thus disable all HDMI specific features when cloning. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Force RGB output for DVI sinkVille Syrjälä1-3/+8
YCbCr output requires infoframes and whatnot, so don't allow it when dealing with a DVI sink (or a HDMI sink we wish to treat as DVI). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Introduce g4x_hdmi_compute_config()Ville Syrjälä2-4/+13
Start pulling some of the more platform specific things out from intel_hdmi_compute_config(). has_pch_encoder is clearly one such thing. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Reorder 12.4 lut udw vs. ldw functionsVille Syrjälä1-8/+8
Satisfy my ocd and define ilk_lut_12p4_ldw() before ilk_lut_12p4_udw(). That is the order all the other similar functions use. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Clean up chv CGM (de)gamma definesVille Syrjälä2-15/+19
Add the missing ldw vs. udw information to the CGM (de)gamma bit definitions to make it a bit easier to see which should be used where. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Clean up 12.4bit precision palette definesVille Syrjälä2-16/+21
Use consistent bit definitions for the 12.4bit precision palette bits. We just define these alongside the ilk/snb register definitions and point to those from the icl+ superfine segment defines (and we also already pointed to them from the ivb+ precision palette defines). Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Clean up 10bit precision palette definesVille Syrjälä2-12/+11
Use consistent bit definitions for the 10bit precision palette bits. We just define these alongside the ilk/snb register definitions and point to those from the ivb+ defines. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Clean up legacy palette definesVille Syrjälä2-18/+17
Use consistent bit definitions for the legacy gamma LUT. We just define these alongside the pre-ilk register definitions and point to those from the ilk+ defines. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Add device name to display tracepointsVille Syrjälä1-54/+107
Include dev_name() in the tracpoints so one can filter based on the device. Example: echo 'dev=="0000:00:02.0"' > events/i915/intel_cpu_fifo_underrun/filter v2: Reduce the magic macros, rebase Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Pass i915 to frontbuffer tracepointsVille Syrjälä2-6/+8
Pass the device to the frontbuffer tracpoints. Will be used later to include the device name in the tracpoints. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Print plane name in fbc tracepointsVille Syrjälä1-6/+15
Print the name of the plane in the fbc tracepoints. As the pipe<->plane assignment can vary on old hw it's probably more helpful to see both the plane and the pipe names together. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Jani Nikula <[email protected]>
2022-11-17drm/i915: Pass intel_plane to plane tracepointsVille Syrjälä2-16/+16
Pass intel_plane rather than drm_plane to the plane tracepoints. Matches what we do eg. with the fbc tracepoints. Using the same type for everything will help with digging out the device name from the plane in the future. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Jani Nikula <[email protected]>
2022-11-17drm/i915/mtl: C6 residency and C state type for MTL SAMediaBadal Nilawar3-5/+76
Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc. v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh) v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo) Change state name for MTL_CC0 to C0 (from "on") (Rodrigo) v7: Change state name for MTL_CC0 to RC0 (Rodrigo) Signed-off-by: Ashutosh Dixit <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/gt: Use RC6 residency types as arguments to residency functionsAshutosh Dixit7-60/+72
Previously RC6 residency functions directly accepted RC6 residency register MMIO offsets (there are four RC6 residency registers). This worked but required an assumption on the residency register layout so was not future proof. Therefore change RC6 residency functions to accept RC6 residency types instead of register MMIO offsets. The knowledge of register offsets as well as ID to offset mapping is now maintained solely in intel_rc6 and can be tailored for different platforms and different register layouts as need arises. v2: Address review comments by Jani N - Change residency functions to accept RC6 residency types instead of register ID's - s/intel_rc6_print_rc5_res/intel_rc6_print_residency/ - Remove "const enum" in function arguments - Naming: intel_rc6_* for enum - Use INTEL_RC6_RES_MAX and other minor changes v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani) Suggested-by: Rodrigo Vivi <[email protected]> Suggested-by: Jani Nikula <[email protected]> Reported-by: Jani Nikula <[email protected]> Signed-off-by: Ashutosh Dixit <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/mtl: Modify CAGF functions for MTLBadal Nilawar2-2/+14
Update CAGF functions for MTL to get actual resolved frequency of 3D and SAMedia. v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR) Move MTL branches in cagf functions to top (MattR) Fix commit message (Andi) v3: Added comment about registers not needing forcewake for Gen12+ and returning 0 freq in RC6 v4: Use REG_FIELD_GET and uncore (Rodrigo) Bspec: 66300 Signed-off-by: Ashutosh Dixit <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: Ashutosh Dixit <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915: Use GEN12_RPSTAT register for GT freqDon Hiatt4-6/+32
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if GT is in RC6. v2: - Fixed review comments(Ashutosh) - Added function intel_rps_read_rpstat_fw to read RPSTAT without forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) v3: - Updated commit title and message for more clarity (Ashutosh) - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in read_cagf (Ashutosh) v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo) Cc: Don Hiatt <[email protected]> Cc: Andi Shyti <[email protected]> Signed-off-by: Don Hiatt <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Signed-off-by: Ashutosh Dixit <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagfAshutosh Dixit3-15/+10
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to extract reg fields. This allows future patches touching this code to also consistently use REG_FIELD_GET and friends. Suggested-by: Rodrigo Vivi <[email protected]> Signed-off-by: Ashutosh Dixit <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/display: move restore state and ctx under display sub-structJani Nikula3-10/+14
Move display suspend/resume and display reset modeset state and ctx members under drm_i915_private display sub-struct. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/display: move global_obj_list under display sub-structJani Nikula5-8/+8
Move display global state member under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Remove a nearby stale comment while at it. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/display: move hti under display sub-structJani Nikula3-13/+15
Move display hti/hdport related members under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/hti: abstract hti handlingJani Nikula8-27/+79
The HTI or HDPORT handling is sprinkled around. Centralize to one place. Add a note about how subtle the mapping from HDPORT_STATE register to dpll mask actually is. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17Merge tag 'gvt-next-2022-11-17' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi8-19/+8
drm-intel-next gvt-next-2022-11-17 - kernel doc fixes - remove vgpu->released sanity check - small clean up Signed-off-by: Rodrigo Vivi <[email protected]> From: Zhenyu Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/i915/edp: wait power off delay at driver remove to optimize probeJani Nikula2-1/+13
Panel power off delay is the time the panel power needs to remain off after being switched off, before it can be switched on again. For the purpose of respecting panel power off delay at driver probe, assuming the panel was last switched off at driver probe is overly pessimistic. If the panel was never on, we'd end up waiting for no reason. We don't know what has happened before kernel boot, but we can make some assumptions: - The panel may have been switched off right before kernel boot by some pre-os environment. - After kernel boot, the panel may only be switched off by i915. - At i915 driver probe, only a previously loaded and removed i915 may have switched the panel power off. With these assumptions, we can initialize the last power off time to kernel boot time, if we also ensure i915 driver remove waits for the panel power off delay after switching panel power off. This shaves off the time it takes from kernel boot to i915 probe from the first panel enable, if (and only if) the panel was not already enabled at boot. The encoder destroy hook is pretty much the last place where we can wait, right after we've ensured the panel power has been switched off, and before the whole encoder is destroyed. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7417 Cc: Lee Shawn C <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Tested-by: Lee Shawn C <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-17drm/tests: helpers: Add SPDX headerMaxime Ripard2-0/+4
The SPDX header is missing, let's add it and fix the corresponding checkpatch warning. Suggested-by: Maíra Canal <[email protected]> Fixes: 44a3928324e9 ("drm/tests: Add Kunit Helpers") Reviewed-by: Maíra Canal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Maxime Ripard <[email protected]>
2022-11-17drm/tests: client: Remove extra blank linesMaxime Ripard1-2/+0
Some extra blank lines slipped through, remove them. Fixes: 8fc0380f6ba7 ("drm/client: Add some tests for drm_connector_pick_cmdline_mode()") Reviewed-by: Maíra Canal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Maxime Ripard <[email protected]>
2022-11-17drm/i915/gvt: Remove the unused function get_pt_type()Jiapeng Chong1-5/+0
The function get_pt_type is defined in the gtt.c file, but not called elsewhere, so delete this unused function. drivers/gpu/drm/i915/gvt/gtt.c:285:19: warning: unused function 'get_pt_type'. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2277 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Zhenyu Wang <[email protected]>
2022-11-17drm/i915: fix repeated words in commentswangjianli1-1/+1
Delete the redundant word 'the'. Signed-off-by: wangjianli <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Zhenyu Wang <[email protected]>
2022-11-17drm/i915/gvt: remove the vgpu->released and its sanity checkZhi Wang2-6/+0
The life cycle of a vGPU, which is represented by a vfio_device, has been managed by the VFIO core logic. Remove the vgpu->released, which was used for a sanity check on the removal path of the vGPU instance. The sanity check has already been covered in the VFIO core logic. Cc: Zhenyu Wang <[email protected]> Cc: Kevin Tian <[email protected]> Cc: Jason Gunthorpe <[email protected]> Cc: [email protected] Suggested-by: Alex Williamson <[email protected]> Signed-off-by: Zhi Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Zhenyu Wang <[email protected]>
2022-11-17i915/gvt: remove hardcoded value on crc32_start calculationPaulo Miguel Almeida1-1/+1
struct gvt_firmware_header has a crc32 member in which all members that come after the that field are used to calculate it. The previous implementation added the value '4' (crc32's u32 size) to calculate the crc32_start offset which came across as a bit cryptic until you take a deeper look at the struct. This patch changes crc32_start offset to the 'version' member which is the first member of the struct gvt_firmware_header after crc32. It's worth mentioning that doing a build before/after this patch results in no binary output differences. Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Zhenyu Wang <[email protected]>
2022-11-17drm/i915: gvt: fix kernel-doc trivial warningsMauro Carvalho Chehab4-6/+6
Some functions seem to have been renamed without updating the kernel-doc markup causing warnings. Also, struct intel_vgpu_dmabuf_obj is not properly documented, but has a kerneld-doc markup. Fix those warnings: drivers/gpu/drm/i915/gvt/aperture_gm.c:308: warning: expecting prototype for inte_gvt_free_vgpu_resource(). Prototype was for intel_vgpu_free_resource() instead drivers/gpu/drm/i915/gvt/aperture_gm.c:344: warning: expecting prototype for intel_alloc_vgpu_resource(). Prototype was for intel_vgpu_alloc_resource() instead drivers/gpu/drm/i915/gvt/cfg_space.c:257: warning: expecting prototype for intel_vgpu_emulate_cfg_read(). Prototype was for intel_vgpu_emulate_cfg_write() instead drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'vgpu' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'info' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'dmabuf_id' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'kref' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'initref' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/dmabuf.h:61: warning: Function parameter or member 'list' not described in 'intel_vgpu_dmabuf_obj' drivers/gpu/drm/i915/gvt/handlers.c:3066: warning: expecting prototype for intel_t_default_mmio_write(). Prototype was for intel_vgpu_default_mmio_write() instead drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting prototype for intel_gvt_switch_render_mmio(). Prototype was for intel_gvt_switch_mmio() instead drivers/gpu/drm/i915/gvt/page_track.c:131: warning: expecting prototype for intel_vgpu_enable_page_track(). Prototype was for intel_vgpu_disable_page_track() instead drivers/gpu/drm/i915/gvt/vgpu.c:215: warning: expecting prototype for intel_gvt_active_vgpu(). Prototype was for intel_gvt_activate_vgpu() instead drivers/gpu/drm/i915/gvt/vgpu.c:230: warning: expecting prototype for intel_gvt_deactive_vgpu(). Prototype was for intel_gvt_deactivate_vgpu() instead drivers/gpu/drm/i915/gvt/vgpu.c:358: warning: expecting prototype for intel_gvt_destroy_vgpu(). Prototype was for intel_gvt_destroy_idle_vgpu() instead Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/375c0c0ca2ef414f25e14f274457f77373a9268d.1657699522.git.mchehab@kernel.org Acked-by: Zhenyu Wang <[email protected]>
2022-11-17drm/i915/reg: Fix spelling mistake "Unsupport" -> "Unsupported"Colin Ian King1-1/+1
There is a spelling mistake in a gvt_vgpu_err error message. Fix it. Fixes: 695fbc08d80f ("drm/i915/gvt: replace the gvt_err with gvt_vgpu_err") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Zhi Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Zhi Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2022-11-17drm/amdgpu: cleanup amdgpu_hmm_range_get_pagesChristian König4-21/+11
Remove unused parameters and cleanup dead code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: rename the files for HMM handlingChristian König9-31/+33
Clean that up a bit, no functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: fix userptr HMM range handling v2Christian König7-51/+46
The basic problem here is that it's not allowed to page fault while holding the reservation lock. So it can happen that multiple processes try to validate an userptr at the same time. Work around that by putting the HMM range object into the mutex protected bo list for now. v2: make sure range is set to NULL in case of an error Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> CC: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: always register an MMU notifier for userptrChristian König1-5/+3
Since switching to HMM we always need that because we no longer grab references to the pages. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Felix Kuehling <[email protected]> CC: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu/dm/dp_mst: Don't grab mst_mgr->lock when computing DSC stateLyude Paul1-4/+0
Now that we've fixed the issue with using the incorrect topology manager, we're actually grabbing the topology manager's lock - and consequently deadlocking. Luckily for us though, there's actually nothing in AMD's DSC state computation code that really should need this lock. The one exception is the mutex_lock() in dm_dp_mst_is_port_support_mode(), however we grab no locks beneath &mgr->lock there so that should be fine to leave be. Gitlab issue: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Lyude Paul <[email protected]> Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share") Cc: <[email protected]> # v5.6+ Reviewed-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu/dm/mst: Use the correct topology mgr pointer in amdgpu_dm_connectorLyude Paul1-19/+18
This bug hurt me. Basically, it appears that we've been grabbing the entirely wrong mutex in the MST DSC computation code for amdgpu! While we've been grabbing: amdgpu_dm_connector->mst_mgr That's zero-initialized memory, because the only connectors we'll ever actually be doing DSC computations for are MST ports. Which have mst_mgr zero-initialized, and instead have the correct topology mgr pointer located at: amdgpu_dm_connector->mst_port->mgr; I'm a bit impressed that until now, this code has managed not to crash anyone's systems! It does seem to cause a warning in LOCKDEP though: [ 66.637670] DEBUG_LOCKS_WARN_ON(lock->magic != lock) This was causing the problems that appeared to have been introduced by: commit 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") This wasn't actually where they came from though. Presumably, before the only thing we were doing with the topology mgr pointer was attempting to grab mst_mgr->lock. Since the above commit however, we grab much more information from mst_mgr including the atomic MST state and respective modesetting locks. This patch also implies that up until now, it's quite likely we could be susceptible to race conditions when going through the MST topology state for DSC computations since we technically will not have grabbed any lock when going through it. So, let's fix this by adjusting all the respective code paths to look at the right pointer and skip things that aren't actual MST connectors from a topology. Gitlab issue: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Lyude Paul <[email protected]> Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share") Cc: <[email protected]> # v5.6+ Reviewed-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>