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2014-03-31MIPS: Loongson: Add UEFI-like firmware interface (LEFI) supportHuacai Chen7-20/+292
The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified Firmware Interface) has 3 advantages: 1, Firmware export a physical memory map which is similar to X86's E820 map, so prom_init_memory() will be more elegant that #ifdef clauses can be removed. 2, Firmware export a pci irq routing table, we no longer need pci irq routing fixup in kernel's code. 3, Firmware has a built-in vga bios, and its address is exported, the linux kernel no longer need an embedded blob. With the LEFI interface, Loongson-3A/2G and all their successors can use a unified kernel. All Loongson-based machines support this new interface except 2E/2F series. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongliang Tao <[email protected]> Signed-off-by: Hua Yan <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6632 Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Loongson 3: Add Lemote-3A machtypes definitionHuacai Chen3-9/+25
Add four Loongson-3 based machine types: MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops; MACH_LEMOTE_A1101 is mini-itx; MACH_LEMOTE_A1205 is all-in-one machine. The most significant differrent between A1004/A1201 and A1101/A1205 is the laptops have EC but others don't. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongliang Tao <[email protected]> Signed-off-by: Hua Yan <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6631 Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen5-5/+76
Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongliang Tao <[email protected]> Signed-off-by: Hua Yan <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Loongson: Add basic Loongson-3 definitionHuacai Chen4-2/+23
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongliang Tao <[email protected]> Signed-off-by: Hua Yan <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6629/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle4-0/+89
And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <[email protected]> Cc: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6066/
2014-03-31MIPS: BCM47XX: Add new file for device specific workaroundsRafał Miłecki4-1/+36
Signed-off-by: Rafał Miłecki <[email protected]> Cc: [email protected] Cc: Hauke Mehrtens <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6627/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: VR41xx: Mark GPIO lines used for IRQLinus Walleij1-0/+20
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Linus Walleij <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Alexandre Courbot <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6417/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Simplify ptrace_getfpregs FPU IR retrievalPaul Burton1-24/+1
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6147/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Simplify PTRACE_PEEKUSR for FPC_EIRPaul Burton2-76/+6
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6144/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin3-5/+3
If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31EDAC: Octeon: Add error injection supportDaniel Walker1-6/+171
This adds an ad-hoc error injection method. Octeon II doesn't have hardware support for injection, so this simulates it. Signed-off-by: Daniel Walker <[email protected]> Cc: David Daney <[email protected]> Cc: Doug Thompson <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5873/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31EDAC: Octeon: Fix lack of opstate_initDaniel Walker1-0/+2
If the opstate_init() isn't called the driver won't start properly. I just added it in what appears to be an appropriate place. Signed-off-by: Daniel Walker <[email protected]> Cc: David Daney <[email protected]> Cc: Doug Thompson <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5872/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Octeon: Remove SYS_HAS_DMA_OPSRichard Weinberger1-1/+0
The symbol is an orphan, get rid of it. Signed-off-by: Richard Weinberger <[email protected]> Cc: [email protected] (open list:MIPS) Cc: [email protected] (open list) Patchwork: https://patchwork.linux-mips.org/patch/6523/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: SEAD3: Don't use module_init in non-modular sead3-mtd.c codePaul Gortmaker1-2/+1
The sead3-mtd.o is built for obj-y -- and hence this code is always present. It will never be modular, so using module_init as an alias for __initcall can be somewhat misleading. Fix this up now, so that we can relocate module_init from init.h into module.h in the future. If we don't do this, we'd have to add module.h to obviously non-modular code, and that would be a worse thing. Note that direct use of __initcall is discouraged, vs. one of the priority categorized subgroups. As __initcall gets mapped onto device_initcall, our use of device_initcall directly in this change means that the runtime impact is zero -- it will remain at level 6 in initcall ordering. We also fix a missing semicolon, which this change uncovers. Signed-off-by: Paul Gortmaker <[email protected]> Reported-by: kbuild test robot <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6412/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Malta: Fix CONFIG_BLK_DEV_IDE vestiges.Ralf Baechle1-9/+13
Don't depend on CONFIG_IDE to make this more robust. Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2Huacai Chen2-4/+4
Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: No need to select ARCH_SUPPORTS_MSIPaul Bolle1-1/+0
Commit c24a8a7a9988 ("MIPS: Netlogic: Add MSI support for XLP") added "select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was already removed in v3.12, so that select is a nop. Drop it. Signed-off-by: Paul Bolle <[email protected]> Cc: Jayachandran C <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6521/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: perf: Add interAptiv supportDeng-Cheng Zhu1-2/+36
Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <[email protected]> Reviewed-by: Markos Chandras <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6528/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: perf: Add proAptiv supportDeng-Cheng Zhu1-2/+26
Choose event/cache maps and handle raw event mapping for proAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <[email protected]> Reviewed-by: Markos Chandras <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6527/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv supportDeng-Cheng Zhu1-4/+4
74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by: Deng-Cheng Zhu <[email protected]> Reviewed-by: Markos Chandras <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6526/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: JZ4740: Don't select HAVE_PWMJingoo Han1-1/+0
The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. The jz4740 platform uses the generic PWM framework, after the commit "f6b8a57 pwm: Add Ingenic JZ4740 support". Signed-off-by: Jingoo Han <[email protected]> Acked-by: Lars-Peter Clausen <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6525/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Restore init.h usage to arch/mips/ar7/time.cPaul Gortmaker1-0/+1
Commit 0046be10e0c502705fc74d91408eba13a73bc201 ("mips: delete non-required instances of include <linux/init.h>") inadvertently removed an include that was actually correct. Restore it. Note that it gets init.h implicitly anyway, so this is largely a cosmetic fixup; no build regressions were caused by this. Signed-off-by: Paul Gortmaker <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6416/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: BCM47XX: Add Belkin F7Dxxxx board detectionCody P Schafer4-0/+16
Add a few Belkin F7Dxxxx entries, with F7D4401 sourced from online documentation and the "F7D7302" being observed. F7D3301, F7D3302, and F7D4302 are reasonable guesses which are unlikely to cause mis-detection. Signed-off-by: Cody P Schafer <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Cody P Schafer <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6594/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: BCM47XX: Add detection and GPIO config for Siemens SE505v2Hauke Mehrtens3-0/+31
This adds board detection for the Siemens SE505v2 and the led gpio configuration. This board does not have any buttons. This is based on OpenWrt broadcom-diag and Manuel Munz's nvram dump. Signed-off-by: Hauke Mehrtens <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6593/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: BCM47XX: Add button and led configuration for some Linksys devicesHauke Mehrtens2-0/+60
This adds led and button GPIO configuration for Linksys wrt54g3gv2, wrt54gsv1 and wrtsl54gs. This is based on OpenWrt broadcom-diag code. Signed-off-by: Hauke Mehrtens <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6592/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: BCM47XX: Detect some more Linksys devicesHauke Mehrtens2-2/+4
The Linksys WRT54G/GS/GL family uses the same boardtype numbers, and the same gpio configuration. The boardtype numbers are changing with the hardware versions, but these hardware numbers are different or each model. Detect them all as one device, this also worked in OpenWrt. Signed-off-by: Hauke Mehrtens <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6591/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: cpu-probe: Add support for probing M5150 coresLeonid Yegoshin1-0/+4
Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6597/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Add support for the M5150 processorLeonid Yegoshin7-1/+10
The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Add processor identifier for the M5150 processorLeonid Yegoshin1-0/+1
Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6595/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Add defconfig for Malta SMVP with EVAMarkos Chandras1-0/+200
Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6581/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Default NR_CPUS=8 for malta SMP defconfigsPaul Burton3-3/+3
The previous NR_CPUS=2 default is not an optimal default for current Malta setups where it is common to have more than 2 CPUs available. It makes sense to increase this to a number which covers all common setups currently in use, such that all of those cores are usable. 8 seems to fit that description. If the user has less than 8 CPUs & they wish to have a more optimal kernel they can simply reduce this in their config. It makes sense for the default to work on as many systems as possible. Signed-off-by: Paul Burton <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6580/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Set page size to 16KB for malta SMP defconfigsPaul Burton3-0/+3
For Malta defconfigs which may run on an SMP configuration without hardware cache anti-aliasing, a 16KB page size is a safer default. Most notably at the moment it will avoid cache aliasing issues for multicore proAptiv systems. Signed-off-by: Paul Burton <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6579/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Malta: Enable DEVTMPFSMarkos Chandras7-0/+7
Recent versions of udev and systemd require the kernel to be compiled with CONFIG_DEVTMPFS in order to populate the /dev directory. Most MIPS platforms have it enabled by default, so enable it for Malta configs as well. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6582/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Regenerate malta defconfigsPaul Burton7-26/+3
This patch simply regenerates the malta defconfigs such that they don't change after being used & saved as a defconfig again. ie. it is the result of running the following: for cfg in arch/mips/configs/malta*; do ARCH=mips make `basename ${cfg}` ARCH=mips make savedefconfig mv -v defconfig ${cfg} done Signed-off-by: Paul Burton <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6578/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Alchemy: pata_platform for DB1200Manuel Lauss2-10/+14
The au1xxx-ide driver isn't any faster than pata_platform since it spends a lot of time busy waiting for DMA to finish; faster PIO/DMA modes only work on the db1200 with a certain cpu speed, UDMA is broken, and finally the old IDE layer is on death row, so time to switch to the newer ATA layer. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6662/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board codeManuel Lauss4-133/+80
Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Alchemy: Unify Devboard support.Manuel Lauss12-863/+339
This patch merges support for all DB1xxx and PB1xxx boards into a single image, along with a new single defconfig for them. Run-tested on DB1300 and DB1500. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6577/ Patchwork: https://patchwork.linux-mips.org/patch/6659/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Alchemy: Determine cohereny at runtime based on cpu typeManuel Lauss4-8/+13
All Alchemy chips have coherent DMA, but for example the USB or AC97 peripherals on the Au1000/1500/1100 are not. This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based on CPU type. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6576/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss3-7/+7
Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Enable MIPS 3.5 features on MaltaMarkos Chandras1-0/+1
Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: Add support for SMP EVAMarkos Chandras2-1/+7
Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: malta-init: Fix System Controller memory mapping for EVALeonid Yegoshin1-0/+13
Shift System Controller memory mapping to 0x80000000 Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: malta-memory: Add free_init_pages_eva() callbackMarkos Chandras1-0/+8
Use a Malta specific function to free the init section once the kernel has booted. When operating in EVA mode, the physical memory is shifted to 0x80000000. Kernel is loaded into 0x80000000 (virtual) so the offset between physical and virtual addresses is 0. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory mapMarkos Chandras1-7/+7
PHYS_OFFSET is used to denote the physical start address of the first bank of RAM. When the Malta board is in EVA mode, the physical start address of RAM is shifted to 0x80000000 so it's necessary to use this macro in order to make the code EVA agnostic. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras2-10/+28
The 'ememsize' variable is used to denote the real RAM which is present on the Malta board. This is different compared to 'memsize' which is capped to 256MB. The 'ememsize' is used to get the actual physical memory when setting up the Malta memory layout. This only makes sense in case the core operates in the EVA mode, and it's ignored otherwise. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)Markos Chandras1-0/+46
Add a spaces.h file for Malta to override certain memory macros when operating in EVA mode. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras2-1/+112
The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000 - 0x7fffffff ignoring the 256 MB IO hole in 0x10000000. The physical memory is shifted to 0x80000000 so up to 2GB can be used. Kuseg is expanded to 3GB (due to board limitations only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB. The Segment Control registers are programmed as follows: Virtual memory Physical memory Mapping 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 0xc0000000 - 0xdfffffff - MK (kseg2) 0xe0000000 - 0xffffffff - MK (kseg3) The location of exception vectors remain the same since 0xbfc00000 (traditional exception base) still maps to 0x1fc00000 physical. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin1-0/+11
There is a chance for the secondary cache to have memory aliases. This can happen if the bootloader is in a non-EVA mode (or even in EVA mode but with different mapping from the kernel) and the kernel switching to EVA afterwards. It's best to flush the icache to avoid having the secondary CPUs fetching stale data from it. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras1-2/+4
Use the userspace cache flushing functions if the interrupted process is a userspace one. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin1-0/+47
Build EVA specific cache flushing functions (ie cachee). They will be used by a subsequent patch. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
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