aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-10-09drm/amd/display: Move stereo timing check to helperTaimur Hassan3-8/+19
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Split pipe for stereo timingsTaimur Hassan1-0/+11
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Use fixed DET Buffer SizeSung Joon Kim3-10/+16
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Handle multiple streams sourcing same surfaceSung Joon Kim3-32/+53
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Add z8_marks in dmlCharlene Liu5-0/+9
Add z8 watermarks to struct for later ASIC use. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Add DCN35 DML2 supportQingqing Zhuo5-7/+110
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Introduce DML2Qingqing Zhuo36-4/+19572
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Co-developed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guardRodrigo Siqueira1-1/+2
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move bw_fixed from DML folderRodrigo Siqueira3-10/+8
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move custom_float from DML folderRodrigo Siqueira3-59/+36
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move dce_calcs from DML folderRodrigo Siqueira4-2/+7
dce_calcs does not have FPU operations, and it is required for DCE and DCN. Remove this file from the DML folder and add it to the basic folder visible for DCE and DCN. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)Alex Deucher1-1/+16
When ROCm is active enable additional SMU 13.0.0 optimizations. This reuses the unused powersave profile on PMFW. v2: move to the swsmu code since we need both bits active in the workload mask. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move the memory allocation out of ↵Sebastian Andrzej Siewior3-13/+18
dcn20_validate_bandwidth_fp(). dcn20_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. To preserve previous "clean" state of "pipes" add a memset() before the second invocation of dcn20_validate_bandwidth_internal() where the variable is used. Acked-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move the memory allocation out of ↵Sebastian Andrzej Siewior3-9/+13
dcn21_validate_bandwidth_fp(). dcn21_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928 Acked-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Add a warning if the FPU is used outside from task context.Sebastian Andrzej Siewior1-0/+1
Add a warning if the FPU is used from any context other than task context. This is only precaution since the code is not able to be used from softirq while the API allows it on x86 for instance. Acked-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd: Fix UBSAN array-index-out-of-bounds for Polaris and TongaMario Limonciello1-6/+6
For pptable structs that use flexible array sizes, use flexible arrays. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742 Signed-off-by: Mario Limonciello <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/radeon: Fix UBSAN array-index-out-of-bounds for Radeon HD 5430Mario Limonciello1-1/+1
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by: Felix Held <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894 Signed-off-by: Mario Limonciello <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7Mario Limonciello2-4/+4
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by: Felix Held <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874 Signed-off-by: Mario Limonciello <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Annotate struct amdgpu_bo_list with __counted_byKees Cook2-2/+2
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct amdgpu_bo_list. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: "Gustavo A. R. Silva" <[email protected]> Cc: Luben Tuikov <[email protected]> Cc: Christophe JAILLET <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Link: https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci [1] Reviewed-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Kees Cook <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Drop unnecessary return statementsSrinivasan Shanmugam9-21/+0
There is no reason to call return at the end of function that returns void. Fixes the below: WARNING: void function return statements are not generally useful Thus remove such a statement in the affected functions. Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05Documentation/amdgpu: Add board info detailsLijo Lazar2-0/+22
Add documentation for board info sysfs attribute. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Add sysfs attribute to get board infoLijo Lazar1-0/+57
Add a sysfs attribute which shows the board form factor like OAM or CEM. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Get package types for smuio v13.0Lijo Lazar1-0/+22
Add support to query package types supported in smuio v13.0 ASICs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Add more smuio v13.0.3 package typesLijo Lazar1-0/+6
Expand support to get other board types like OAM or CEM. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: fix ip count query for xcp partitionsSathishkumar S1-8/+36
fix wrong ip count INFO on spatial partitions. update the query to return the instance count corresponding to the partition id. v2: initialize variables only when required to be (Christian) move variable declarations to the beginning of function (Christian) Signed-off-by: Sathishkumar S <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amd/pm: Remove set df cstate for SMUv13.0.6Asad Kamal1-8/+0
Remove set df cstate as disallow df state is not required for SMUv13.0.6 Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Move package type enum to amdgpu_smuioLijo Lazar2-5/+7
Move definition of package type to amdgpu_smuio header and add new package types for CEM and OAM. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: Fix complex macros errorSrinivasan Shanmugam4-5/+7
Fixes the below: ERROR: Macros with complex values should be enclosed in parentheses WARNING: macros should not use a trailing semicolon +#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdkfd: Use partial migrations in GPU page faultsXiaogang Chen4-85/+160
This patch implements partial migration in gpu page fault according to migration granularity(default 2MB) and not split svm range in cpu page fault handling. A svm range may include pages from both system ram and vram of one gpu now. These chagnes are expected to improve migration performance and reduce mmu callback and TLB flush workloads. Signed-off-by: Xiaogang Chen <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amd/display: Simplify the per-CPU usage.Sebastian Andrzej Siewior1-30/+20
The fpu_recursion_depth counter is used to ensure that dc_fpu_begin() can be invoked multiple times while the FPU-disable function itself is only invoked once. Also the counter part (dc_fpu_end()) is ballanced properly. Instead of using the get_cpu_ptr() dance around the inc it is simpler to increment the per-CPU variable directly. Also the per-CPU variable has to be incremented and decremented on the same CPU. This is ensured by the inner-part which disables preemption. This is kind of not obvious, works and the preempt-counter is touched a few times for no reason. Disable preemption before incrementing fpu_recursion_depth for the first time. Keep preemption disabled until dc_fpu_end() where the counter is decremented making it obvious that the preemption has to stay disabled while the counter is non-zero. Use simple inc/dec functions. Remove the nested preempt_disable/enable functions which are now not needed. Acked-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amd/display: Remove migrate_en/dis from dc_fpu_begin().Sebastian Andrzej Siewior1-2/+0
This is a revert of the commit mentioned below while it is not wrong, as in the kernel will explode, having migrate_disable() here it is complete waste of resources. Additionally commit message is plain wrong the review tag does not make it any better. The migrate_disable() interface has a fat comment describing it and it includes the word "undesired" in the headline which should tickle people to read it before using it. Initially I assumed it is worded too harsh but now I beg to differ. The reviewer of the original commit, even not understanding what migrate_disable() does should ask the following: - migrate_disable() is added only to the CONFIG_X86 block and it claims to protect fpu_recursion_depth. Why are the other the architectures excluded? - migrate_disable() is added after fpu_recursion_depth was modified. Shouldn't it be added before the modification or referencing takes place? Moving on. Disabling preemption DOES prevent CPU migration. A task, that can not be pushed away from the CPU by the scheduler (due to disabled preemption) can not be pushed or migrated to another CPU. Disabling migration DOES NOT ensure consistency of per-CPU variables. It only ensures that the task acts always on the same per-CPU variable. The task remains preemptible meaning multiple tasks can access the same per-CPU variable. This in turn leads to inconsistency for the statement *pcpu -= 1; with two tasks on one CPU and a preemption point during the RMW operation: Task A Task B read pcpu to reg # 0 inc reg # 0 -> 1 read pcpu to reg # 0 inc reg # 0 -> 1 write reg to pcpu # 1 write reg to pcpu # 1 At the end pcpu reads 1 but should read 2 instead. Boom. get_cpu_ptr() already contains a preempt_disable() statement. That means that the per-CPU variable can only be referenced by a single task which is currently running. The only inconsistency that can occur if the variable is additionally accessed from an interrupt. Remove migrate_disable/enable() from dc_fpu_begin/end(). Cc: Tianci Yin <[email protected]> Cc: Aurabindo Pillai <[email protected]> Fixes: 0c316556d124 ("drm/amd/display: Disable migration to ensure consistency of per-CPU variable") Acked-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: amdgpu_drm.h: fix comment typosRandy Dunlap1-2/+2
Correct typos of "occurred". Signed-off-by: Randy Dunlap <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: [email protected] Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: refine fault cache updatesAlex Deucher1-1/+6
Don't update the fault cache if status is 0. In the multiple fault case, subsequent faults will return a 0 status which is useless for userspace and replaces the useful fault status, so only update if status is non-0. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-05drm/amdgpu: add new INFO ioctl query for the last GPU page faultAlex Deucher5-5/+63
Add a interface to query the last GPU page fault for the process. Useful for debugging context lost errors. v2: split vmhub representation between kernel and userspace v3: add locking when fetching fault info in INFO IOCTL Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 libdrm MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 Cc: [email protected] Reviewed-by: Christian König <[email protected]> Acked-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/pm: Add GC v9.4.3 thermal limits to hwmonLijo Lazar1-7/+12
Publish max operating temperature of SOC and memory as temp*_emergency nodes in hwmon. temp*_crit will show the throttle temperature limits. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/pm: Add throttle limit for SMU v13.0.6Lijo Lazar1-7/+27
CTF limit represents the max operating temperature and thermal limit gives the limit at which throttling starts. Add support for both limits. SOC and HBM may have different limit values.*_emergency_max gives max operating temperature and *_crit_max value represents throttle limit. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: 3.2.254Aric Cyr1-1/+1
DC v3.2.254 * Stability fixes through null pointer checks, blackscreen fixes on certain configurations * Improvements for various functionality like Idle optimization, ILR, DSC, IPS * Fixes for ILR functionality * Trivial code cleanups =================================================================== Acked-by: Aurabindo Pillai <[email protected]> Cc: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Adjust code style for hw_sequencer.hAurabindo Pillai8-102/+23
[Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Adjust code style for dmub_cmd.hAurabindo Pillai1-81/+81
[Why&How] Make some formatting changes and rearranging of definitions for consistency. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Update DMUB cmd headerAurabindo Pillai1-3/+28
[Why&How] * Add hints about the bits used in the packed struct. * Update new bitfields for ABM and IPS Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Add a check for idle power optimizationSung Joon Kim3-1/+21
[why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. Signed-off-by: Sung Joon Kim <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: use full update for clip size increase of large plane sourceWenjing Liu2-2/+15
[why] Clip size increase will increase viewport, which could cause us to switch to MPC combine. If we skip full update, we are not able to change to MPC combine in fast update. This will cause corruption showing on the video plane. [how] treat clip size increase of a surface larger than 5k as a full update. Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Clean up code warningsAric Cyr1-1/+1
- Fix constness of string parameters - Fix zero-initialization of structs which cannot take a 0 literal as the first field, for example enums Reviewed-by: Dillon Varone <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: Make driver backwards-compatible with non-IPS PMFWOvidiu Bunea3-12/+19
[why] Driver needs to be compatible with PM FW that doesn't support IPS [how] Toggle internal control flag Reviewed-by: Charlene Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: refactor ILR to make it workSherry Wang4-12/+31
[Why] Current ILR toggle is on/off as a part of panel config for new function, which breaks original ILR logic [How] Refactor ILR and take panel config into account Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Sherry Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: remove duplicated edp relink to fastbootChiawen Huang1-59/+0
[Why&How] enable_accelerated_mode function is fully to check whether fastboot support or not. It is no longer to disable_vbios_mode_if_required. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Chiawen Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: apply edge-case DISPCLK WDIVIDER changes to master OTG ↵Samson Tam2-4/+4
pipes only [Why] The edge-case DISPCLK WDIVIDER changes call stream_enc functions. But with MPC pipes, downstream pipes have null stream_enc and will cause crash. [How] Only call stream_enc functions for pipes that are OTG master. Reviewed-by: Alvin Lee <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amd/display: enable dsc_clk even if dsc_pg disabledMuhammad Ahmed3-5/+8
[why] need to enable dsc_clk regardless dsc_pg Reviewed-by: Charlene Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amdkfd: Fix EXT_COHERENT memory allocation crashPhilip Yang1-11/+7
If there is no VRAM domain, bo_node is NULL and this causes crash. Refactor the change, and use the module parameter as higher privilege. Need another patch to support override PTE flag on APU. Fixes: 5f248462c69d ("drm/amdgpu: Add EXT_COHERENT memory allocation flags") Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-04drm/amdgpu: ratelimited override pte flags messagesPhilip Yang2-16/+10
Use ratelimited version of dev_dbg to avoid flooding dmesg log. No functional change. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.