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2022-10-10drm/amd/display: Use set_vtotal_min_max to configure OTG VTOTALRodrigo Siqueira4-20/+5
In multiple parts of the DCN code, we write directly to the OTG_V_TOTAL_* registers in some OPTC functions. Let's avoid it by using the set_vtotal_min_max. Tested-by: Daniel Wheeler <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Add a missing hook to DCN20Rodrigo Siqueira1-0/+1
The struct timing_generator_funcs provides a hook for setting up the maximum possible vertical dimension of display for OTG, as the panel supports. DCN10 has a standard function named optc1_set_vtotal_min_max which all ASICs can use to set the aforementioned hook. Since we did not set it for DCN20, this commit initializes the set_vtotal_min_max with the DCN10 function. Tested-by: Daniel Wheeler <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: always allow pstate change when no dpps are active on dcn315Dmytro Laktyushkin1-3/+6
Prevents certain configs blocking s0i3 when streams aren't completely removed Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Display does not light up after S4 resumeMeenakshikumar Somasundaram5-1/+56
[Why] Dpia hpd interrupt processing is disabled when entering S4/S0i3 and would be reenabled after detection completes during resuming. Because, keeping hpd interrupts enabled during detection leads to multiple detections for the same hpd transition. There is a S4 case where dpia hpd interrupt is missed when driver is in transitioning from hpd interrupt processing disable to enable and the display does not light up. [How] - Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt is disabled, dmub will keep the hpd pending and post it once driver reenables dpia hpd interrupt or when querying with DMUB_CMD__QUERY_HPD_STATE. - Added dmub boot option dpia_hpd_int_enable_supported to notify dmub about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Mustapha Ghaddar <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Use the same cursor info across featuresMax Tseng11-148/+400
Since different features would need to update cursor registers, However, they would use different approaches. To unify varied methods, this refactor is implemented the same update cursor info method for current varied features. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Max Tseng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Fix bug preventing FCLK Pstate allow message being sentDillon Varone1-2/+2
[Why & How] FCLK pstate allow message should not be dependent on local "update_fclk". Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone2-15/+41
[Why & How] Acquire FCLK DPM levels to properly construct DML clock limits. Further add new logic to keep number of indices for each clock in clk_mgr. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Validate DSC After Enable All New CRTCsFangzhi Zuo1-4/+9
Before enabling new crtc, stream_count in dc_state does not sync with that in drm_atomic_state. Validating dsc in such case would leave newly added stream not jointly participating in dsc optimization with existing streams, but simply using default initialized vcpi all the time which gives wrong dsc determination decision. Consider the scenaio where one 4k60 connected to the dock under dp-alt mode. Since dp-alt mode is 2-lane setup, stream 1 consumes 63 slots with dsc needed. Then hook up a second 4k60 to the dock. stream 2 connected with 65 slot initialized by default without dsc. dsc pre validate will not jointly optimize stream 2 with stream 1 before crtc 2 added into the dc_state. That leads to stream 2 not getting dsc optimization, and trigger atomic_check failure all the time, as 65 > 63 limit. After getting all new crtcs added into the state, stream_count in dc_state correctly reflect that in drm_atomic_state which comes up with correct dsc decision. Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic check") Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Mark Broadworth <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-10-10drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resourcesJun Lei5-2/+61
[Why & How] Add a helper to map ODM/MPC/Multi-Plane resources from DC Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Jun Lei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: increase hardware status wait timeVladimir Stempen2-3/+3
[Why] Diagnostics reports exceptions generated when timeout waiting for DISPCLK frequency divider change expires when testing ODM4to1. Diagnostics reports exceptions generated when timeout waiting for OTG busy status expires when disabling OTG during ODM4to1 test. [How] Increase HW status waiting time for DISPCLK frequency divider change and OTG busy status when disable OTG. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Ariel Bernstein <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Vladimir Stempen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Do not trigger timing sync for phantom pipesAurabindo Pillai1-3/+23
[Why&How] Doing timing sync seqence for phantom pipes will not go through since they are not fully programmed like normal pipes. Skip the sequence on such pipes Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Use correct pixel clock to program DTBCLK DTO'sDillon Varone1-1/+1
[Why?] Currently phy_pix_clk is used to program DTO's which is incorrect. [How?] Use the timing pixel clock to program DTO's correctly. Reviewed-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: do not compare integers of different widthsJosip Pavic1-2/+1
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Josip Pavic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: zeromem mypipe heap struct before using itMartin Leung1-0/+2
[Why & How] bug was caused when moving variable from stack to heap because it was reusable and garbage was left over, so we need to zero mem Fixes: 7acc487ab57e ("drm/amd/display: reduce stack size in dcn32 dml (v2)") Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Martin Leung <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-10-10drm/amd/display: properly configure DCFCLK when enable/disable FreesyncVladimir Stempen2-1/+13
[Why] Bandwidth validation is using Freesync parameters from previous Freesync state. Bandwidth validation ignores DCFCLK calculated after Freesync parameters are configured [How] Set Freesync bandwidth parameters to its default state before running bandwidth validation. Take DCFCLK calculated after Freesync bandwidth parameters are assigned and bandwidth is recalculated. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Vladimir Stempen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10Revert "drm/amd/display: skip commit minimal transition state"Dillon Varone1-20/+0
This reverts commit e4e481e4d838f30985dd46d43ed195110ed265f5. [Why & How] The reverted commit creates memory leak and causes issue upon driver install. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-10drm/amd/display: Update PMFW z-state interface for DCN314Nicholas Kazlauskas2-9/+5
[Why] Request from PMFW to change the messaging format to specify whether we support z-state via individual bits. [How] Update the args we pass in the support message. Fixes: d5c6909e7460 ("drm/amd/display: Add DCN314 clock manager") Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0
2022-10-10drm/amd/display: explicitly disable psr_feature_enable appropriatelyShirish S1-2/+6
[Why] If psr_feature_enable is set to true by default, it continues to be enabled for non capable links. [How] explicitly disable the feature on links that are not capable of the same. Fixes: 8c322309e48e9 ("drm/amd/display: Enable PSR") Signed-off-by: Shirish S <[email protected]> Reviewed-by: Leo Li <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.15+
2022-10-06Revert "drm/amdgpu: use dirty framebuffer helper"Hamza Mahfooz1-12/+2
This reverts commit 66f99628eb24409cb8feb5061f78283c8b65f820. Unfortunately, that commit causes performance regressions on non-PSR setups. So, just revert it until FB_DAMAGE_CLIPS support can be added. Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2189 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216554 Fixes: 66f99628eb2440 ("drm/amdgpu: use dirty framebuffer helper") Fixes: abbc7a3dafb91b ("drm/amdgpu: don't register a dirty callback for non-atomic") Signed-off-by: Hamza Mahfooz <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amdgpu: Correct amdgpu_amdkfd_total_mem_size calculationPhilip Yang1-3/+3
amdkfd_total_mem_size is the size of total GPUs vram plus system memory to estimate page tables memory usage and leave enough VRAM room for page tables allocation. Calculate amdkfd_total_mem_size in amdgpu_amdkfd_device_probe is incorrect because adev->gmc.real_vram_size is still 0 called from amdgpu_device_ip_early_init. Move the calculation to amdgpu_amdkfd_device_init to get the correct VRAM size. Do reverse calculation in amdgpu_amdkfd_device_fini_sw to support hot-unplugging GPUs. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amdgpu: Set vmbo destroy after pt bo is createdPhilip Yang1-1/+4
Under VRAM usage pression, map to GPU may fail to create pt bo and vmbo->shadow_list is not initialized, then ttm_bo_release calling amdgpu_bo_vm_destroy to access vmbo->shadow_list generates below dmesg and NULL pointer access backtrace: Set vmbo destroy callback to amdgpu_bo_vm_destroy only after creating pt bo successfully, otherwise use default callback amdgpu_bo_destroy. amdgpu: amdgpu_vm_bo_update failed amdgpu: update_gpuvm_pte() failed amdgpu: Failed to map bo to gpuvm amdgpu 0000:43:00.0: amdgpu: Failed to map peer:0000:43:00.0 mem_domain:2 BUG: kernel NULL pointer dereference, address: RIP: 0010:amdgpu_bo_vm_destroy+0x4d/0x80 [amdgpu] Call Trace: <TASK> ttm_bo_release+0x207/0x320 [amdttm] amdttm_bo_init_reserved+0x1d6/0x210 [amdttm] amdgpu_bo_create+0x1ba/0x520 [amdgpu] amdgpu_bo_create_vm+0x3a/0x80 [amdgpu] amdgpu_vm_pt_create+0xde/0x270 [amdgpu] amdgpu_vm_ptes_update+0x63b/0x710 [amdgpu] amdgpu_vm_update_range+0x2e7/0x6e0 [amdgpu] amdgpu_vm_bo_update+0x2bd/0x600 [amdgpu] update_gpuvm_pte+0x160/0x420 [amdgpu] amdgpu_amdkfd_gpuvm_map_memory_to_gpu+0x313/0x1130 [amdgpu] kfd_ioctl_map_memory_to_gpu+0x115/0x390 [amdgpu] kfd_ioctl+0x24a/0x5b0 [amdgpu] Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amdgpu: Fix VRAM BO swap issueArunpravin Paneer Selvam1-5/+12
DRM buddy manager allocates the contiguous memory requests in a single block or multiple blocks. So for the ttm move operation (incase of low vram memory) we should consider all the blocks to compute the total memory size which compared with the struct ttm_resource num_pages in order to verify that the blocks are contiguous for the eviction process. v2: Added a Fixes tag v3: Rewrite the code to save a bit of calculations and variables (Christian) Fixes: c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu") Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Remove unused struct i2c_id_config_accessYuan Can1-7/+0
After commit 5a8132b9f606 ("drm/amd/display: remove dead dc vbios code"), no one use struct i2c_id_config_access, so remove it. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Yuan Can <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Removed unused variable 'sdp_stream_enable'Dong Chenchen1-10/+6
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c: In function 'dcn31_hpo_dp_stream_enc_update_dp_info_packets': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c:439:14: warning: variable 'sdp_stream_enable' set but not used [-Wunused-but-set-variable] 439 | bool sdp_stream_enable = false; Removed unused variable 'sdp_stream_enable'. Reviewed-by: Rodrigo Siqueira <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Dong Chenchen <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: clean up dcn32_fpu.c kernel-docRandy Dunlap1-67/+49
Rectify multiple kernel-doc warnings in dcn32_fpu.c. E.g.: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:247: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Finds dummy_latency_index when MCLK switching using firmware based drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:484: warning: Function parameter or member 'phantom_stream' not described in 'dcn32_set_phantom_stream_timing' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'dc' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'context' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'index' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: Function parameter or member 'dc' not described in 'dcn32_update_bw_bounding_box_fpu' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: Function parameter or member 'bw_params' not described in 'dcn32_update_bw_bounding_box_fpu' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: expecting prototype for dcn32_update_bw_bounding_box(). Prototype was for dcn32_update_bw_bounding_box_fpu() instead Reviewed-by: Rodrigo Siqueira <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Randy Dunlap <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Cc: George Shen <[email protected]> Cc: Alvin Lee <[email protected]> Cc: Nevenko Stupar <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Fix vblank refcount in vrr transitionYunxiang Li1-29/+26
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on which causes drm_crtc_vblank_get in vrr_transition to fail, and later when drm_crtc_vblank_put is called the refcount on vblank will be messed up. Therefore move the call to after manage_dm_interrupts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1247 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1380 Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Yunxiang Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-10-06drm/amd/display: Enable dpia support for dcn314Roman Li1-1/+2
[Why] DCN 3.1.4 supports DPIA. [How] - Set dpia_supported flag for dcn314 in dmub_hw_init() - Remove comment that becomes irrelevant after this change. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-10-06drm/amdgpu: Enable F32_WPTR_POLL_ENABLE in mqdRuili Ji2-2/+4
This patch is to fix the SDMA user queue doorbell missing issue on SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is used. Otherwise ringing SDMA user queue doorbell can't wake up system from gfxoff. Signed-off-by: Ruili Ji <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-10-06drm/amdgpu/sdma: add missing release_firmware() in amdgpu_sdma_init_microcode()Yang Yingliang1-3/+5
In some error path in amdgpu_sdma_init_microcode(), release_firmware() is not called, the memory allocated in request_firmware() will be leaked, calling amdgpu_sdma_destroy_inst_ctx() which calls release_firmware() to avoid memory leak. Fixes: 15aa13056d11da ("drm/amdgpu: add function to init SDMA microcode") Signed-off-by: Yang Yingliang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: clean up one inconsistent indentingYang Li1-1/+1
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2321 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: clean up one inconsistent indentingYang Li1-1/+1
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2238 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Minor code style changeRodrigo Siqueira1-7/+2
This commit adds some minor code style changes just to reduce the merge conflicts we have when we upstream some of the VBA code. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: update DSC for DCN32Rodrigo Siqueira1-6/+4
Update DSC checks in the DCN32 VBA. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Disconnect DSC for unused pipes during ODM transitionRodrigo Siqueira1-8/+11
[Why] During transition from ODM combine to ODM bypass, if DSC is enabled need to disconnect the DSC mux for pipes no longer in use. [How] During ODM update, detect pipes with DSC that are no longer being used for new state and call new DSC interface to disconnect. Add new DSC interface to disconnect from pipe Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: unblock mcm_lutsMartin Leung1-3/+2
why and how: needed to fix bad assumption for enable mcm_luts Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: 3.2.206Aric Cyr1-1/+1
This version brings along the following: - ILR improvements - PSR fixes - DCN315 fixes - DCN32 fixes - ODM fixes - DSC fixes - SubVP fixes Reviewed-by: Hamza Mahfooz <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Enable 2 to 1 ODM policy if supportedRodrigo Siqueira1-0/+4
If the current configuration supports 2 to 1 ODM policy, let's also enable the windowed MPO feature. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-10-06drm/amd/display: Add PState change high hook for DCN32Rodrigo Siqueira1-0/+1
For some reason, we missed the PState check for DCN32 which may cause issues for clock transition. This commit add that required hook. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amdgpu: Enable VCN PG on GC11_0_1Sonny Jiang1-0/+1
Enable VCN PG on GC11_0_1 Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-10-06drm/amd/display: Add missing mask sh for SYM32_TP_SQ_PULSE registerWenjing Liu1-0/+1
There is a missing register mask in dcn32 causing the hardware programming is not executed when programming SQ_num test pattern for DP2. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Add missing SDP registers to DCN32 reglistGeorge Shen1-0/+2
[Why] Certain features require the additional DP SDP configuration registers DP_SEC_CNTL1 and DP_SEC_CNTL5 in order to function correctly. The DCN32 DIO stream encoder reglist is currently missing these two registers. [How] Add the missing registers to the DCN32 DIO stream encoder reglist. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Fix disable DSC logic in the DIO codeEric Bernstein1-1/+1
[Why] In DIO stream encoder, definition of DP_DSC_MODE is changed (only enable/disable) In OPTC, OTG_SET_V_TOTAL_MIN_MASK_EN is removed (same as DCN3.1) [How] In DIO stream encoder, update enc32_dp_set_dsc_config(). In OPTC, use DCN3.1 version for function interfaces .set_vrr_m_const and .set_drr Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Fix merging dynamic ODM+MPO configs on DCN32Dillon Varone1-0/+5
[WHY&HOW?] When merging ODM pipes that are using MPO, we must copy the stream_res from the new top pipe to the bottom pipe so that the overlayed plane is not pointing to the wrong stream assets. Reviewed-by: Martin Leung <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Adding missing HDMI ACP SEND registerRodrigo Siqueira1-0/+1
Add HDMI ACP bit field definition for DCN32. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Remove OPTC lock checkRodrigo Siqueira6-16/+0
At some point, we decided to blank HUBP during pixel data blank, and to handle that, we added some OPTC lock checks. Later, we realized that this change caused multiple regression, and we removed it. Nevertheless, we still have some leftovers that might affect some ASIC behavior, and this commit drops those changes to keep the code consistent. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Fix SubVP control flow in the MPO contextRodrigo Siqueira3-20/+20
SubVP has some issues related to how we allocate and enable it. This commit fixes this behavior by adding the proper check and configuration to the SubVP code path. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Update DCN321 hook that deals with pipe aquireRodrigo Siqueira1-1/+1
DCN provides a hook to check if we can have a new pipe allocation based on some DC constraints. If the current configuration supports the new pipe request, DC updates its context; otherwise, it will keep the same configuration. This behavior is similar across multiple ASICs, and for this reason, we reused DCN20 on DCN321. However, this DCN32x has some peculiarities which require its function to avoid weird pipe split issues. This commit update this issue by using dcn32_acquire_idle_pipe_for_head_pipe_in_layer instead of dcn20_acquire_idle_pipe_for_layer. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Drop unused code for DCN32/321Rodrigo Siqueira6-36/+1
Under DCN32/321 we identified some code paths that DC never executes. This commit removes those unused codes to avoid distractions when debugging issues. Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: block odd h_total timings from halving pixel rateMartin Leung2-5/+39
why: when dynamic odm was turned on, there is also logic to halve the pixelclk this still turned on when we avoided odm in the case of odd h_total timings how: block the pixel clk mechanism also in the case of odd h_total timings Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-06drm/amd/display: Fix vupdate and vline position calculationAric Cyr1-35/+25
[how] Large deltas for periodic interrupts could result in the interrupt not being programmed properly and thus not firing. [why] Add proper wrap-around support for calculating VUPDATE and VLINE positions. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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