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2018-09-26drm/amdgpu: Enable BAD_OPCODE intr for gfx8Harish Kasiviswanathan1-1/+2
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in response to bad opcodes in a CP queue. Signed-off-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: KFD doesn't support TONGA SRIOVEmily Deng1-16/+0
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV environment, it will let compute ring IB test fail. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Shaoyun.liu <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: reflect atomic support in IO link propertiesEric Huang3-12/+39
Add the flags of properties according to Asic type and pcie capabilities. Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Add warning message for INT SW fallback.Andrey Grodzovsky1-0/+1
Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26Revert "drm/amdgpu: remove fence fallback"Andrey Grodzovsky3-0/+58
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:No action when VCN PG state is unchangedJames Zhu2-2/+11
When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: remove redundant null pointer check before kfreezhong jiang1-6/+2
kfree has taken the null pointer into account. hence it is safe to remove the redundant null pointer check before kfree. Signed-off-by: zhong jiang <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: print smc feature mask in debugfs amdgpu_pm_infoAlex Deucher1-0/+5
Print the enabled smc feature mask in amdgpu_pm_info for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega20Alex Deucher1-0/+5
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega12Alex Deucher1-1/+5
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega10Alex Deucher3-4/+11
So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: add new AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK sensorAlex Deucher1-0/+1
For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20Alex Deucher3-24/+34
For consistency with other asics. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12Alex Deucher3-12/+22
For consistency with other asics. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: Move vega10_enable_smc_featuresAlex Deucher6-12/+15
to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/powerplay: add get_argument callback for vega20Alex Deucher4-32/+15
For consistency with other vega parts. Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Raise dispclk value for dce120 by 15%Nicholas Kazlauskas1-0/+3
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by: Nick Sarnie <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: fix gamma not being appliedSivapiriyanKumarasamy1-5/+14
[WHY] Previously night light forced a full update by applying a transfer function update regardless of if it was changed. This logic was removed, Now gamma surface updates are only applied when there is also a plane info update, this does not work in cases such as using the night light slider. [HOW] When moving the night light slider we will perform a full update if the gamma has changed and there is a surface, even when the surface has not changed. Also get stream updates in setgamma prior to update planes and stream. Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Remove mst_hotplug_workLeo Li2-12/+0
[Why] The work struct's schedule call was removed a while ago, making this useless. [How] Remove it. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Guard against null stream dereference in do flipNicholas Kazlauskas1-1/+14
[Why] During suspend under some hardware configurations can result in a series of atomic commits with a NULL stream status - which causes a NULL pointer dereference. This should be guarded. [How] Exit early from the function - if we can't access the stream then there isn't anything that can be done here. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Stereo 3D support in VSCEric Bernstein1-4/+54
[Why] Need to add strere 3D information in VSC [How] Update mod_build_vsc_infopacket with stereo info Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: dc 3.1.67Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Steven Chiu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: program v_update and v_ready with proper fieldSu Sung Chung3-13/+13
[WHY] There are two different variables used to calculate v_update and v_ready, one for validation and the other for performance parameter calculation. Before the variable for validation was used which caused underflow on 1080edp with vsr enabled [HOW] program v_update and v_ready with the variables for performance parameter calculation Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Add color bit info to freesync infoframeSivapiriyanKumarasamy4-21/+198
Parse the native color bit and send it to freesync module for future use Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: add pp_smu NULL pointer checkCharlene Liu1-1/+1
add pp_smu NULL ptr check Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: use proper pipe_ctx indexSamson Tam1-2/+18
Use link->link_index as index to pipe_ctx[] to get proper link information instead of using index 0 to avoid potential miss matches. Signed-off-by: Samson Tam <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: Refactor FPGA-specific link setupNikola Cornij3-40/+32
FPGA doesn't program backend, so we don't need certain link settings (audio stream for example). Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Return error immediately if load firmware failedRex Zhu1-4/+6
this can avoid hard hang and be useful for debug. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Honour DC's clock limits on RvRex Zhu1-8/+17
Honour display's request for min engine clock/memory clock. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/dc: Trigger set power state task when display configuration changesRex Zhu1-0/+2
Revert "drm/amd/display: Remove call to amdgpu_pm_compute_clocks" This reverts commit dcd473770e86517543691bdb227103d6c781cd0a. when display configuration changes, dc need to update the changes to powerplay, also need to trigger a power state task. amdgpu_pm_compute_clocks is the interface to set power state task either dpm enabled or powerplay enabled Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-27BackMerge v4.19-rc5 into drm-nextDave Airlie805-4518/+8350
Sean Paul requested an -rc5 backmerge from some sun4i fixes. Signed-off-by: Dave Airlie <[email protected]>
2018-09-27Merge tag 'drm-hisilicon-next-2018-09-26' of github.com:xin3liang/linux into ↵Dave Airlie5-27/+12
drm-next - A crash fix founded in recent linux-next from John Garry - One sparse warning fix from Souptick Joarder - Some xxx_unref cleanup from Thomas Zimmermann Signed-off-by: Dave Airlie <[email protected]> From: Xinliang Liu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAGd==04mXPMjVZ3=cM8r+DSQNM6zy7Anc4T2OsHjZgSsazBTPQ@mail.gmail.com
2018-09-27Merge tag 'du-next-20180925' of git://linuxtv.org/pinchartl/media into drm-nextDave Airlie11-147/+595
R-Car DU support for the D3 and E3 SoCs (v4.20) Signed-off-by: Dave Airlie <[email protected]> From: Laurent Pinchart <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/3289904.RCOHkcp7u8@avalon
2018-09-26drm/hisilicon: Replace ttm_bo_unref with ttm_bo_putThomas Zimmermann1-1/+1
The function ttm_bo_put releases a reference to a TTM buffer object. The function's name is more aligned to the Linux kernel convention of naming ref-counting function _get and _put. A call to ttm_bo_unref takes the address of the TTM BO object's pointer and clears the pointer's value to NULL. This is not necessary in most cases and sometimes even worked around by the calling code. A call to ttm_bo_put only releases the reference without clearing the pointer. The current behaviour of cleaning the pointer is kept in the calling code, but should be removed if not required in a later patch. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-26drm/hisilicon: Replace drm_dev_unref with drm_dev_putThomas Zimmermann2-6/+6
This patch unifies the naming of DRM functions for reference counting of struct drm_device. The resulting code is more aligned with the rest of the Linux kernel interfaces. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-26gpu/drm/hisilicon: Convert drm_atomic_helper_suspend/resume()Souptick Joarder2-18/+3
convert drm_atomic_helper_suspend/resume() to use drm_mode_config_helper_suspend/resume(). Fixed one sparse warning by making hibmc_drm_interrupt static. Signed-off-by: Ajit Negi <[email protected]> Signed-off-by: Souptick Joarder <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-26drm/hisilicon: hibmc: Use HUAWEI PCI vendor ID macroJohn Garry1-1/+1
Switch to use Huawei PCI vendor ID macro from pci_ids.h file. In addition, switch to use PCI_VDEVICE() instead of open coding. Signed-off-by: John Garry <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-26drm/hisilicon: hibmc: Don't overwrite fb helper surface depthJohn Garry1-1/+0
Currently the driver overwrites the surface depth provided by the fb helper to give an invalid bpp/surface depth combination. This has been exposed by commit 70109354fed2 ("drm: Reject unknown legacy bpp and depth for drm_mode_addfb ioctl"), which now causes the driver to fail to probe. Fix by not overwriting the surface depth. Fixes: d1667b86795a ("drm/hisilicon/hibmc: Add support for frame buffer") Signed-off-by: John Garry <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-26drm/hisilicon: hibmc: Do not carry error code in HiBMC framebuffer pointerJohn Garry1-0/+1
In hibmc_drm_fb_create(), when the call to hibmc_framebuffer_init() fails with error, do not store the error code in the HiBMC device frame-buffer pointer, as this will be later checked for non-zero value in hibmc_fbdev_destroy() when our intention is to check for a valid function pointer. This fixes the following crash: [ 9.699791] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001a [ 9.708672] Mem abort info: [ 9.711489] ESR = 0x96000004 [ 9.714570] Exception class = DABT (current EL), IL = 32 bits [ 9.720551] SET = 0, FnV = 0 [ 9.723631] EA = 0, S1PTW = 0 [ 9.726799] Data abort info: [ 9.729702] ISV = 0, ISS = 0x00000004 [ 9.733573] CM = 0, WnR = 0 [ 9.736566] [000000000000001a] user address but active_mm is swapper [ 9.742987] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 9.748614] Modules linked in: [ 9.751694] CPU: 16 PID: 293 Comm: kworker/16:1 Tainted: G W 4.19.0-rc4-next-20180920-00001-g9b0012c #322 [ 9.762681] Hardware name: Huawei Taishan 2280 /D05, BIOS Hisilicon D05 IT21 Nemo 2.0 RC0 04/18/2018 [ 9.771915] Workqueue: events work_for_cpu_fn [ 9.776312] pstate: 60000005 (nZCv daif -PAN -UAO) [ 9.781150] pc : drm_mode_object_put+0x0/0x20 [ 9.785547] lr : hibmc_fbdev_fini+0x40/0x58 [ 9.789767] sp : ffff00000af1bcf0 [ 9.793108] x29: ffff00000af1bcf0 x28: 0000000000000000 [ 9.798473] x27: 0000000000000000 x26: ffff000008f66630 [ 9.803838] x25: 0000000000000000 x24: ffff0000095abb98 [ 9.809203] x23: ffff8017db92fe00 x22: ffff8017d2b13000 [ 9.814568] x21: ffffffffffffffea x20: ffff8017d2f80018 [ 9.819933] x19: ffff8017d28a0018 x18: ffffffffffffffff [ 9.825297] x17: 0000000000000000 x16: 0000000000000000 [ 9.830662] x15: ffff0000092296c8 x14: ffff00008939970f [ 9.836026] x13: ffff00000939971d x12: ffff000009229940 [ 9.841391] x11: ffff0000085f8fc0 x10: ffff00000af1b9a0 [ 9.846756] x9 : 000000000000000d x8 : 6620657a696c6169 [ 9.852121] x7 : ffff8017d3340580 x6 : ffff8017d4168000 [ 9.857486] x5 : 0000000000000000 x4 : ffff8017db92fb20 [ 9.862850] x3 : 0000000000002690 x2 : ffff8017d3340480 [ 9.868214] x1 : 0000000000000028 x0 : 0000000000000002 [ 9.873580] Process kworker/16:1 (pid: 293, stack limit = 0x(____ptrval____)) [ 9.880788] Call trace: [ 9.883252] drm_mode_object_put+0x0/0x20 [ 9.887297] hibmc_unload+0x1c/0x80 [ 9.890815] hibmc_pci_probe+0x170/0x3c8 [ 9.894773] local_pci_probe+0x3c/0xb0 [ 9.898555] work_for_cpu_fn+0x18/0x28 [ 9.902337] process_one_work+0x1e0/0x318 [ 9.906382] worker_thread+0x228/0x450 [ 9.910164] kthread+0x128/0x130 [ 9.913418] ret_from_fork+0x10/0x18 [ 9.917024] Code: a94153f3 a8c27bfd d65f03c0 d503201f (f9400c01) [ 9.923180] ---[ end trace 2695ffa0af5be375 ]--- Fixes: d1667b86795a ("drm/hisilicon/hibmc: Add support for frame buffer") Signed-off-by: John Garry <[email protected]> Reviewed-by: Xinliang Liu <[email protected]> Signed-off-by: Xinliang Liu <[email protected]>
2018-09-25drm: rcar-du: Add r8a77990 and r8a77995 device supportUlrich Hecht1-0/+30
Add support for the R-Car D3 (R8A77995) and E3 (R8A77990) SoCs to the R-Car DU driver. The two SoCs instantiate compatible DUs, so a single information structure is enough. Signed-off-by: Ulrich Hecht <[email protected]> [Add support for R8A77990] Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2018-09-25drm: rcar-du: Don't use TV sync mode when not supported by the hardwareLaurent Pinchart3-12/+29
The official way to stop the display is to clear the display enable (DEN) bit in the DSYSR register, but that operates at a group level and affects the two channels in the group. To disable channels selectively, the driver uses TV sync mode that stops display operation on the channel and turns output signals into inputs. While TV sync mode is available in all DU models currently supported, the D3 and E3 DUs don't support it. We will thus need to find an alternative way to turn channels off. In the meantime, condition the switch to TV sync mode to the availability of the feature, to avoid writing an invalid value to the DSYSR register. When the feature is unavailable the display output will turn blank as all planes are disabled when stopping the CRTC. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2018-09-25drm: rcar-du: Cache DSYSR value to ensure known initial valueLaurent Pinchart3-11/+17
DSYSR is a DU channel register that also contains group fields. It is thus written to by both the group and CRTC code, using read-update-write sequences. As the register isn't initialized explicitly at startup time, this can lead to invalid or otherwise unexpected values being written to some of the fields if they have been modified by the firmware or just not reset properly. To fix this we can write a fully known value to the DSYSR register when turning a channel's functional clock on. However, the mix of group and channel fields complicate this. A simpler solution is to cache the register and initialize the cached value to the desired hardware defaults. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2018-09-25drm: rcar-du: Enable configurable DPAD0 routing on Gen3Laurent Pinchart2-11/+18
All Gen3 SoCs supported so far have a fixed association between DPAD0 and DU channels, which led to hardcoding that association when writing the corresponding hardware register. The D3 and E3 will break that mechanism as DPAD0 can be dynamically connected to either DU0 or DU1. Make DPAD0 routing dynamic on Gen3. To ensure a valid hardware configuration when the DU starts without the RGB output enabled, DPAD0 is associated at initialization time to the first DU channel that it can be connected to. This makes no change on Gen2 as all Gen2 SoCs can connected DPAD0 to DU0, which is the current implicit default value. As the DPAD0 source is always 0 when a single source is possible on Gen2, we can also simplify the Gen2 code in the same function to remove a conditional check. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]>
2018-09-25drm: rcar-du: Use LVDS PLL clock as dot clock when possibleLaurent Pinchart3-15/+59
On selected SoCs, the DU can use the clock output by the LVDS encoder PLL as its input dot clock. This feature is optional, but on the D3 and E3 SoC it is often the only way to obtain a precise dot clock frequency, as the other available clocks (CPG-generated clock and external clock) usually have fixed rates. Add a DU model information field to describe which DU channels can use the LVDS PLL output clock as their input clock, and configure clock routing accordingly. This feature is available on H2, M2-W, M2-N, D3 and E3 SoCs, with D3 and E3 being the primary targets. It is left disabled in this commit, and will be enabled per-SoC after careful testing. At the hardware level, clock routing is configured at runtime in two steps, first selecting an internal dot clock between the LVDS PLL clock and the external DOTCLKIN clock, and then selecting between the internal dot clock and the CPG-generated clock. The first part requires stopping the whole DU group in order for the change to take effect, thus causing flickering on the screen. For this reason we currently hardcode the clock source to the LVDS PLL clock if available, and allow flicker-free selection of the external DOTCLKIN clock or CPG-generated clock otherwise. A more dynamic clock selection process can be implemented later if the need arises. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]>
2018-09-25drm: rcar-du: Perform the initial CRTC setup from rcar_du_crtc_get()Laurent Pinchart1-51/+56
The rcar_du_crtc_get() function is always immediately followed by a call to rcar_du_crtc_setup(). Call the later from the former to simplify the code, and add a comment to explain how the get and put calls are balanced. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]>
2018-09-25drm: rcar-du: lvds: D3/E3 supportLaurent Pinchart2-47/+355
The LVDS encoders in the D3 and E3 SoCs differ significantly from those in the other R-Car Gen3 family members: - The LVDS PLL architecture is more complex and requires computing PLL parameters manually. - The PLL uses external clocks as inputs, which need to be retrieved from DT. - In addition to the different PLL setup, the startup sequence has changed *again* (seems someone had trouble making his/her mind). Supporting all this requires DT bindings extensions for external clocks, brand new PLL setup code, and a few quirks to handle the differences in the startup sequence. The implementation doesn't support all hardware features yet, namely - Using the LV[01] clocks generated by the CPG as PLL input. - Providing the LVDS PLL clock to the DU for use with the RGB output. Those features can be added later when the need will arise. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Jacopo Mondi <[email protected]> Reviewed-by: Ulrich Hecht <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]>
2018-09-25drm: bridge: thc63: Restrict modes based on hardware operating frequencyLaurent Pinchart1-0/+18
The THC63LVD1024 is restricted to a pixel clock frequency in the range of 8 to 135 MHz. Implement the bridge .mode_valid() operation accordingly. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Tested-by: Jacopo Mondi <[email protected]>
2018-09-25dt-bindings: display: renesas: lvds: Add EXTAL and DU_DOTCLKIN clocksLaurent Pinchart1-1/+11
On the D3 and E3 SoCs, the LVDS encoder can derive its internal pixel clock from an externally supplied clock, either through the EXTAL pin or through one of the DU_DOTCLKINx pins. Add corresponding clocks to the DT bindings. To retain backward compatibility with DT that don't specify the clock-names property, the functional clock must always be specified first, and the clock-names property is optional when only the functional clock is specified. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]> Reviewed-by: Ulrich Hecht <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2018-09-24dt-bindings: display: renesas: lvds: Document r8a77990 bindingsLaurent Pinchart1-0/+1
The E3 (r8a77990) supports two LVDS channels. Extend the binding to support them. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Ulrich Hecht <[email protected]> Reviewed-by: Kieran Bingham <[email protected]>
2018-09-24dt-bindings: display: renesas: du: Document r8a77990 bindingsLaurent Pinchart1-0/+2
Document the E3 (r8a77990) SoC in the R-Car DU bindings. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Ulrich Hecht <[email protected]>
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