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2020-09-30drm/amd/amdkfd: Surface files in Sysfs to allow users to get number ofRamesh Errabolu2-2/+94
compute units that are in use. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Surface files in Sysfs that allow user to determine the number of compute units that are in use for a given process. One Sysfs file is used per device. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-By: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/amdgpu: Define and implement a function that collects number ofRamesh Errabolu2-0/+187
waves that are in flight. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-By: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: disable gfxoff temporarily for navy_flounderJiansong Chen1-0/+3
gfxoff is temporarily disabled for navy_flounder, since at present the feature caused some tdr when performing display operations. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: drop duplicated ecc check for vega10 (v5)Guchun Chen1-12/+7
The same ECC check has been executed in amdgpu_ras_init for vega10, prior to gmc_v9_0_late_init. v2: drop all atombios helper callings v3: use bit operation v4: correct inline comment, remove parity check statement v5: squash in build fix Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/display: add pipe reassignment prevention code to dcn3Dmytro Laktyushkin1-12/+49
Add code to gracefuly handle any pipe reassignment occuring on dcn3 hardware. This should only happen when new surfaces are used for an update rather than old ones updated. Fixes: 69fc1f4b976cea ("amd/drm/display: avoid dcn3 on flip opp change for slave pipes") Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: use function pointer for gfxhub functionsOak Zeng15-83/+155
gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/amdgpu: Prepare implementation to support reporting of CU usageRamesh Errabolu2-2/+6
[Why] Allow user to know number of compute units (CU) that are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/amdgpu: Clean up header file of symbols that are defined to be staticRamesh Errabolu1-5/+0
[Why] Header file exports functions get_gpu_clock_counter(), get_cu_info() and select_se_sh() that are defined to be static Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu: Use SKU instead of DID for FRU check v2Kent Russell1-11/+24
The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU variants (D131 or D134) until a more general solution can be determined. v2: Remove string-based logic, correct the VBIOS string comment Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu/swsmu/smu12: fix force clock handling for mclkAlex Deucher1-3/+5
The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313 Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: remove duplicate call to rn_vbios_smu_get_smu_version()Dirk Gouders1-1/+0
Commit 78fe9f63947a2b ("drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions") added a call to rn_vbios_smu_get_smu_version() to set clk_mgr->smu_ver. That field is initialized prior to the if-statement, already. Fixes: 78fe9f63947a2b (drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions) Signed-off-by: Dirk Gouders <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Sung Lee <[email protected]> Cc: Yongqiang Sun <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/powerplay: add one sysfs file to support the feature to modify gfx ↵Xiaojian Du7-2/+118
clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu: add new trace event for page table updateShashank Sharma2-2/+52
This patch adds a new trace event to track the PTE update events. This specific event will provide information like: - start and end of virtual memory mapping - HW engine flags for the map - physical address for mapping This will be particularly useful for memory profiling tools (like RMV) which are monitoring the page table update events. V2: Added physical address lookup logic in trace point V3: switch to use __dynamic_array added nptes int the TPprint arguments list added page size in the arg list V4: Addressed Christian's review comments add start/end instead of seg use incr instead of page_sz to be accurate V5: Addressed Christian's review comments: add pid and vm context information in the event V6: Re-sequence the variables (put pid and ctx_id first) Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu: fix incorrect commentGuchun Chen1-1/+1
It should be one copy-paste typo. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu: restore proper ref count in amdgpu_display_crtc_set_configJean Delvare1-1/+1
A recent attempt to fix a ref count leak in amdgpu_display_crtc_set_config() turned out to be doing too much and "fixed" an intended decrease as if it were a leak. Undo that part to restore the proper balance. This is the very nature of this function to increase or decrease the power reference count depending on the situation. Consequences of this bug is that the power reference would eventually get down to 0 while the display was still in use, resulting in that display switching off unexpectedly. Signed-off-by: Jean Delvare <[email protected]> Fixes: e008fa6fb415 ("drm/amdgpu: fix ref count leak in amdgpu_display_crtc_set_config") Cc: [email protected] Cc: Navid Emamdoost <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: make two symbols staticJason Yan1-2/+2
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2740:6: warning: symbol 'dce110_set_cursor_position' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2785:6: warning: symbol 'dce110_set_cursor_attribute' was not declared. Should it be static? Reviewed-by: Harry Wentland <[email protected]> Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: make get_color_space_type() staticJason Yan1-1/+1
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c:180:26: warning: symbol 'get_color_space_type' was not declared. Should it be static? Reviewed-by: Harry Wentland <[email protected]> Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29amd/drm/display: avoid dcn3 on flip opp change for slave pipesDmytro Laktyushkin1-3/+40
At the moment on flip opp reassignment does not work in all cases for non root pipes. This change simply makes sure we prefer pipes not used previously when splitting in dcn3. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: disable stream if pixel clock changed with link activeChiawen Huang1-1/+0
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by: Chiawen Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: [FW Promotion] Release 0.0.35Anthony Koo1-6/+126
[Header Changes] - Definition for retaining ABM settings during disable - Addition of some new AUX interface definitions - Addition of some outbox definitions Signed-off-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Revert check for flip pending before locking pipesAric Cyr4-14/+13
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Add debug param to force dio disableWesley Chalmers2-0/+4
[WHY] At the moment, some tests are failing because cur_link_settings is invalid. As a workaround, add an option to force dio disable. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Calc DLG from dummy p-state if full p-state unsupportedJoshua Aberback3-41/+80
[Why] Currently, when full p-state changes are not supported, DLG parameters are calculated for no p-state support at all. However, we are required to always support dummy p-state changes, so we should instead calculate DLG based on dummy p-state latency when full p-state is unsupported. This behaviour already exists for DCN2. [How] - move DLG calculation inside WM calculation - if p-state unsupported, do not recalculate for set A, instead copy from set C, and perform DLG calculation with dummy p-state latency Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: disable stream if pixel clock changed with link activeChiawen Huang2-4/+60
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by: Chiawen Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Ensure all debug bits are passed to fwWyatt Wood1-2/+3
[Why] Some debug bits are not being copied from driver to fw. [How] Copy debug bits properly. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoderEric Bernstein2-10/+18
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/display: Update NV1x SR latency valuesAlvin Lee1-2/+2
[Why] HW team measurement requires updating values [How] Update bounding box values Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitorsEvan Quan1-31/+12
Revert the guilty change introduced by the commit below: drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: fix a warning in amdgpu_ras.c (v2)Alex Deucher1-1/+4
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(&adev->dev->kobj, &group); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ v2: just print an error for sysfs group creation failure Acked-by: Nirmoy Das <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: clean up ras sysfs creation (v2)Guchun Chen1-56/+31
Merge ras sysfs creation together by calling sysfs_create_group once, as sysfs_update_group may not work properly as expected. v2: improve commit message Signed-off-by: Guchun Chen <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: stop data_exchange work thread before resetTiecheng Zhou1-0/+5
In FLR routine, init_data_exchange is called at reset_sriov while fini_data_exchange is not. This will duplicating work thread. So call fini_data_exchange before reset for SRIOV Signed-off-by: Tiecheng Zhou <[email protected]> Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: Implement new guest side VF2PF message transaction (v2)Bokun Zhang3-124/+198
- Refactor the driver code to use amdgpu_virt_read_pf2vf_data and amdgpu_virt_write_vf2pf_data instead of writing all code in one function (which is the old amdgpu_virt_init_data_exchange) - Adding a new transaction method for VF2PF message between host and guest driver. Guest side will periodically update VF2PF message in the framebuffer. In the new header, we include guest ucode information, guest framebuffer usage, and engine usage - Clean up the old macros since they will cause compile error if the new transaction method is used v2: squash in build fix Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: Update VF2PF interfaceBokun Zhang2-20/+285
- Update guest side VF2PF interface header file Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/include: add PP_FEATURE_MASK comments (v3)Ryan Taylor1-0/+28
Documents PP_FEATURE_MASK enum. Provides instructions on how to use ppfeaturemasks. v2: improve enum definitions and add kernel command line parameters to ppfeaturemask instructions v3: fix alignment issues Signed-off-by: Ryan Taylor <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: disable sienna chichlid UMC RASJohn Clements1-2/+2
disable UMC RAS in lieu of stability issues on certain sku Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: add an auto setting to the noretry parameterAlex Deucher2-3/+32
This allows us to set different defaults on a per asic basis. This way we can enable noretry on dGPUs where it can increase performance in certain cases and disable it on chips where it can be problematic. For now the default is 0 for all asics, but we may want to try and enable it again for newer dGPUs. Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: store noretry parameter per driver instanceAlex Deucher16-10/+40
This will allow us to have different defaults per asic in a future patch. Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu/display: fix CFLAGS setup for DCN30Alex Deucher1-2/+16
Properly handle clang and older versions of gcc. Fixes: e77165bf7b02a3 ("drm/amd/display: Add DCN3 blocks to Makefile") Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: Remove some useless codeEmily.Deng4-30/+0
Signed-off-by: Emily.Deng <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd: Skip not used microcode loading in SRIOVJingwen Chen6-13/+29
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd/pm: Skip use smc fw data in SRIOVJingwen Chen1-29/+32
smc fw is not needed in SRIOV, thus driver should not try to get smc fw data. Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd/display: fix return value check for hdcp_workFlora Cui1-1/+1
max_caps might be 0, thus hdcp_work might be ZERO_SIZE_PTR Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.Jiansong Chen1-8/+2
Remove gpu_info fw support for sienna_cichlid etc., since the information can be retrieved from discovery binary. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22gpu/drm/radeon: fix spelling typo in commentsWang Qing1-1/+1
Modify the comment typo: "definately" -> "definitely". Signed-off-by: Wang Qing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/display: optimize code runtime a bitBernard Zhao1-9/+1
In the function dal_ddc_service_query_ddc_data, get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. This change is to make the code run a bit fast. Signed-off-by: Bernard Zhao <[email protected]> Changes since V1: *get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. Link for V1: *https://lore.kernel.org/patchwork/patch/1309014/ Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd: fix typoes in commentsBernard Zhao8-14/+14
Change the comment typo: "programm" -> "program". Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/radeon: fix typoes in commentsBernard Zhao3-4/+4
Change the comment typo: "programm" -> "program". Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amdgpu: Add initial kernel documentation for the amd_ip_block_type ↵Ryan Taylor2-25/+71
structure. v3 Added IP block section to amdgpu.rst. Added more documentation to amd_ip_funcs. Created documentation for amd_ip_block_type. v2: Provides a more detailed DOC section on IP blocks v3: Clarifies the IP block list. Adds info on IP block enumeration. Signed-off-by: Ryan Taylor <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amdgpu: fix hdp register access errorStanley.Yang1-1/+1
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: update driver if file for sienna cichlidLikun Gao2-3/+3
Update driver if file for sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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